TW200845011A - Systems for complete word line look ahead with efficient data latch assignment in non-volatile memory read operations - Google Patents

Abstract

Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored by adjacent cells. To account for the shift, compensations are applied when reading. When reading a selected word line, the adjacent word line is read first and the data stored in a set of data latches for each bit line. One latch for each bit line stores an indication that the data is from the adjacent word line. The selected word line is then read with compensations based on the different states of the cells on the adjacent word line. Each sense module uses the data from the adjacent word line to select the results of sensing with the appropriate compensation for its bit line. The data from the adjacent word line is overwritten with data from the selected word line at the appropriate time and the indication updated to reflect that the latches store data from the selected word line. The efficient use of the data latches eliminates the need for separate latches to store data from the adjacent word line.

Description

200845011 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The specific embodiments of the present disclosure relate to non-volatile memory technology. Cross-reference the following application and incorporate it in its entirety by reference:

Man Mui et al. entitled "Complete Word Line Look Ahead With Efficient Data Latch Assignment in Non-Volatile Memory Read Operations" in "Non-volatile Memory Read Operations" US Patent Application No. _________ [Agent File Number SAND-01144US0], the case was filed on the same day. [Prior Art] Semiconductor memory devices have become more and more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrically erasable programmable read only memory (EEPROM) (including flash EEPROM) and electrically programmable read only memory (EPROM) are among the most popular non-volatile semiconductor memories. One example of a flash memory system uses a NAND structure that includes a plurality of transistors arranged in series between two select gates. The series of electrical crystals and the select gates are referred to as a NAND string. Figure 1 is a top plan view of a NAND string. Figure 2 is an equivalent circuit thereof. The NAND string shown in Figures 1 and 2 includes four transistors 10, 12, 14 and 16 arranged in series between a first select gate 12 and a second select gate 22. Select gate 12 connects the NAND string 127827.doc 200845011 to bit line terminal 26. Select gate 22 connects the NAND string to source line terminal 28. The selection gate 12 is controlled by applying an appropriate voltage to the control gate 20CG via the selection line SGD. The selection gate 22 is controlled by applying an appropriate voltage to the control gate 22CG via the selection line SGS. Each of the transistors 10, 12, 14 and 16 includes a control gate and a floating gate to form the gate elements of a memory cell. For example, the transistor 10 includes a control gate 10CG and a floating gate 10FG. The electric crystal 12 includes a control gate 12CG and a floating gate 12FG. The transistor 14 includes a control gate 14CG and a floating gate 14FG. The transistor 16 includes a control gate 16CG and a floating gate 16FG. The control gate 10CG is connected to the word line WL3. The control gate 12CG is connected to the word line WL2, the control gate 14CG is connected to the word line wli, and the control gate 16Cg is connected to the word line WL0. It should be noted that although Figures 1 and 2 show four memory cells in the NAND string, the use of four transistors is only an example. A NAND string can have fewer than four memory cells or more than four memory cells. For example, some NAND strings will include 8 memory cells, 16 memory cells, 32 memory cells, and the like. The discussion herein is not limited to any particular number of memory cells within a nand string. A typical architecture for a flash using a NAND structure will include several NAND strings. An example of a related NAND type flash memory and its operation are provided in the following U.S. Patent/Patent Application, the entire contents of which are hereby incorporated by reference in its entirety, U.S. Patent No. 5,570,315, U.S. Patent No. 5,774,397. U.S. Patent No. 6,046,935, U.S. Patent No. 5,386,422, U.S. Patent No. 127, 827, filed No. PCT No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. Other types of non-volatile memory other than NAND flash memory can also be used in accordance with specific embodiments. In addition, a non-conductive dielectric material can be used to store charge in a non-volatile manner in place of a conductive floating gate. Such a unit is described in a paper by Chan et al., True Single Crystal Oxide Nitride Oeprom Device, IEEE Transactions on Electronics, Vol. EDL_8, No. 3, March 1987, No. To page 95, the entire contents of which are incorporated herein by reference. When programming an EEPROM or flash memory device, a programmed voltage is typically applied to the control gate and the bit line is grounded. The electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell rises, causing the memory unit to be in a stylized state. The floating gate charge and threshold voltage of the cell may indicate a particular state corresponding to the stored data. More information on stylization can be found in U.S. Patent Application Serial No. 1/379,608, filed May 2003, entitled "Self-pressurization Technology" and U.S. Application for July 29, 2003. Case No. 10/629,068, entitled "Extracted Processed Memory", both of which are incorporated herein by reference. The apparent charge offset stored on a floating gate or other charge storage region may occur due to an electric field coupling based on the charge stored in the adjacent floating gate. This floating gate-to-floating gate coupling phenomenon is described in U.S. Patent No. 5,867,429, the disclosure of which is incorporated herein by reference. Although not all, the floating gate-to-floating gate coupling phenomenon is extremely significant between sets of adjacent memory cells that are stylized at different times. 127827.doc 200845011 For example, it is possible to stylize the first-memory unit. A charge level corresponding to the eve, the, and the bake material is added to its floating gate. Subsequently, one or adjacent memory cells are programmed to add a charge bit corresponding to a set of data to its floating gate. After stylizing one or more of the adjacent memory cells, the charge level read from the first memory cell can be = because of the charge on the adjacent memory cell The effect of the face-to-face first element is different from the charge level at the time of stylization.

The rendition from the adjacent heart unit can shift the apparent charge level read from the selected memory unit to a number sufficient to cause erroneous reading of the stored data. The size of the memory unit is continuously reduced, and it is expected to be natural. The stylized and erased threshold voltage distribution will increase due to short channel effects, larger oxide thickness/combination ratio changes, and more channel dopant fluctuations, thereby reducing the available spacing between adjacent states. Reducing the space between the word lines and between the bit lines will also increase. (4) The floating gates of the floating _ pole to the floating gates have a growing multi-state device, because of the permissible allowable threshold. The range of the electrical and the prohibited range (the range between the two different threshold voltage ranges representing different memory states) is more narrow than in the binary device. Therefore, the 'floating gate to floating gate junction may cause the memory cell unit to be shifted from an allowable threshold voltage range to a forbidden range. It has been proposed to compensate for the float during the read operation. In addition, U.S. Patent Application Serial No. 11/09-49 describes a technique for applying different read reference times to a selected word line based on the state of an adjacent cell on a neighboring word line. In addition, U.S. Patent Application Serial No. 11/377,972, a 127,827.doc 200845011, directly applies a compensation voltage to an adjacent memory cell when reading a selected memory cell to compensate for the memory device from the adjacent memory cell. Floating gate coupling technology. The entire contents of the above-identified patent applications are hereby incorporated by reference. SUMMARY OF THE INVENTION The apparent charge offset stored in a charge storage region (eg, a floating gate) in a non-volatile storage element may occur due to the electric field coupling based on the stored energy of the adjacent cells. . To account for this offset, a complement is applied at the time of reading based on the different possible states that adjacent memory cells may have been programmed. When a selected word line is read, the adjacent word line is read first. In the future, the data of the memory unit of the self-phased sub-line is stored in the flash of the group of materials for each element line. For flash memory - flash storage This data is from the - sub-line of the $ sub-line. The selected word line is then read. Based on the different possible states of the cells on the adjacent sub-line, the target is compensated differently when the item is taken at the selected word line. Based on the appropriate compensation for each element line (4) Do not select the result of the specific sensing operation for the bit line. Each element: under-sensing, modulo, and using the data stored in the data latch for the adjacent word line to select the result of the appropriate sensing operation. Respond to appropriate sensing operations - use data from the selected word line to overwrite the adjacent character ‘ 35H when overwriting the material, update the indication to reflect the

These lines of the meta-line + I are storing data from the selected word line. Thus, a right-handed R is provided for the data latches, thereby minimizing the wafer space in which the compensation sensing is applied. In the case of a non-volatile storage device, a second non-volatile storage element is read by a response-required reading of 127827.doc 200845011 to obtain a second non-volatile storage element, which is taken from the second storage element. The data stored in the flash data of the group data and stored in the questions is read from a portion of the H volatile storage element: the reading is followed by reading the first non-volatile storage element. a plurality of sensing operations to read the first non-volatile storage element. Each sensing operation corresponds to a different data that may be stored in the flash for the second material element. (4) The data should be flashed in the group The sensing operation of the sensing device from the data of the first non-volatile (four) storage component during which the first storage element is conducted and the data is indicative of the first non-volatile storage component. Using the predetermined data to replace the data from the second storage element in the flash of the set of data. If the data from the second stored one is replaced, the expected use in the set of data is from the Μ - non-volatile Storage element a second indication to replace the one indication. To read the non-volatile storage in another embodiment comprises storing data from the -second=the-group non-volatile storage element as a - a portion of the word line - the second set of non-volatile components - the read operation. The first group and the second group communicate with a plurality of bit lines. The data includes the first group of sub And a set of data of each storage element is stored in a set of data flashes for the corresponding bit line. The second set is read using a plurality of sensing operations of the state. Each of the sensing operations associated with the first group is associated with a set of potential data stored by each of the data flashes of the group data. For the = one line of the second group Whether the storage element is conducted during the sensing operation, the shirt sensing operation is associated with the information stored in the group of lean materials in the storage line. If the second group comes Frost 传导 During conduction during a specific sensing operation, the predetermined asset is used to overwrite the storage element for the first group The set of data of the various embodiments may include non-volatile storage elements and management circuitry, such as management circuitry, in communication with the storage elements to perform various of the described procedures: The circuitry may include, for example, control circuitry (eg, including a state) [System], column row decoder, item fetch/write circuit and/or a controller element [Embodiment] 'The memory unit can be used to store data represented by analog or digital form through the control unit threshold. The possible threshold voltage range of the memory unit can be divided into a plurality of ranges representing different memory states. For example, two thresholds can be used to establish two memory states, which specify logic 1 and 0. Typically, at least a voltage breakpoint level is established to divide the memory window into two ranges by applying a predetermined, fixed voltage corresponding to the reference threshold voltage level (eg, When the reference voltage is read to the cell gate to read the cell, the source/no-pole conduction state is established by comparing the conduction current with a breakpoint level or reference current. If the current is high and the reference current level is determined, the unit is determined to be turned on, and is in the k-like state. If the current is less than the reference current level, then the single = off and in other logic states is determined. In a NAND flash memory example T, the threshold voltage is negative after erasing the memory cell and is defined as a logic one. The threshold voltage is positive after a stylized operation and is defined as a logic zero. When the threshold voltage is negative and by applying 〇¥ to the control gate 127827.doc -12- 200845011 s 5: When capturing, the δ hex element will be turned on to indicate that the logic 1 is being stored. The voltage is positive and a try is taken by applying a volt to the control closed pole. 'The seven memory cells will not turn on to indicate that the logic is being stored - the memory cell can also be utilized by using more than two threshold voltages. Scope representation • 丨 ° 己 L 体 体 体 健 健 健 健 健 健 健 健 健 健 健 健 健 健The threshold voltage can be viewed as the desired memory state and the number of voltage breakpoint levels used to resolve the individual states. For example, if four states are used, then _ 胄 four threshold voltage ranges 'which represent four different memory states, which specify data values 11, 10, 01, and 00. The specific relationship between the stylized memory 7L(4) data and the voltage range of the single i3516 depends on the data encoding scheme used by the memory cells. For example, U.S. Patent No. 6,222,762, filed on Jun. 13, 2003, and U.S. Patent Application Serial No. 10/461,244 "Tracking Unit for Memory Systems" Description for Multi-State Flash Memory Various data encoding schemes for volume units, both of which are incorporated herein by reference. Lu Figure 3 illustrates an exemplary array 100 of NAND strings 50, such as a map! The strings shown in 2 are shown. Along the rows, a bit line 27 is coupled to one of the bit line select gates of the NAND strings for the row. Along the columns of NAND strings, a source line 29 can be connected to all of the source terminals 28 of the source 'pole selection gates of one of the Nand strings. The memory cell array 1 is divided into a plurality of memory cell blocks. As is common to flash EEPROM systems, a block erase unit can be referred to as an erase block or a physical block. Each block may include a minimum number of memory cells that are erased together. In Figure 3, a block (e.g., block 3 〇) includes all cells connected to the _ group 127827.doc • 13- 200845011 shared word lines WL0 to WLi. Each block is generally divided into several pages. A page is often a minimal stylized or read unit, but can be programmed or read in more than one page in a single operation. The individual pages can be divided into a plurality of segments, the combination of which is stored as a minimum number of cells written once in a basic stylized operation. One or more gastric data is stored in a column of memory cells. A page can store one or more data segments. The data segment size is generally defined by a host system. One section includes user data and management information. The official information generally includes an error correction code (ECC) that has been calculated based on the segment user data. A portion of the controller (as described below) calculates the ECC when the data is being processed in the array and checks the ECC when reading data from the array. Alternatively, the ECC and/or other management materials are stored on such pages or even different blocks from the user data to which they belong. A user data section is typically 512 bytes, which corresponds to the segment capacity commonly used in a disk drive. Management data is typically an additional 16 to 2 bytes. A large number of pages form a block, wherever it is, for example, from 8 pages up to 32, 64 or more pages. In some embodiments, a column of ΝΑΝβ strings contains a block. Each memory cell block includes a set of bit lines forming a row and a set of word lines forming a column. In a specific embodiment, the bit line is divided into odd bit lines and even bit lines. The memory cells along a common word line and connected to the odd bit lines are stylized at one time, while the g-resonant cells along a common word line and connected to the even bit lines are in another Time stylized ("odd/even stylized"). In another embodiment, the memory cells are stylized along a word line for all bit lines within the block ("all bit threads 127827.doc -14 - 200845011"). In other embodiments, the bit lines or blocks may be decomposed into other groups (eg, left and right, more than two groups, etc.). FIG. 4 is a & The / write circuit is used to parallel capture and program a memory unit page. The memory device can include one or more memory dies or wafers 112. The memory die 112 includes a two-dimensional Memory cell array 100, control circuit 120, and read/write circuits 130A and 130B. In one embodiment, various peripheral circuit access memory arrays 100 are symmetrical on opposite sides of the array shown The manner is implemented to halve the access line and circuit density on each side. In other embodiments, various peripheral circuits may be included on only one side of the array. The read/write circuits 130A and 130B A plurality of sensing blocks 200 are included that allow for parallel reading A memory cell page is programmed. The memory array 1 can be addressed by word lines via column decoders 140A and 140B and by bit lines via row decoders 142A and 142B. In a typical embodiment, A controller 144 is included within the same memory device (eg, a removable memory card or package) as the one or more memory dies j 12 . Between the host and controller 144 via line 132 and Commands and data are transferred between the controller and one or more memory dies 112 via line 134. Control circuit 120 cooperates with the read/write circuits 130A and 130B to be in memory array 10 The memory operation is performed on the control circuit 120. The control circuit 120 includes a state machine 122, an on-chip address decoder 124, and a power control module 126. The state machine 122 provides wafer level memory operation control. The on-chip address decoder 124 is on the host. Or an address interface between a memory controller and a hardware address used by the decoders 140A, 140B, 142A, and 142B 127827.doc -15- 200845011. The power control module 126 controls In mind And power supplied to the word line voltage and the bit line of those during operation thereof.

Figure 5 is a block diagram of a different sensing block 2 (10) divided into a core portion (referred to as a sensing module 210) and a shared portion 22A. In one embodiment, there is a separate sensing module 21 for each bit line and a common portion 22 for a plurality of sensing modules 21A. In an example, a sensing block includes a shared portion 22 and eight sensing modules 210. The sensing modules in the group will be connected to the associated shared portion via a data bus 2〇6. Communication. For more information, please refer to U.S. Patent Application Serial No. 11/26,536, filed December 29, 2014, title, "Non-volatile memory and method for shared sense amplifier set processing", This is incorporated herein by reference. The sensing module 210 includes a sensing circuit 2〇4 that determines whether the conduction current in a connected bit line is above or below the m threshold level. Sensing mode = 210 also includes __bit, (4) 2()2, which is used to set a voltage condition on the connected bit line. For example, a predetermined state latched in the bit line latch 202 will cause the connected bit line (4) to - to specify a stabilizing state (e.g., Vdd). The group data latch 214 and a coupling portion 220 include a processor 212 coupled to the 1/0 interface, 216 between the set of ports 214 and the data bus 134. ^ $212 performs the calculation. For example, 'the function' is to determine the material stored in the memory unit to be tested and store the determined data in the group data. This group of data flash 214 is used to store the data bits of the two shirts in one reading. It is also used to store data bits imported from the data bus 134 during the program 127827.doc -16· 200845011. The data bits that are imported represent the data that is attempted to be programmed into the memory. The 1/〇 interface 216 provides an interface between the data latch 214 and the data bus 134. During reading or sensing, system operation is controlled by state machine 122 of Figure 4, which controls the supply of different control gate voltages to the addressed cells via word lines. As it progressively traverses various predefined control gate voltages corresponding to the various memory states supported by the memory, the sensing module 21 will

One of the voltages trips off and provides an output from the sense amplifier 21 to the processor 212 via the bus 206. At this time, the processor 212 determines the generated memory state by considering the (equivalent) trip event of the sensing group and the information about the control gate voltage applied from the state machine via the input line 2〇8. . It then calculates a binary code for the memory state and stores the generated data bits in the data query 214. In another embodiment of the core portion, bit (4) 2() 2 serves a dual task while acting as a latch for latching the output of sensing module 210 and also as a bit line latch as described above. The data latch stack 214 includes a data latch stack corresponding to the sensing module. In a particular embodiment, each sensing module has a set of data queries such that each of the meta-lines are associated with its own resource group. Two bit data are supported in each memory unit - in the specific embodiment, there are three data points for each bit line. Four data flashes can be used when storing three bit data in these units. In some embodiments, but not necessarily, the data flash is implemented as a shift register such that parallel assets stored therein are converted to serial data for data bus 134, and vice versa. Of course. 127827.doc -17· 200845011 should read/write all the data of the block from the beginning of the current scale. You can bind to form a block shift register, make or output - data Block. Specific words...take: by serial transport to make its data door* item fetch/write module library tune, '], and each of the poor material latches move data in/out out of the secondary material bus As if it were used for the entire read/write 5⁄4 memory. "Solid-fetch" write block-shift temporarily! In the case of month, parallel operation of one page of memory cells. Therefore, - 2 pairs of sensing modules 21G are operated in parallel. A page controller (not shown) conveniently provides control and timing signals to the parallel operational sensing modules. For details on the sense amplifiers (10) and (iv), please refer to the US application filed April 5, 2005. The specific application serial number 11\〇99,133, entitled "Light-compensation compensation during the reading operation of non-volatile memory", is hereby incorporated by reference in its entirety. Additional information on the structure and/or operation of the specific embodiments can be found in (1) U.S. Patent Application Publication No. 2004/0057287, filed on March 25, 2004, which is incorporated herein by reference. "Memory and Methods", (2) US Patent Application Publication No. 2004/0109357, published June 10, 2004, "Improved Sensing Nonvolatile Memory and Methods,: (3) December 16, 2004美国 US Patent Application No. 11/15, 199 "Improved memory sensing circuit and method for low voltage operation", inventor Raul-Adrian Cernea; (4) U.S. Patent Application Serial No. 11/099,133, filed on Apr. 5, 2005, entitled "In Non-volatile Memory Coupling compensation during the reading operation of the body, 'Inventor Jian Chen; and (5) US Patent Application No. 11/321,953, filed December 28, 2005, entitled "for 127827.doc - 18 - 200845011 Reference sense amplifier for non-volatile memory, inventor Siu Lung to catch with Raul-Adrian Cemea. All five patent documents of the patent documents listed above are hereby incorporated by reference in their entirety.

At the end of a successful stylized program, the threshold voltage of the memory cells should be within one or more threshold voltage distributions for the programmed memory cells or for the erased memory cells. - Threshold voltage: within the cloth range. Figure 6 illustrates the threshold voltage distribution for a memory group as each memory cell stores two bits of data. Figure 6 shows the -thic voltage distribution for the erased cell, the three threshold voltage distributions A, B&c for the programmed memory cells. In a specific embodiment, the threshold voltage in the E distribution is negative and the threshold pressure in the A, B & C distribution is positive. The different threshold voltage ranges of Figure 6 correspond to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory unit and the cell threshold voltage level depends on the data encoding scheme used by the units. In one embodiment, the data value is assigned to the threshold voltage range using a Gray code (gray c〇de) such that if the threshold voltage of a floating gate is incorrectly offset to its neighboring entity state, then only Will affect one yuan. However, in other concrete examples, Gray coding is not used. An example specifies "丨丨 to the threshold voltage range E (state E), "10" to the threshold voltage range a (state A), "〇〇" to the threshold voltage range B (state B), 0Γ, to the threshold voltage range c (state C). The four states are shown in Figure 6, but specific embodiments in accordance with the present disclosure may also be used with other binary or multi-state structures, including more or less Structure in four states. 127827.doc -19· 200845011

Figure 6 shows three read reference voltages Vra, Vrb and Vrc for reading data from a memory cell. By testing whether the threshold voltage of a given memory cell is above or below Vra, Vrb, and Vrc, the system can determine the state of the memory cell. If a memory cell is conducted by applying vra to its control gate, the memory cell is in state E. If a memory cell conducts under Vrb and Vrc and does not conduct under Vra, then the memory cell is in state A. If the memory cell conducts under Vrc and does not conduct under Vra and Vrb, then the memory cell is in state B. If the memory cell is not conducting under Vra, Vrb or Vre, then the memory cell is in state c. Figure 6 also shows three verification reference voltages Vva, Vvb and Vvc. When staging the memory cells to state A, the system tests whether the memory cells have a threshold voltage greater than or equal to Vva. When the memory cells are programmed to state B, the system tests whether the memory cells have a threshold voltage greater than or equal to Vvb. When the memory cells are programmed to state c, the system tests whether the memory cells have a threshold voltage greater than or equal to Vvc. By way of non-limiting example, in a specific embodiment,

Vra=0.0 V, Vr (four)·35 v, Vrc=2 6 v, Vva=(K5 v,

Vvb = 1.9 V and Vvc = 3.3 V. θ 6 also describes the king sequence stylization technique. In full sequence stylization, the memory unit is directly programmed from the erase state to any of the stylized states A or C. A group of memory cells can be erased first, so that all memory cells are erased. A series of programmable voltage pulses are then applied to the control idlers of the selected memory cells to program the memory cells directly into states A, B or C. In some 127827.doc 200845011 memory cells are being programmed from state E to state A, other memory cells are being programmed from state E to state b and/or from state E to state C. Figure 7 illustrates an example of a technique for two-pass stylized multi-state memory cells. The multi-state memory cells store two different pages of data: a page and an upper page. Describe four states. For state E, both pages store a 1 . For state A, the next page stores one and the previous page stores one. For state B, both pages store "0". For state C, the next page stores i and the previous page stores

Hey. Each state of the ia tube has been assigned a specific bit pattern, but different bit patterns may be specified. In the first pass of the stylization, the unit threshold voltage level is set according to the bit to be programmed in the lower logical page. If the bit is a logic "1", the threshold voltage is not changed because it is in an appropriate state due to an earlier erase. However, if the stylized bit is a logical "0", then the unit threshold is increased to state A, #arrow 25〇. This ends the first pass of stylization.隹一弟二二遇 Stylized Ding...Thinking m flat You are very eager to program the bits in the upper logical page to set. If the upper logical page bit is stored - the logical block does not have any stylization. Since it depends on the stylization of the next page bit, the single state (four) and other states or the _ of the A state, the second state is loaded with the upper page bit 1. The bit on the upper right page is to be - logical q, then offset the threshold voltage. If the first pass causes the unit to remain in the wipe, the 诼 诼 诼 状 恶 , , , , , , ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' Arrow 254 does not. As the first early squad has been programmed to state A, the program is further stylized in the first time, so that the threshold voltage is increased by 127827.doc -21 - 200845011. B, as indicated by arrow 252. The second pass is used to program the unit into a state designated to store a logical "〇" on the previous page without changing the next page. Figures 8A through 8C disclose a stylized non-volatile The program of the memory, by which any particular memory unit writes the specific memory relative to a specific page. First, the adjacent memory unit is written for the previous page to reduce the floating gate. To floating gate coupling. This technique can be referred to herein as the last first mode (LM) stylization. In the examples of Figures 8A through 8C, four data states are used, each cell storing two bits of data per memory cell. Erase status (4) Save data 11, status A stores data 01, status B stores data 1〇, and status C stores data. Other data can also be used to entity data status encoding. Each memory unit stores two logical data pages. Part of it. For reference purposes, the pages are referred to as the upper and lower pages, but other annotations may be given. State A is encoded to store the bits for the upper page and the storage is used for the next page, and state B is encoded. The storage bit 丨 is used for the upper page and the storage element 储存 is used for the lower page, and the state C is coded for storing the bit 〇 for the two pages. At the word line WLn, the page data under the memory unit is The first page in the first step shown in Fig. 8 is programmed, and the upper page of the unit is programmed in a first step as shown in Fig. 8C. If the next page of information is to retain data, it is used for one. Single-turn, the threshold voltage of the unit is still in the state E during the first step. If the next page of data is to be programmed to 〇, the threshold voltage of the memory unit is raised to the state B. The state B' is a middle State B, which has a lower than Vv_ verify level Vvb*. In one embodiment, after the 127827.doc -22-200845011 on the next page of the stylized memory unit, it will be stylized relative to its next page. An adjacent sibling cell at the adjacent word line WLn+. For example, at WL2 in the target! The page below the body unit can be programmed after the page below the memory unit at WL1. If the threshold voltage of the memory unit 1 after the memory unit 12 is programmed from state E to state B', then The floating gate coupling may increase the apparent threshold voltage of the memory cell - 12. The cumulative coupling effect on the memory cell at WLn will broaden the apparent threshold voltage distribution for the threshold voltage of the cells. • As shown in Figure 8B, the apparent threshold voltage distribution broadening can be corrected when stylizing pages on the word line of interest, as shown in Figure 8C. Figure 8C depicts the procedure for staging the upper page of the unit at WLn. A memory cell is in erased state E and its upper page bit is intended to remain at 丨, then the memory cell is still in state E. If the memory cell is in the state £ and its previous page data is to be programmed to zero, then the threshold voltage of the memory cell will rise to within the range of the case A. If the memory unit has a threshold voltage distribution b in the middle and the previous page data is to remain 丨, the memory unit will be programmed to the final shape. If the memory cell is in a middle threshold voltage distribution b and its upper page data is to become data 〇, the memory cell threshold voltage will rise to within the range of state C. Figure 8-8 to 8€: The program shown reduces the floating gate coupling because only the page stylization on the adjacent memory cells affects the apparent threshold voltage of a given 5 kb body. An alternative state coding example of this technique moves from intermediate state B to state c on the previous page dataset 1 and moves to state B on the previous page data system. Although Figure 8 provides an example of four data states and two data pages, the concepts are applicable to embodiments having more or less than four states and different page counts. 127827.doc -23- 200845011 Figure 9 is a timing diagram depicting (iv) signal behavior of a non-volatile memory system during a read or verify program iteration. Each of the processes of the program of Fig. 9 represents a single-sensing operation using the memory of each unit. If the memory such as money is “糸 binary memory unit”, the program of Figure 9 can be executed once. If the memory unit has four states (for example, multi-state memory cells of e, A, B, and . The pin memory unit performs the procedure of FIG. 9 three times (three sensing operations), etc., and generally, during the (four) fetch and verify operation, the selected word line is connected to the read reference voltage Vegr, which The level is specified for each read and test operation to determine whether the phase voltage of one of the phase memory cells has reached this level. After applying the word line voltage, the conduction current of the memory cell is measured to Determining whether to respond to a voltage applied to the word line to turn on the memory cell. If the measured conduction current is greater than a specific value, it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the memory cell The threshold voltage. If the measured conduction current is not greater than the specific value, it is assumed that the memory unit is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory unit. There are many methods to The conduction current of a memory cell is measured during a read or verify operation. In one example, the conduction current of a memory cell is measured according to the discharge rate of a dedicated capacitor in the sense amplifier. In another example The conduction current of the selected memory cell allows (or does not allow) the NAND string including the memory cell to release the bit line charge. The charge on the bit line is measured after a period of time to see if it has been discharged. Figure 9 shows #5 Tiger SGD, wl-unsel. WLn+1, wxn, SGS, 127827.doc -24 - 200845011

Selected BL, BLCLAMP, and Source start at Vss (approximately volts). The SGD system selects the gate selection line of the gate on the drain side. The source side of the SGS system selects the gate selection line of the gate. WLn selects the word line for reading/verification. WLn+ is the unselected word line of the adjacent word line of the WLn汲 side. WL_unsel indicates other unselected word lines other than the adjacent character line on the bungee side. Selected BL is the bit line selected for reading/verification. Source is the source line for these memory cells (see Figure 3). BLCLAMP is an analog signal that sets the bit line at time t1 when charging from the sense amplifier, SGD rises to Vdd (eg, approximately 3.5 volts), and the unselected word lines (WL_unsel) rise to VREAD (eg, approximately 5.5 volts), the drain side adjacent word line (WLn+Ι) is raised to VREADX, and the selected word line WLn is raised to Vcgr for a read operation (eg, Vra, Vrb, or Vrc) or a verify level (eg, Vva, Vvb, or Vvc) for a verify operation, and BLCLAMP is raised to a precharge voltage to precharge the selected bit line Selected BL (eg, to approximately 0.7 V). The voltages Vread and VreadX are used as transfer voltages because they cause the unselected memory cells to be turned "on" (either physical or threshold) and used as pass gates. At time t2, BLCLAMP is reduced to Vss, so the NAND string can control the bit line. Also at time t2, the source side selection gate is turned on due to the rise of SGS (B) to Vdd. This point provides a path for dissipating the charge on the bit line. If the threshold voltage of the memory cell for reading is greater than Vcgr or the verify level applied to the selected word line WLn, the selected memory cell will not be turned on and the bit line will not be discharged, such as a signal line. 260 is shown. If the threshold voltage of 127827.doc -25· 200845011 for reading the memory cell is less than Vcgr or less than the verify level applied to the selected word line WLn, the memory cell selected for reading will be turned on. (Conditional) and the bit line voltage will dissipate as indicated by signal line 262. After time t2 and at some point prior to time t3 (as determined by the particular implementation), the sense amplifier determines if the bit line has consumed a sufficient amount. Between t2 and t3, BLCLAMP rises to cause the sense amplifier to measure the evaluated BL voltage and then decrease. At time 〇, the signals shown

Will be reduced to Vss (or another value for standby or reply). It should be noted that in other embodiments, the timing of some of the signals may be changed (e.g., the offset is applied to the apostrophe of the neighbor). For further details, including an explanation of the conduction current of a unit by means of a discharge rate of a dedicated capacitor in the sense amplifier, see U.S. Patent Application Serial No. 11/377,972, to the name of N. Coupling compensation system for performing read operations on the storage", the entire contents of which are incorporated herein by reference.

As previously described, the floating gate face may be erroneous during a read operation. The charge stored on the floating gate of the memory cell can be due to the charge associated with the charge stored in the floating gate or other charge region of the adjacent memory cell (eg, a dielectric charge storage region). : Apparent offset. Although theoretically derived from the floating gate of the I 1 · memory cell of the charge on the floating gate of the - memory cell in the memory array: to any other - 1 pole in the array, the effect is for adjacent memory Single and pay for the Lord. Adjacent memory cells may be included in adjacent memory cells on the same word line as the phase 127827.doc -26 - 200845011

Coupled effectively to the target memory cell, an adjacent memory cell portion will pass through the electric field coupling to cause an apparent shift in the threshold voltage of the target memory cell. After stylization, the apparent threshold voltage of a memory cell can be shifted to a degree after stylization, so that it is expected to be used for the read-only reference voltage of the memory bank in the desired memory state. , it will not turn on and off (conduction).

The meta-lines (WL1, WL2, WL3, etc.) are sequentially programmed such that at least one data is obtained after the previous word line (WLn) is programmed (the cells of the word lines are placed in their final state) The page is stylized within an adjacent word line (WLn+1). This stylized mode causes an apparent voltage shift of the memory cell after the staging due to the floating gate coupling. For each character line to be programmed except for the last word line of the NAND string, an adjacent word line is programmed after completion of the stylization of the word line of interest. The negative charge added to the floating gate of the memory cell on the adjacent, later stylized word line increases the apparent threshold voltage of the memory cell on the word line of interest. Stylization can also begin with the word line adjacent to the gate on the drain side and 127827.doc •27- 200845011 Select the gate advance to the source side in turn. In this case, the floating gates may similarly affect the apparent threshold voltage of the memory cells. Figure ίο graphics explain the concept of floating gate coupling. Figure 10 depicts adjacent floating gates 302 and 304 on the same NAND string. Floating gates M2 and 3〇4 are located above NAND channel/substrate 306 having source/drain regions 308, 3 10 and 312. The system above the floating gate 302 is connected to the control gate 314 of the word line WLn. Connected above the floating gate 3〇4 is connected to the control gate 316 of the word line WLn+1. In some cases, the control gates form the word lines, and in other cases, the characters are formed separately and then connected to the control gates. Although the floating gate 3〇2 can affect the coupling from a plurality of other floating gates, the effect from a neighboring memory cell is shown for simplicity. Figure 1A shows three consumable components, which are provided from the floating gates neighbors to the floating interpoles ··H, and the Cr° component rl is between the adjacent floating gates (302 discs 3〇4) The ratio is calculated as the sum of the capacitances of the adjacent floating gates divided by the sum of all capacitive couplings of the floating gates 03 to all of the pots and their electrodes around them. The component r2 is the coupling ratio between the adjacent floating M ▲ $木3 02 and the non-polar side adjacent control gate 3 16 , and is used as the > _ and as the sweat gate 302 and the control gate 316 Calculated by the sum of the right-handed thumps of the oceanic gate 3 〇 2 to the moon - /, all other electrodes around.八 栳 amp &, private knife ^ system control gate coupling ratio and as? The sum of the capacitive couplings of the eight electrodes and the :i: 斟座-〇" corresponding to the control gate 316 are moved to the surrounding u and are divided by the dirt. The sum of all the capacitive couplings of the eight electrodes is shown in Figure 11. Stylized—the adjacent column of the column memory element (eg WLn) 127827.doc -28- 200845011 (WLn+l) before (solid curve) and after (dashed curve) the apparent threshold voltage of the column memory cell Distribution. Each distribution is widened by the addition of a negative charge to the floating gates of the memory cells of adjacent word lines. Because of the floating gate coupling, a later stylized memory cell on WLn+Ι The negative charge will raise the apparent threshold voltage of a memory cell connected to WLn of the same bit line. Distributions 320 and 322 represent the state before and after the stylized adjacent word line WLn+Ι, respectively. A unit of selected character line WLn under A. Distributions 324 and 326 represent the units of WLn in state B before and after stylized WLn+1, respectively. Distributions 328 and 330 represent after stylized WLn+Ι, respectively. The unit of WLn in state C. Because the distribution is widened, it may be erroneously Taking the memory unit in an adjacent state, the memory unit at the upper end of each distribution may have an apparent threshold voltage above a corresponding read comparison point. For example, when the reference voltage Vrb is applied, it is programmed to The particular memory cell of state A may not be sufficiently conductive due to its apparent threshold voltage offset. These cells may be erroneously read as being in state B, causing a read error. The later stylized unit may also affect Apparent threshold voltages connected to WLn memory cells of different bit lines, such as those connected to adjacent bit lines. Figure 12 is a graphical depiction of some of the threshold voltages shown in Figure 11. One of the apparent offset reading techniques. When reading the data on the word line WLn, the data of the word line WLn+Ι can also be read and if the data on the word line WLn+Ι has interfered with The data on WLn is used by the WLn read program to compensate for the interference. The state or charge level of the memory cells at the word line WLn+Ι can be determined to select the appropriate read reference voltage for reading. Take the word line 127827.doc -29- 200845 011 WLn individual memory cell. Describes the individual read reference voltage of WLn read based on the state of an adjacent memory cell at word line WLn+1. In general, the normal read reference voltage Vra, Different offsets of Vrb and Vrc (for example, 〇V, ο, νv, 0·2 V, 0·3 V). The sensing results at different offsets are used as a memory on an adjacent word line. The functions of the cells are selected as a function of the state of the cells. The memory cells at the word line WLn are sensed using respective read reference voltages of the different read reference voltages including the different offsets. For a given memory cell, the result of sensing at one of the read reference voltages can be selected based on the state of an adjacent memory cell at the word line. The read reference voltages Vra Vrb and Vrc can be used when reading the word line WLn+1. In other embodiments, different read reference voltages can be applied at WLn+i. In some embodiments, the read operation for WLn+1 determines the actual data stored at WLn+1. In other implementations, the read operation for WLn+1 only determines the charge level of the individual's. These charge levels may or may not accurately reflect the data stored at WLn+Ι. In some embodiments, the number of levels and/or levels used to take WLn+Ι may not be exactly the same as the number of levels and/or levels used to read WLn. In some embodiments, an approximation of the oceanic threshold may be sufficient for correction purposes. In a particular embodiment, the read result at WLn+Ι can be stored in question 214 at each bit line for use in reading the heart. The interest word line WLn is read at the normal read reference voltage level, Vrb 127827.doc • 30- 200845011 and Vrc, without compensating for any coupling effects. The read results at the normal reference levels are stored in the latches that have previously determined that the adjacent cells in WLn+Ι are in the bit line of the memory cell of state E. For other bit lines, the data is ignored. Another read operation is performed at word line WLn using one of the read reference voltages, the first set of offsets. For example, the reader can use Vral (Vra+0.1 V), Vrbl (Vrb+0.1 V), and Vrcl (Vrc+0.1 V). The result of storing the reference values is used to store the bit line of the memory cell in which the adjacent memory cell is in state A at 1^+1. Ignore data for other bit lines. The word line WLn is read again under a second set of offsets using the read reference levels Vra2 (Vra+0.2 V), Vrb2 (Vrb + 0.2 V), and Vrc2 (Vrc+0.2 V). The results are stored for use in the latch of the bit line of the memory cell where the adjacent cell at WLn+1 is in state B. Ignore the information used for other bit lines. Using the reference levels Vra3 (Vra+0.3 V), Vi*b3 (Vrb+0.3 V), and Vrc3 (Vrc+0.3 V), a final read is performed on the word line WLn under a third set of offsets. The results are stored for the bit line of the memory cell where the adjacent cell is in state C at WLn+Ι. In some embodiments, no offset is used at Vra because of the greater natural boundary between state E and state A. Such a specific implementation is shown, for example, in Figure 12, in which a single read reference voltage Vra is described under state A level. Other embodiments may also use offsets for this level. The program of Figure 12 can be used to restore data or as an initial read program. The different offsets of the normal read reference voltages can be selected as a function of the state of a memory cell on adjacent word lines. For example, a set of offset values may include a 0 V offset, which corresponds to an adjacent unit in state E, a 127827.doc -31 - 200845011 0.1 V offset, which corresponds to an adjacent in state A The cell, a 2 V offset, which corresponds to an adjacent cell in state B, and a -3 v offset, which corresponds to a neighboring cell in state d. These offset values will vary depending on the implementation. In a particular embodiment, the offset values are equal to the number of apparent threshold voltage offsets resulting from the stylization of a neighboring unit to a corresponding state. For example, 0.3 V may represent the apparent threshold voltage offset of the cell at WLn when a neighboring cell of milk (4) is programmed to state C after staging WLn. The offset values are not - (4) and the reference voltages are the same. For example, the offset values for the Vrb reference voltage may be 〇v, 〇丨v, 〇·2 V, and G.3 V', and the offsets for the Vre reference voltage may be 〇V, 0.15 V, 0.25 V, and 〇.35 V. In addition, the offset increments are not necessarily the same for every - state. For example, a set of offsets in a particular embodiment may include 0 V, (Μ V, 0.3 V, and 0.4 v for adjacent cells in states E, A, B, and C. The other is used to compensate for floating The gate coupling technique provides for compensating for a memory cell adjacent to a selected memory cell to reduce the coupling effect of the adjacent memory cell on the selected memory cell. One such embodiment includes verification The condition for applying the adjacent memory cell compensation later is set during the program. In such a specific embodiment, the transfer voltage (also referred to as vREAD) applied to WLn+ is applied from one of the other selected word lines. A typical value (for example) 6 V is reduced to, for example, 3 V. The voltage used during the verification phase of the stylization/verification operation is compared, which is applied by a higher voltage during the read operation performed on WLn. WLn+1 consists of. This compensation can include full/difference ΔVreadIEVreaM during reading WLn 127827.doc -32- 200845011 WLn+l)]-[VREAD (WLn+l during verification of WLn)] }. The advantage of using a lower VREAD value during verification is that it allows a reasonable V READ value to be applied later during the read operation while maintaining the desired AV READ °. If not using a value less than the normal VREAD value during verification, allow enough The necessary Vread value for AVread during reading will be, for example, 6 + 3 = 9 V, which will be a large voltage that may cause read disturb conditions. An example of such a later compensation setting is depicted in Figure 9 as applying VREADX to the drain side adjacent word line while other unselected word lines receive VREAD. In general, all unselected word lines will receive VREAD. In the particular embodiment of Figure 9, all unselected word lines will receive VreAD ' except for the neighbors on the drain side, while the neighbors on the extreme side will receive VreAdX. For the verification procedure from the source side to the drain side stylized memory cell, (in one embodiment) it is guaranteed that all memory cells on the word line WLn+Ι are written when the word line WLn is written. In erased state (eg state E) (note: this is true for the full sequence, but not for LM. See above for explanation). The word line WLn+1 will receive a voltage level VreadX, where VreadX = VreadLA(E) (as described below). In a specific embodiment, VreadLA(E) is equal to 3.7V. In another embodiment, VreadX = Vread. Other values may be used in other embodiments. In various embodiments, different VreadLA(E) or VREADX values can be determined based on device characteristics, experimentation, and/or simulation. In a specific embodiment, the amount of compensation AVread required can be calculated as follows: 127827.doc -33- 200845011 AVread = (AVTn +1)---- 1 + r2 + (rl)(Cr)

Where ΔνΤη+l is the threshold voltage change of the adjacent memory cells on the drain side between the WLn time and the current time. AVTn+l and 1*1 are the root causes of the parasitic compilation of the word line to word line reduced by this method. AV RE AD is used to counteract the compensation of this effect. Figure 13 is a flow chart illustrating one of the embodiments of such a compensation technique. The program shown in Fig. 13 is applicable to the full sequence programming described above with respect to Fig. 6, in which the two bits of a logical page are stored in each unit and read and reported together. Figure 13 can also be used to read two pages of data stored in accordance with the techniques of Figure 7 or Figures 8 through 8C. At step 350, a read operation for the adjacent word line WLn+1 is performed. This operation may include applying regular read reference voltages Vra, Vrb, and Vrc to adjacent word lines. Other embodiments may use different reference voltages when reading WLn+Ι. Sensing results at different levels are used to determine the data stored in each unit at WLn+Ι. The results are stored at step 352. At step 354, a read operation is performed for the word line of interest WLn. This operation may include performing the procedure of Figure 9 using VreadX = VreadLA (C) (Figure 9). In a specific embodiment, VreadLA(C) = Vread. Therefore, all unselected word lines (see WL-unsel and WLn+Ι in Figure 9) receive VREAD. This point provides maximum compensation because the compensation is due to the difference between the VREAD value currently used for WLn+Ι during the read operation and the VREAD value used earlier during the verification phase of the stylization/verification. Decide. The compensation value compC can be determined as follows: compC=VREADLA(C)- 127827.doc -34- 200845011

VreadP = 5.5-3 = 2.5 V, where VREADp is the VREAD value used during stylization/verification. The results of step 354 are stored in the data latch of the bit line of the memory cell of state C (at step 350) that was previously stored at WLn+Ι in step 356. Therefore, the maximum compensation CompC is used for units whose top-side neighbors experience the highest threshold voltage change due to staging from state E to state C. It should be noted that these immersed neighbors were in state E during the stylization/verification of WLn, but are now in state c. The required compensation for φ in all cases is the change in the state of the infinite-side neighbor on the WLn+1 experienced between the WLn write time and the current read time of WLn. For the other bungee side neighbors, the bit line in state C is not currently detected, and the data read by this WLn using VreadLA(C) on WLn+1 is ignored. At step 358, a read operation is performed for WLn when the drain side adjacent word line WLn+1 receives VreadLA(B) (VreadX=VreadLA(B)); wherein VreadLA(C) 'VreadLA(B) is compared The value is closer to the VREADp used during stylized verification. Delivering a smaller compensation for the unit on the bungee side that is now in state B_. A compensation example is compB=VREADLA(;B)-

VreadP=4.9-3 = 1.9 V. Thus 'VreadLA(B) differs from VREADp by compB. In step 360, the results of the storage step 358 are used for the bit line of the memory cell where the adjacent memory cell is in state B at WLn+1. Ignore data for other bit lines. At step 362, a read procedure is performed for WLn of word line WLn+1 receiving VreadLA(A). (VreadX = VreadLA(A)), where VreadLA(B) is compared, the VreadLA(A) value is closer to the VREADp used during the stylization. Deliver a smaller amount of compensation for the 汲 127827.doc -35- 200845011 yuan for the neighbors on the bungee side. An example of the amount of compensation is compA=VREADLA(A)-VreadP=4.3-3=1_3 V. Thus 'VreadLA(A) differs from VreadP by compA. In step 364, the results of the storage step 362 are used for the bit line of the memory cell where the adjacent memory cells are in state A at WLn+Ι. Ignore data for other bit lines. At step 366, a read routine is executed for WLn that receives VreadLA(E) (VreadX = VreadLA(E)) for word line WLn+1, where VreadLA(E) is equal to the VREADp value used during stylization. This does not deliver any compensation that is suitable for the unit on the bungee side that is now in state E, since it is tied to the stylization/verification time. The number of compensations is compE=VREADLA(E)-VREADp=3-3 = 0.0 V. In step 368, the results of the storage step 366 are used for the bit line of the memory cell where the adjacent memory cells are in state E at WLn+Ι. Ignore the information used for other bit lines. During the procedure of Figure 13, adjacent bit lines will receive four voltages. However, each selected memory cell of the WLn being read utilizes or selects the results only when sensing at an appropriate voltage corresponding to the state of its adjacent cell at WLn+Ι. In various embodiments, different VreadLA(C), VreadLA(B), ^^人〇1^(eight), and \^八〇1^八(£) values may be determined based on device characteristics, experiments, and/or simulations. . For more information on the technique of Figure 13, please refer to U.S. Patent Application Serial No. 1 1/384,057 to Nima Mokhlesi, entitled "Read Operation of Non-volatile Storage with Coupling Compensation", the entire contents of which is This is incorporated herein by reference. Compensating the floating gate coupling effect during non-volatile memory read operations described in relation to both of the above techniques requires that a selected word line WLn be read during operation 127827.doc -36 - 200845011 Take reading ό 丄 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上Take the word 70 line WLn+i data. This may challenge the memory designer T's especially when trying to minimize the use of a specific compensation technology chip. Consider the memory unit that stores two bits of data. A. 1" body device. If the data from the adjacent word line WLn+Ι is selected

= Line WUl can be used during read operation '- Designer can choose to include enough shell gates to store data from word line |!^+1 and word WLn simultaneously in the selected word line during a read operation At the office. If each memory-unit stores two-dimensional data, each data line requires four data latches. Two data flashes can store two-dimensional data from the word line WLn+1 and the other two resources (4) can store two-dimensional data from the word line WLn. Similarly, three additional questions can be used for a three-bit device, four additional flashes for a four-bit device, and the like. Although this technique is more &amplitude, adding a data register to each 7L line for each unit of storage area number may be unacceptable in some embodiments due to space limitations. Figure 14 is a flow chart showing a method of reading a selected word line WLn in accordance with an embodiment. This example is presented for each unit storing a four-state device of two-dimensional data. Performing sensing of each memory cell at state A level (between states £ and 八), state B level (between states A and B), and state c level (between states B and C) . Compensation is provided during each quasi-sensing to account for the states of the four potential states of the adjacent memory cells at the subsequent stylized character line 翟!^+1. In order to select an appropriate sensing operation result for each memory unit, when the corresponding unit at 127827.doc -37 - 200845011 WLn is sensed, the 5 holes for the adjacent memory cells on the word line WLn+1 are stored for each bit. Yuan line. The processor for the bit line will use this information to select the appropriate sensing operation results. The data latch group for each element line is responsible for storing the data read from one of the memory cells of the selected word line. The same data latch group for each of the meta-lines will also store information about one of the memory cells of the character line adjacent to the selected sub-line. The additional data latch for each bit line operates as a flag, storing an information about the data. • The latch is storing an indication of the data for the selected word line or the adjacent word line. Thus, the technique of Figure 14 efficiently utilizes such data flashes for bit lines such that it is not necessary to use an additional set of questions to store data from adjacent word lines WLn =. In the example of Figure 14, the memory cells store two poor materials, so three data latches are used. Figure 14 presents an exemplary embodiment. It should be understood that the principles of the disclosure may be extended to embodiments in which each unit has the same number of bits (e.g., 3, 4 or more). In general, the number of data flashes required for each line is equal to one more number of bits stored in each memory unit. To identify the origin of the current stored data, use _ = an extra latch. In Fig. 14, data flash codes DL0 and Du are used for each bit line. • The data of the memory cells read from the corresponding bit lines are stored. A data sheet labeled DL2 is used to store the travel # — , 诚仔旗钻, which refers to whether the data currently stored in the data flash DL 〇 and D L1 corresponds to the data from the selected word line WLn or The data 对应 corresponds to the data from the character line WLn+1 adjacent to the selected word line. 127827.doc -38· 200845011 At step 400, the read operation begins by reading adjacent word line WLn+Ι. The adjacent word line can be read at three normal reference levels Vra, Vrb, and Vrc, as shown in FIG. In a particular embodiment, no compensation is applied when reading WLn+Ι. At step 402, the data values of the memory cells of the adjacent word line are determined. At step 404, the data values of the memory cells of the bit lines at word line WLn+1 are stored in a set of corresponding data latches DL0 and DL1 of the bit line. At step 406, the third data flash DL2 for each bit line is set to logic 0 to indicate that the data in data flashes DL0 and DL1 corresponds to data from a memory cell at WLn+Ι. At steps 408 through 422, a set of sub-reads at state A level (between states E and A) is performed for the selected word line WLn. The first sub-read at step 408 does not provide any compensation to account for the floating gate coupling. For example, if one uses the offset read reference voltage compensation technique illustrated in Figure 12, step 408 can include applying a read reference voltage Vra to the selected word line without using an offset. If one of the compensation techniques shown in Fig. 13 is used, the same read transfer voltage VreadP applied to WLn + 在 during WLn stylization verification is applied again to WLn + 感 at the time of sensing at WLn. For example, 'VreadLA(E) = VreadP can be applied to WLn+1, VREAD can be applied to each of the remaining unselected word lines, and Vra is applied to the selected word line WLn. At step 410, the processor of each bit line determines whether to update the data latch for the bit line. The processor does not change any of the values stored in the data latch for the bit line that is not conductive by the memory cells of the selected word line during the sub-read of step 408. For the bit line of the memory cell conduction, the processor determines whether the data latches DL0 and DL1 currently store data corresponding to the state 127827.doc -39- 200845011 state E. For example, if the data specified in Figure 6 is used, the processor determines if the flash is simultaneously storing a logic one. If the questions are not storing logic 11, then the processor does not change the value in the data latch. If the second latch is storing 11, the processor determines if the third data latch DL2 is storing a logical volume. A logic 0 indicates that latches DL0 and DL1 are storing data from WLn+1 and should be overwritten. In one embodiment, the processor may first check for flash DL2 and only check flash DL0 and DL1 when DL2 is storing a logic zero. If two conditions are satisfied for a conductive memory cell, DL0 and DL1 are set to predetermined data values for the erase state. The third data latch DL2 is set to 1 to indicate that DL0 and DL1 are now storing data for the data line WLn. A logic 1 within DL2 excludes overwriting latches DL0 and DL1 during subsequent sub-reads. At step 412, another state A sub-read is performed. At this time, a compensation is applied which corresponds to the adjacent memory cell at WLn+1 stylized to state A. For example, Vral including a Vra offset as shown in Fig. 12 can be used. In another embodiment, VreadLA(A) can be applied to WLn+1 and Vra can be applied to WLn. The processor at each bit line performs another logic sequence to decide whether to update the latch for the bit line having a conductive memory cell. If DL0 and DL1 do not store data for state A (for example, 10), no action is taken. If it is being stored, the processor determines if DL2 is storing a 0 to indicate that the WLn+ data is currently stored. If DL is set to 0, the processor overwrites DL0 and DL1 with the data for state E. The processor sets DL2 to 1 to indicate that the latches now store data from WLn. 127827.doc -40- 200845011 At step 416, a state A sub-read is performed at WLn, while a compensation based on the unit at WLn+1 stylized to state B is applied. For a conductive memory cell, the corresponding bit line processor determines whether DL0 and DL1 are storing data corresponding to state B (e.g., 00). If no, no action is taken. If so, the processor determines if DL2 is storing a logic zero. If no, no further action is taken. If DL2 is set to 0, the predetermined data for state E is used to overwrite DL0 and DL1 and DL2 is set to 1 to indicate that the latch is storing data from WLn. At step 420, a final sub-read at level A is performed. A compensation based on adjacent cells at WLn+Ι in state C is applied. For conductive memory cells, the corresponding bit line processor determines whether the latch is storing data for state 1 (e.g., 01). If the DL2 is set to 2, no action is taken. If DL2 is set to 0, the processor determines if DL2 is storing 0. If no, no further action is taken. If so, the processor overwrites DL0 and DL1 with the predetermined data for state E and sets DL2 to 1. At steps 424 through 444, for the word line WLn, a sub-read sequence at the state B level is performed. An initial sub-read at step 424 does not provide any ^ floating gate coupling compensation. This sub-reading result can be applied to the units at WLn+Ι - the neighboring unit is in the erased state E. Step 424 can include applying Vrb to WLn while applying a VREAD value to WLn+1, which is equal to the value used during the stylized verification for WLn (eg, VreadLA(E) = VreadP). For a conductive memory cell, the corresponding processor determines whether DL0 and DL1 for the bit line are storing data for state E. This step checks to determine 127827.doc • 41 200845011 The current sensed at WLn is the current that should be stored in the unit. If DL0 and DL1 do not correspond to state E, Bay does not take any action. If DL0 and DL1 match for state E, the processor determines that DL2 is storing a logic 0 to indicate that the data in DL0 and DL1 is for WLn+Ι and not for selected word line WLn. If DL2 is set to 1, the processor does not overwrite the data in DL0 and DL1. Logic 1 indicates that the DL0 and DL1 data are from WLn and should not be overwritten. If DL2 is set to 0, then at step 426, the processor overwrites the data in DL0 and DL1 with the data for the current group read. In this case, the processor sets DL0 and DL1 to the status A data (e.g., 10). The processor also sets DL2 to 1 to indicate that DL0 and DL1 are now storing data from the selected word line WLn and should not be overwritten during subsequent sub-reads at WLn. At step 428, a state B sub-read is performed at word line WLn while a compensation is applied based on the neighboring cells in state A at WLn+Ι. In a specific embodiment, Vrbl is applied to WLn. In another embodiment, Vrb is applied to WLn while VreadLA(A) is applied to WLn+Ι. For a conductive memory cell, the processor for the corresponding bit line determines whether DL0 and DL1 are storing data for state A. If no, no action is taken. If so, the processor determines if DL2 is storing logic 0. If not, no further action is taken on the bit line. If so, the processor overwrites the data in DL0 and DL1 with the data corresponding to state A. The processor also sets DL2 to logic 1. At step 432, WLn is read while a compensation is applied for the memory cells for an adjacent cell at WLn+1 to be in state B. If a memory bank 127827.doc -42- 200845011 is transmitted, the processor for the corresponding bit line determines whether DL0 and DL1 for the bit line are sharing state B data (for example, 00). If so, the processor determines if the data in DL0 and DL2 is from WLn (DL2 = 1) or WLn + 1 (DL2 = 0). If the data is from WLn+1, the processor overwrites DL0 and DL1 with the predetermined material for state A. The processor also sets DL2 to logic 1. If any of the conditions are not met, the processor does not change the contents of DL0 to D12. • At step 436, a state B sub-read is performed at word line WLn while a compensation is applied based on adjacent cells at WLn+Ι of state C. For a conductive memory cell, the processor determines if DL0 and DL1 are storing data for state C (e.g., 〇 1). If no, no action is taken. If so, the processor determines if DL2 is storing logic. If no, no action is taken. If so, the processor overwrites the data in DL0 and DL1 and sets DL2 to logic 1 using the data for state A. Steps 440 through 456 perform a set of sub-reads at state C read reference voltage levels. A first sub-read is performed at step 440, which does not include any floating gate coupling compensation. In a specific embodiment, Vrc can be applied to Vrc while VreadLA(E) is applied to WXn+1. The corresponding bit line processor for the conductive memory unit '' determines whether the latches DL0 and DL1 store the * data for the state E. If not, no action is taken at the bit line. If so, the processor determines if DL2 is storing logical buffers. If not, since the data latches share the data for WLn, they will not change. If DL2 is set to 〇, the corresponding processor overwrites the data in DL0 and DL1 with the data corresponding to state B (for example, 00). The processor also sets DL2 127827.doc -43 - 200845011 to 1 to indicate that DL0 and DL1 are storing WLn data. At step 444, a state C sub-read is performed while applying a compensation based on the neighboring cells in state A. Vrc can be applied at WLn or VreadLA(A) can be applied to WLn+1' while Vrc is applied at WLn+1. For the conduction unit, the bit line processor determines whether DL0 and DL1 are storing data for state A. If no, no action is taken. If so, the processor determines if DL2 is storing a logic 0. If no, no action is taken. If so, the processor overwrites latches DL0 and DL1 and sets DL2 to logic 1 using the data for state B. At step 448, a state C sub-read is performed while a compensation is applied to the neighboring cells for stylization to state B. Vrc2 can be applied to WLn or VreadLA(B) can be applied to WLn+1' while Vrc is applied at WLn. For the pilot unit, the processor determines if DL0 and DL1 are storing the data for state B. If not, the data latches are not disturbed. If it is storing data for state B, the processor determines if DL2 is storing a logic zero. If no, then • do not update the latches. If so, the processor overwrites the data in DL0 and DL1 with the predetermined data for state B. The processor also uses a 1 to overwrite the data in DL2 to indicate that the data in DL0 and DL1 is now on the word line WLn. ‘ At step 452, a final state C sub-read is performed while applying a compensation for adjacent memory cells at WLn+Ι in state C. In a specific embodiment, Vix3 is applied to WLn to effect compensation. In another embodiment, Vrc is applied to WLn while VreadLA(C) is applied to WLn+Ι. For the conduction unit, the processor determines whether DL0 and DL1 are being stored. 127827.doc -44 - 200845011 c information. If no, 刖 otherwise no action is taken. If so, the processor decides whether to store u or not, and does not take any action. If yes, then use the data for state B to overwrite DL〇 and DL1 and set DL2 to 1. - ^ 456 仃 - the final logical sequence. The bit line processor decides whether or not the third data for the any-bit line is not fixed. ☆ ☆ The bit line that is still stored in DL2 is in any shape at WLn

Do not conduct during any read period under ~' level. Accordingly, the memory cells are in the highest stylized state (ie, the state. The processors for the bit lines will be DU) and the data is used for the state (eg, logic 01). DL2 is then set to 1 to indicate that the data is now being stored for WLn. Figures 14A through 14B present one embodiment of the use of compensation when reading at state a. In another embodiment As previously described with respect to Figure (2), no compensation is used at State A level due to the naturally occurring boundary between the erased state and State A. Figures 15A through 15C depict a table in accordance with an embodiment. The data latch designation for a read operation is illustrated. Row 502 proposes various operations or sub-reads that are performed as part of the read operation for the selected word line WLn. Row 504 lists the data register DL0. - DL2, and for each individual operation within row 5 〇 2, the bit line processor responds to the logic executed by the corresponding operation. Lines 506, 508, 510, and 5 12 present the data gates after each operation Stored data values. Used for sub-reading at WLn State E, State A, State B, or State C is listed at the top of each row. State E (row 506) represents a 127827.doc -45- 200845011 bit line stored in its data latch group just prior to the corresponding operation in row 502. State E data (DL2 = 0) at WLn+1. State A indicates that a bit line stores state A data for WLn + 在 in its data latch group just before the corresponding operation in row 502 (DL2 = 0) State B indicates that a bit line stores state B data for WLn+Ι in its data group just before the corresponding operation in row 502 (DL2 = 0). State C indicates that one bit line is just in row 502. The state C data for WLn+Ι is stored in its data latch group before the operation (DL2==0). The third data latch DL2 of each bit line is assumed to be set to 0 just before the operation in line 502 at WLn. Since the byte line of the logic 1 is stored in the DL2 before the operation at WLn is not updated (the WLn data has been stored), additional lines for indicating the bit lines are not displayed for clarity of explanation. The first operation or sub-read listed by 502 is for a read operation of the adjacent word line WLn+1. The reading of WLn+Ι, the state at the top of lines 506 to 5 12 indicates the state of the cell read from WLn+Ι. If the memory cell of the bit line at WLn+Ι is in the state £, As shown in row 506, DL0 and DL1 are set to 11. If the memory cell is in state A at WLn+Ι, then as shown in row 508, DL0 and DL1 are set to 10. If at WLn+Ι When the memory cell is in state B, as shown in row 5 10, DL0 and DL1 are set to 00. If the memory cell of a bit line is in state C, then as shown in row 512, DL0 and DL1 are set to 01. In each case, the DL2 is set to 0 to indicate that the data within the latches is from WLn+Ι. Other data encodings can be used. A set of sub-reads at state A level begins the operation at WLn. The second column of operations in line 127827.doc • 46- 200845011 5 02 is used for the first sub-read of the selected word line under the state A level. The first sub-read A(E) is executed at state A and no floating gate coupling compensation is applied. Thus, the read A(E) sub-read can be applied to a bit line where the cell is in state E at WLn+Ι. The conditions or logic for deciding whether to update DL0 and DL1 for a particular bit line after reading the A(E) sub-read are presented in row 504. If the cell conduction at WLn for the bit line is previously set to 0 and DL0 to DL1 were previously set to 11, the data latches for that bit line are updated. The state E is stored in DL0 to DL1 and the bit line is set to 0 by DL0 to DL1 before the read A(E) operation satisfies the data latching criterion. If the memory cells of WLn are transmitted, DL0 and DL1 are updated for the bit lines. The values in rows 506 through 5 12 read immediately following the read A(E) sub-display show various data latch data that can be stored after the first sub-read can be performed at state A. These data latches are updated with a bit line that has a conducting unit and previously stores the WLn+Ι state E data. DL0 to DL1 retain 11 and set DL2 to 1. This is shown in line 5 06. All of the bit lines having state A, state B, or state C WLn+1 data as shown in rows 508 through 512 continue to store the same data. All bit lines with a non-conducting cell remain intact, as are the bit lines of the stored WLn data (DL2 = 1, not shown). The next sub-read reads A(A) is a state A-bit read that applies a compensation based on an adjacent memory cell in state A. The logic within row 504 indicates that if the DL2 is previously set to 0, and DL0 to DL1 were previously set to 10, then the data latch should be updated. The bit line storing the state A data for WLn+1 before the A(A) operation is read satisfies the 127827.doc -47·200845011 data latch criterion. Line 508 indicates that a bit line stores state A data for WLn+Ι just prior to sub-reading. The data in the flash for such bit lines is updated to store 11 for status E in DL0 through DL1. Also DL2 will not be reached; [indicating that DL0 and DL1 are storing WLn data. The bit line set to state E, state B or state C for WLn+Ι is not changed as shown in row 506, 510 or 512. The next sub-reading system reads A(B). This sub-read provides a compensation based on the adjacent memory cells at WLn+Ι in state b. If the cell conducts, dl〇 to DL1 is previously stored, and DL2 is previously set to 〇, then the data latches for a bit line are updated. The bit line storing the state B data for WLn+1 satisfies the data flash criterion and is updated as it has a conduction unit at WLn, as shown in row 510. The latches DL〇 and 〇1^ are updated to 11α to indicate the sadness data and set DL2 to 1. The bit line for the state Ε, state Α or state C of WLn+Ι is stored before the sub-read. The last sub-reading at state A reads A(c), which provides a compensation based on an adjacent cell at WLn+Ι in state c. The data latches will be updated for those bit cells that have a conducting cell and that have previously stored 〇1 in DL0 to DL· and stored a bit line in DL2. These latches are updated for bit lines currently configured with this profile to store 丨j in dlo to dl 1 and store one in DL2! As shown in line 512. The bit lines for state E, state A, or state B for WLn+Ι are not updated, as shown in rows 5〇6, and 510. A set of sub-reads at state B level begins with a read B(E) sub-read without applying any compensation. The latches are updated for bit lines that have a conduction unit and currently store logic 1 in DL0 to 127827.doc -48 - 200845011 DL1 and store logic 0 in DL2. For the bit line, which corresponds to the WLn+Ι latch data set set to state ,, DLO to DL1 are set to 10 and DL2 is set to 1. This is shown in line 506. For such bit lines having a non-conducting unit, the data latches set to state A, state B, or state C are not updated, as shown in rows 508, 510, and 512. The read B(A) sub-read applies a compensation based on a neighboring memory cell at wLn+1 in state A. The logic update during this sub-read is used for the data latches that have a conducting cell and are currently storing 1 DL in DL0 through DL1 and storing a 0 bit line in DL2. The dedicated strobe update for the bit lines stores 1 闪 in flashes DL0 through DL1 and a logic 1 in DL2, as shown in row 5〇8. The bit lines storing the WLn+ data for state E, state A, or sorrow B are not updated as shown in rows 5, 6, 510, and 512. Similarly, bit lines having a non-conducting unit or DL2 = 1 are not updated. 10 The read B(B) sub-read applies a compensation based on an adjacent memory cell at WLn+Ι in state B. The logic update during this sub-read is used for the data latches that have conductive cells and are currently stored in flashes DL0 through DL1 and store the bit lines in the DL2. The data flash is updated for the bit lines to store 1 闪 in flashes DL0 through DL1 and a logic 1 in DL2, as shown in row 510. Bit lines for state E, state a, or state with hungry data are not updated prior to the sub-read, as shown in rows 5, 6, 508, and 512. Bit lines having a non-conducting unit or DL2=1 are not updated. 127827.doc -49- 200845011 The read B(C) sub-read applies a compensation based on an adjacent memory cell at WLn+1 in state C. The data latches for a bit line having a conduction unit and currently storing logic 01 in DL0 to DL1 and storing logic 在 in DL2 are updated. The data latches for the bit lines are updated to store 10 in DL0 through DL2 and store logic 1 in DL2. The bit lines for the WLn+ data stored in state E, state A, or state C are not updated, as shown in lines 5 06, 508, and 510. A bit line having a non-conducting unit or DL2=2 is not updated. A set of sub-reads at state C level begins with a read c(E) sub-read without any compensation being applied. If a bit line has a conducting cell during sensing, the processor for that bit line determines whether the bit line flash is currently storing 11 in DL0 through DL1 and storing it in DL2. If so, the processor updates the latches for the bit line to the data shown in row 5-6. DL0 to DL1 are set to 00 and DL2 is set to 1. The latches are not updated for those bit lines that have a non-conducting unit or a conduction but are currently held for status A, B or c (lines 508 to 512). Similarly, the bit line having the DL2 setting of 1 is not updated since it has stored goods [11 data. The C(A) sub-predicate applies a compensation based on a neighboring stun-like unit at WLn+1 in state A. The processors for the bit lines having a conducting unit determine whether the bit line latches are storing 10 in dL0 through DL1 and storing 0 in DL2. If so, the processor updates the flash as shown in row 508. DL0 to DL1 are updated to 〇〇 and 〇1^ is updated to Logic 1. Bit lines having a non-conducting unit or a conduction but not currently maintaining state E, state B, or state CiWLn+1 data are not updated, as shown in lines 5〇6, 127827.doc-50-200845011 510 and 512. Bit lines with DL2=1 are not updated. The read C(B) sub-read applies a compensation based on an adjacent memory cell at WLn + 状态 in state b. The latches for the bit lines having a conducting cell are checked to determine if they are storing DL in DL0 through DL1 and store a logic 0 in DL2. The flashes for the bit lines are updated as shown in row 510 to store 〇〇 in DL0 through DL1 and store 1 in DL2. Bit lines with a non-conducting unit are not updated. The bit lines currently stored for WLn+ i, E, A or C, are not updated. Bit lines with dl2=1 are not updated. The read C(C) sub-read applies a compensation based on an adjacent memory cell at WLn+Ι in state c. The questions for the conductive bit lines are checked to determine if they are storing 〇1 in DL0 to DL1 and storing 〇 in DL2. If so, it is updated as shown in row 512 to store 〇1 in dl〇 to DL1 and to store logic 1 in DL2. Bit lines with a non-conducting unit are not updated. The DL2 setting is not updated to 1 or the bit line for the state E, A or B data of wLn+1 is stored. Row 504 specifies a final set of logic that is executed after the completion of the sub-read groups. If DL2 is storing a logic 〇 for any bit line after the last sub-read of state C level, then at WLn for that bit line during any sub-read of the sub-reads The memory unit is not conducting. Thus, the unit is programmed into state C. The processor associated with the bit line will set DL0 and 1 > 1^ to 01 to indicate the data for state c. The processor sets the third data latch DL2 for the bit lines to i to indicate that DL 〇 to DL1 are currently storing data for WLn. Figure 16 is a timing diagram of various signals of a memory 127827.doc - 51 - 200845011 system during a read operation in accordance with an embodiment. The signals applied to a selected word line WLn, an adjacent unselected word source line WLn+1, and each of the remaining unselected word lines are described. A strobe signal is also described, the initial sensing module sensing. The first portion of the read operation for WLn includes reading the adjacent word line WLn+1. The selected word line is raised to the transfer voltage VREAD such that all of the memory cells on it operate as a transfer gate. The adjacent word line is read by applying an appropriate read reference voltage Vcgr. Figure 16 illustrates an exemplary four-state device, so three read reference voltages Vra, Vrb, and Vrc are used. The unit conducting under Vra is in state E. The unit conducting under Vrb is in state A. Units that conduct under Vrc but do not conduct under Vra or Vrb are in state B. Also, cells that are not conducting at any of these voltages are in state C. The data values for the memory cells at WLn+1 are stored in the data latches DL0 and DL1 for each corresponding bit line. A third data latch DL2 is set to 0 to indicate that the data is for WLn+1. The actual sub-read at the selected word line begins after reading the adjacent word line. A set of sub-reads is first performed at the state A reference voltage level. The state A read voltage Vr a is applied to the selected word line during each sub-reading process. A first read conduction voltage VreadLA(E) is applied to the adjacent word line WLn+1 for a first sub-read. This first read transfer voltage does not provide any compensation based on floating gate coupling. The results of this sub-read store store state E data for conducting memory cells at WLn where one of the adjacent word lines WLn+1 is in state E. In response to a conductive memory cell, the bit line processor determines whether the latches DL0 and DL1 are storing data corresponding to the sub-read compensation level state E (e.g., 11). If so, the processor checks DL2 to determine if the data in 127827.doc -52- 200845011 DL0 and DL1 is for WLn+1. If so, the processor will overwrite DL0 and DL1 with the data for state E and set DL2 to 1 to indicate that DL0 and DL1 are now storing data for WLn+Ι and during subsequent sub-reads. Should not be overwritten. A second read transfer voltage VreadLA(A) is then applied to the adjacent bit line while Vra is continuously applied to WLn. At this point for the conduction unit, the corresponding bit line processor checks to determine if the latches DL0 and DL1 are storing data for state A and whether DL2 is storing one. If the two conditions are met, the processor overwrites the DL0 and DL1 data and sets DL2 to 1 using the data for state E. A third read transfer voltage VreadLA (B) and a fourth read transfer voltage VreadLA (C) are then applied. The steps outlined above and also outlined with respect to Figure 13 are repeated during the application of each of the read transfer voltages. This first set of sub-reads ends after VreadLA(C) is applied in conjunction with Vra. The second set of sub-reads begins by applying a second read reference voltage Vrb to the selected word line. Since the conduction unit at the Vra level is locked from overwriting the data latch by setting a flag in DL2, the conduction unit at the Vrb level indicates the unit at state A. A first sub-read is performed without applying any compensation to the adjacent word line WLn+Ι. Corresponding to the adjacent cells in state E, VreadLA(E) is applied. For the corresponding bit line data latch, the conductive memory unit for storing the data for the state E is used, and when the DL2 system is set to 〇, the state A is overwritten with the state A. If DL2 is set to 1 or DL0 and DL1 are storing data for another status, no action is taken. Then by applying 127827.doc -53- 200845011

VreadLA(A) to the adjacent word line to perform a second sub-read at the state B level. The data in dl〇&du is overwritten using the state A data for the DL0 and DL1 set to state A and the DL2 set to 1 transfer memory cell. Two "extra sub-reads are performed by applying read transfer voltages VreadLA(b) and VreadLA(c). These logic steps are repeated as described in Figure 13 and Figures 14A-14B. The last group read. Add the state € read reference φ voltage VrC^ to the selected word line. The four read transfer voltages are applied again to the adjacent word lines in sequence. The bit line processors execute the previous A logical step of ticking to update the latches as appropriate and switching the third data latch to indicate when the WLn data is stored. Each sensing module performs sensing beginning with the strobe signal described at the bottom of FIG. A single gating is used at each reference level Vra, vomit and deuterium when reading at WLn+1. When sensing at WLn, the second gating is used for the first sub-read in each bit. A single strobe is used for each sub-read of the three remaining sub-i readings. Two strobes are often used during the item fetch operation to minimize source voltage errors due to galvanic current in the source line. The pole line has a limited grounding resistance. The read/write circuit is 13〇13, 13〇β Simultaneous operation on the memory unit page. The conduction current of each of the 6 memory cells flows from the sensing module into the non-polarity of the memory unit and flows out from the source, and then passes through a source line to the ground. When a common source line is used and connected to an external pad, a finite resistance is still between the source electrode of a memory cell and the pad, that is, when the source line resistance is reduced by using the genus ▼. When a finite resistance exists between 127827.doc -54- 200845011 between the source electrode of a memory cell and the ground pad, the voltage drop across the resistor is equal to the product of the total conduction current of all cells and the finite resistance. This may cause a sensing error. A method to reduce errors is often done by multi-pass sensing. Each pass helps to identify and turn off the memory using a conduction current higher than - a given division value. In this way, subsequent pass sensing will be less affected by the source line bias 'because the higher current cell has been turned off. In a particular embodiment, the memory cell has a conduction current that exceeds the dividing point. borrow It is turned off by setting the drain voltage of its bit line to ground (for example, by setting an appropriate value in the bit line latch 202). Since the high current units are removed, more accurate sensing is achieved. Wait for the remaining cells. When reading at WLn+Ι, a single strobe is used in each of the bits, because the reading accuracy is not critical when determining the neighbor's charge level or state information. Use two strobes for The first sub-read of each element is read, but only one strobe is used for reading at each of the remaining sub-levels. The two strobes shown in Figure 16 correspond to the two-pass sensing described. The memory cell that is conducted during the first sub-reading sets its bit line to ground for the remaining sub-reads at that level to reduce the voltage drop due to the source line bias. After turning off the memory cells during a sub-read, a single pass sensing (one gating) can be used for the remaining sub-reads at the same level. Since the cells that were turned off during the first sub-reading reduce the source line bias voltage drop, accurate sensing is still being paid. This represents a technical improvement that can use a first VREAD value at WLn+Ι to apply different reference voltage levels to the selected word line and repeat with a different value at WLn+1. 127827.doc -55- 200845011 ^ For such techniques to sequentially increase the power applied at the selected word line, then two passes of sensing at each sub-read may be required. Early pass sensing as currently disclosed will use less energy and improve performance time. Figure 17 is a diagram for the case of -1 〇 μ -, ^, one of the specific embodiments not compensated in Figure 12. As in the prior art, the adjacent word line is read for the bit lines by applying the selected word line and the three read reference voltages Vra are read, and the adjacent word lines are unbounded by +1. Data storage

It is stored in the shells and asks the third data to q to indicate that the data is for the word line WLn+Ι. In the beetle, the "Muzhi", the moxibustion, began to be used for the selected character line: the equator (9) took, and. For each sub-read of the far-group read, the phase of the phase ball is raised to VREAD 'so that the memory cell on it acts as the transfer gate and h also raises the other unselected word lines. Up to ν_, its memory cell operates as a transfer gate. The selected word line has a different read reference voltage applied for the state level. A first term reference voltage Vra is applied which does not include any compensation based on the state of an adjacent memory cell at WLn+1. The sensed results stored at this level are used in the memory cell where the adjacent memory cells are in the erased state at WLn+Ι. For units that conduct under the target plus Vra, the corresponding processor determines whether the data latches DL〇 and DL1 are storing data for state E. If so, the processor checks if DL2 is being stored to indicate that the data in 1^〇 and 1)]^1 is for WLn+Ι. If the two conditions are met, the processor overwrites the data in DL0 and DL1 with the data for the current sub-read group. Read in state A. The processor sets the latches to be equal to the status E data (e.g., 11). For all other bit lines of 127827.doc -56 - 200845011, no action is taken. These steps are repeated for each of the read reference voltages of the remaining read reference voltages. Vral corresponds to an adjacent memory cell in state A, Vra2 corresponds to an adjacent memory cell in state B, and Vra3 corresponds to an adjacent memory cell in state C. The processors for each of the meta-wires perform a sequence of logical steps to determine whether the data latches should be overwritten. To overwrite the data, the corresponding processor overwrites the data with the data for state E and sets the third data latch to 1 to indicate that the latch now stores the data for word line WLn. In the particular embodiment of Figure 17, two gates are used for sensing during each sub-read of state A level (and at state B and state C levels described below). Two gating sensings are used because the voltage applied to the selected word line during each particular group of sub-reads is increased for each subsequent sub-read. A second set of sub-reads at state B level is performed after each sub-read of the state A-level sub-reads is performed for the selected word line WLn. The adjacent word line is again raised to V READ to operate as a pass gate', as are other unselected word lines. The first state B read reference voltage is applied to the word line WLn. The first read reference voltage does not compensate for floating gate coupling. Accordingly, DL0 and DL1 are set to the state E value and DL2 is set to 0 to indicate that it is storing the WLn+1 data bit to update its data latch. For these bit lines, DL0 and DL1 are set to the value for state A (eg 10) and DL2 is set to 1 to indicate that it is now storing data for WLn. This procedure is repeated in the remaining state B reading levels Virbl, Vrb2 and Vrb3. A final group sub-read is performed at state C level. VREAD is applied to the adjacent word line WLn+Ι. The state B is sequentially applied to read the reference voltages Vrc, Vrcl, 127827.doc -57- 200845011

Vrc2 and Vrc3 use these sensing results to overwrite the data latch values for the appropriate bit lines, as already explained. The method described with respect to Figures 14 through 17 is presented in terms of full sequence stylization in which two bits of a logical page are stored to store the memory cells shown in Figure 6. The data programmed according to the techniques of the upper and lower pages shown in Figure 7 can also be read in a similar sensing sequence and data latch configuration. The adjacent word line WLn+Ι can be read and the data for each bit line is stored in the registers DLO and DL1 (assuming a 2-bit device). If the next page is read for the selected word line, then only the status A (eg, Vra) and status C (eg, Vrc) reference levels are read. Steps 408 through 420 of Figures 14A through 14B can be performed at selected word lines, followed by steps 440 through 454. Since the read operation only determines one bit of metadata for each cell of the selected word line, a single data latch is required to store the data from WLn. For example, the next page of information can be stored in DL0. Steps 408 through 420 will be modified to respond to setting a DL0 to logic 1 by a conducting unit during an appropriate sensing operation for the bit line based on data from WLn+1. When the WLn data is stored as previously described, DL2 is set to logic 1. Steps 440 through 454 will be modified to respond to setting a DL0 to logic 0 by a conducting unit during a suitable sensing operation for the bit line based on data from WLn+1. For a bit line having a non-conducting cell during state A and state C-bit read, set DL0 to logic and DL2 to logic 1.

For the previous page read, simply read at the Status B reference level (eg Vrb). A single latch is required to store the previous page. For example, data can be stored in DL0 or DL1. Steps 424 to 438 of Figs. 14A to 14B 127827.doc - 58 - 200845011 can be performed after reading WLn + 用于 for selecting the Μ element line, thereby storing the data in the DL0 and DN, and setting DL2 to 〇. If a memory cell is conducted during the appropriate sub-reading of the state B level, then the positivity can be set to logic 丄 and (10) can be set to logic if the memory cell is read in the state B sub- If it is not conducted during the period, set DL〇 to 位 for the bit line and set DL1 to 1. The compensation and data flashing can be similarly performed to read the data stylized according to the technique described in FIG. 8C. #When reading the data programmed according to the program of ^^^^, the page above the stylized pending memory cell should be corrected for the floating gate due to the page below the stylized adjacent cell. Any-disturbance. Because, when trying to compensate for the floating gate face from an adjacent unit, one embodiment of the program only needs to consider the effect of the lightness caused by the page on the stylized adjacent unit... The program is therefore readable ^ Used for the previous page of adjacent word lines. If *programs the page above the adjacent word line, the page can be read without compensating for the floating gate coupling. If the page above the 70 lines of the adjacent word is programmed, some of the inter-floating offset compensation will be used to read the consideration page. In some embodiments, the read operation for adjacent word lines results in determining whether the charge on the adjacent word line does or may complementfully reflect the data stored thereon. Moreover, the library phonetic: the selected character line (ie WLn) read may have its own data on the next page: This may happen when the entire block is not programmed. In this case, it is always guaranteed that the cells on WLn+丨 are still erased, so there is no coupling effect that still plagues the WLn cells. This means that τ / / 又 又 又 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 ▲ In one embodiment, a memory array implementing the programming of Figures 8-8 (the stylized program will retain a set of memory cells to store one or more flags. For example, a usable-line memory cell To store a flag indicating whether the page below the unit has been programmed, and another row of memory cells can be used to store the flag, indicating whether the page for the column memory unit is on the screen. In some embodiments, a redundant unit = a copy of the flag can be used. By checking the appropriate flag, it can be used to program whether the page above the adjacent word line has been programmed. More details of such flags and stylized programs can be found in (4) U.S. Patent No. 6'657'891 to Gam et al., "Semiconductor Memory Device for Storing Multivalued Data", the entire contents of which are This is incorporated herein by reference. Figure 18 illustrates a specific embodiment of a procedure for reading a sheet of material above an adjacent word line (e.g., adjacent WLn + 没 on the opposite side). In step (9), Applying a "buck reference voltage Vix" to the character associated with the read page At step 602, the bit line is sensed. In step _, the results of step 6 〇 2 are stored in the appropriate flash. In step 606, the system checks the relevant % of the item on the page. In a specific embodiment, when the flag is not present, the memory unit storing the flag will store the state E and the state c information is stored when the flag is 5 and the flag is stored. Therefore, when the specific memory unit is sensed in step 602, if the memory unit conducts (turns on) 'the A memory unit is good in the data of the state c, and the flag is not set. If the sedative II-w body does not conduct early, then it is assumed in step 606 that the memory indicates that the previous page has been borrowed by 4, and 2%. Other 127827.doc 200845011 components for storing a flag may be used, for example By storing the flag in a tuple data. If the flag has not been set (step 608), the procedure of Figure 18 is aborted, summarizing that the previous page has not been programmed. A coupling compensation can be performed at WLn. Standard reading material. If the WLn reads the lower stomach data, it is in the gB level (example) Sensing under Vrb) is sufficient to determine the next page of data. If the previous page is read, sensing is performed in state A (eg, Vra), state b (eg, Vrb), and state c level (eg, Vrc). The flag has been set (step 608), assuming that the upper page has been programmed and the voltage Vrb is applied to the word line associated with the read page at step 612. The bit line is sensed as described above at step 614'. The results of step 614 are stored in the appropriate question at step 616. At step 618, the voltage is applied to the word line associated with the read page. At step 620, the bit line is sensed. Step 622' stores the results of step 62G in a suitable flash. At step 624, processor 212 determines that the memory is being read based on the results of the three sensing steps 6〇2, ^, and 6 The value of the data stored in each memory unit of the unit. At step 626, the data values determined at step 624 are stored in the appropriate data_. In the step coffee, the processor says to use the well-known simple logic technique depending on the (4) special mode encoding to determine the upper and lower data values. For example, for _ to 8 (: the encoding, the next page is W (the value stored when reading under Vrb complements the previous page data system Vra*〇R (Vrb AND v is already used in the embodiment) The similar technique described is based on /I in an alternative specific storage of data. A unique skills in the individual sensing operations in a specific implementation, _ procedures include application to the bungee side 127827.doc • 61- 200845011 Adjacent word lines. Thus, for the extent of Figure 18, VREADX = VREAD. In another embodiment of the procedure of Figure 22, 'VreadX = VreadL A(E) 〇 only needs to be read according to Figures 8A through 8C The technique-programmed unit time compensates for floating gate coupling due to the upper page of the stylized WLn+Ι. In a specific embodiment, full data from WLn+Ι can be stored in the latch (eg, storage) Two bits in DL0 and DL2. If a cell of WLn+1 is in state E or state B, no compensation is used when reading an adjacent cell at WLn. If the cell is in state A or state C , a compensation can be applied. Because only one compensation is provided or not provided, In the example, a single bit of data is stored for WLn+Ι. Figure 19 provides a flow diagram that is interpreted to perform a decision whether or not to use an offset for requiring a latch to store a particular bit line of WLn+Ι data. Step 1. The first step is to use Vra to perform a read procedure on the word line. The second step is to perform a read using Vrb. When reading under Vra, a latch is stored when the memory unit is in state E. 1 and store a 0 when the memory unit is in state A, B or C. When reading under Vrb, the latch will store a 1 for states E and A, and store a 0 for state B. And C. The third step of Figure 19 includes performing an XOR operation on the result of the flip from the second step and the result from step 1. In the fourth step, a read is performed using Vix on the word line. 1 for states E, A, and B, and storing a 0 for state C. In the fifth step, the results of steps 4 and 3 are operated by a logical AND operation. It should be noted that steps 1, 2 And 4 can be implemented as part of Figure 18. Steps 3 and 5 of Figure 19 can be dedicated The body is executed by processing 127827.doc -62 - 200845011 212. The result of step 5 is stored in a latch of storage 1 when no compensation is required and is stored in a latch of storage 0 when compensation is required. Thus, for those cells having WLn read on adjacent memory cells on WLn+, the A/C state will require a compensation. This scheme requires only a latch to determine if WLn is to be corrected. After reading and storing the information from WLn+Ι, the selected word line WLn is read. If the next page of the page is read, Figure 20 is executed. If the previous page is being read, Figure 21 is executed. Figures 20 and 21 relate to an example in which only one meta-data is stored to indicate whether a compensation should be used at WLn based on WLn+Ι. Other embodiments may store full WLn+1 data. In Figs. 20 and 21, DL0 is used to indicate that the corresponding unit at WLn is in state E/B (DL = 0) or state A/C (DL0 = 1). A compensation is used when DL0 = 1 and no compensation is used when DL0 = 0. The page data stored using the data encoding scheme shown in Figs. 8A through 8C can be determined by reading at the state B reference level. A first sub-read is performed at step 650 without applying any compensation. The processor checks with a bit line of a conductive memory cell to determine if DL0 is storing a logic 0. This indicates that the adjacent cell at WLn+Ι is in state E or state B, so no compensation is required when reading WLn DL1. If DL0 is set to 0, the processor checks DL1 to see if it is set to 0, indicating that DL0 is storing WLn+Ι data. If both DL0 and DL1 are set to 1, the processor sets DL0 to logic 1. The processor also sets DL1 to logic 1 to indicate that DL0 is storing data for WLn. At step 654, another WLn state B level read is performed while a floating gate coupling compensation of 127827.doc -63 - 200845011 is applied. If the memory cell of one bit line is conducting during the compensator read and a logic 1 is being stored in DL0 and a logic 0 is being stored in DL1, then at step 656 the processor sets DL0 to 0 and sets DL1 to Logic 2. This indicates that the latches are now storing the logical 0 next page data for WLn. At step 658, it is determined whether any of the bit lines are storing a logic 0 in DL1. This indication corresponds to the memory unit not being conducted at each sub-read. For these bit lines, DL0 remains at logic 0 and DL1 is set to 1 to indicate that the latch is storing the logical 0 next page data for WLn. If the page is read on the page, the method of FIG. 21 is performed. A read is required under the Status A, State B, and Status C reference levels to determine the upper page data for the word line. The DL0 for each bit line will store the data for the previous page, but DL1 may store the previous page and a third latch DL2 for storing the flag. At step 700, a non-compensated sub-read at state A level is performed for WLn. If a bit line memory cell is conducting, DL0 is currently set to logic 0 and DL1 is currently set to logic 0, then in step 702, the processor sets DL0 to logic 1 and DL1 to logic 1. At step 704, a compensator read is performed at WLn. If a memory cell of a bit line is transmitted, DL0 is currently set to logic 1 and DL1 is currently set to logic 0, then in step 706, the processor sets DL0 to logic 1 and DL1 to logic 1. At step 708, a no-compensated sub-read at state B level is performed for WLn. If the memory cell of one bit line is conducted, the DL0 system is currently set to logic 0 and the DL1 system is currently set to logic 0, then in step 710, the processor 127827.doc -64-200845011 sets DL0 to logic 〇 and DL1 Set to logic 1. At step 712, a compensator read is performed at WLn. If the memory cell of one bit line is conducting, the DL0 system is currently set to logic 1 and the DL1 system is currently set to logic 〇, then in step 714, the processor sets DL0 to logic 0 and DL1 to logic at step 716. A no-compensated sub-read at state B level is performed for WLn. If the memory cell of one bit line is conduction, DL0 is currently set to logic 0 and DL1 is currently set to logic 〇, then in step 71, the processor sets DL0 to logic 1 and DL1 to logic 1. At step 720, a compensator read at state b is performed for WLn. If the memory cell of a bit line is conductive, DL0 is currently set to logic 1 and DL1 is currently set to logic 0, then in step 722, the processor sets DL0 to logic 1 and DL 1 to logic 1. For a bit line having a non-conductive memory cell during each sub-read (the logic 0 is still stored in DL1), the memory cell is in state c. Thus, at step 724, DL0 is set to logic set to logic 1 °. Figure 22 is a description - used to read a check word when the system does not need to face the floating gate to floating gate compensation from the adjacent word line. A flowchart of a specific embodiment of the data of the meta-line. Figure 22 can be executed in response to the unsynchronized decision of the previous page of adjacent word lines (step 61 of Figure 18). At step 750' it is determined whether the read is for the associated page above or below the associated word line. If the read is for the next page, then at step 754, voltage Vrb is applied to the word line associated with the read page. In the step..., sense the 127827.doc •65- 200845011 equipotential 兀 line. At step 758, the results of the sensing step 756 are stored in the appropriate query. At step 76, the flag is checked to determine if the page contains the previous page. If there are no flags, then any current data will be in intermediate state B and Vrb is the incorrect comparison voltage to be used. The program proceeds in step 762. At step 762, Vra is applied to the word line and the bit line is re-sensed at step 764. At step 766, the result is stored. At step 768 (at step 766 or if flag step 76 is set), processor φ determines a data value to store. In one embodiment, when the next page is read, if the memory unit responds by applying Vrb (or Vra) to the word line, the next page is "1". Otherwise, the next page of data is "〇". If it is determined that the page bit address corresponds to the next page (step 75A), then a page capture process is performed in step 752. In a specific embodiment, step 752 The page reading procedure includes the same method as described in Figure 18. Figure 18 includes the read flag and all three states, since one may be addressed for reading or another reason, not written to the upper page. The procedure of Figure 22 includes applying a chirp to the left side adjacent word line. Thus, for the procedure of Figure 22, VREADX = VREAD. In another embodiment of the procedure of Figure 22, vreadX = vreadLA ( The above detailed description is intended to be illustrative and not restrictive, and the invention is not intended to be The embodiments are intended to best explain the principles of the invention and the application of the invention, and the embodiments of the invention can With Patent Application No. 127827.doc -66 - 200845011 to define the scope of the present invention. [Simplified Schematic] Fig. 1 is a top view of a NAND string. Fig. 2 is an equivalent circuit diagram of a NAND string of Fig. 1. Fig. 3 is a A block diagram of a NAND flash memory cell array. Figure 4 is a block diagram of a non-volatile memory system. Figure 5 is a block diagram of one embodiment of a sensing block.

Figure 6 depicts a set of exemplary threshold voltage distributions, a full sequence stylized sequence. Figure 7 depicts a set of exemplary threshold voltage distributions and an upper/lower page deuteration procedure. Figures 8A through 8C depict a set of exemplary threshold voltages and one or two programming runs. sequence. Figure 9 is a timing diagram illustrating the behavior of a particular signal during a read/verify operation. Figure 10 is a block diagram showing the capacitive coupling between two adjacent memory cells. Figure 11 is a set of exemplary threshold voltages for a floating gate light-sinking effect. Figure 12 illustrates an exemplary set of threshold voltage distributions that may be used in accordance with one embodiment using a floating idler coupling technique. Figure 13 is a flow chart showing one of the floating interpole coupling coupling techniques that can be used in accordance with an embodiment. Figures 14A through 14B illustrate a flow chart of a method for reading a non-volatile 127827.doc-67-200845011 hair storage device while compensating for floating gate coupling in a particular embodiment. Figure! 5A through 15C describe a table for specifying a data latch during a read operation in a specific embodiment. Fig. 16 is a timing chart showing one of various voltage signals for the execution-read operation of the sun and the moon. Figure 17 of each adjacent word line of a read operation illustrates a timing diagram for performing a voltage signal in a particular embodiment.

Figure 18 is a flow chart illustrating one of the methods of reading in accordance with one embodiment. Figure 19 is a diagram for providing a table 0 of whether or not to use a compensation when reading a particular bit line based on adjacent word line data. Figure 20 is a specific embodiment. The first one is used to read the next page data from the 7K line of the one-kilometer, including one of the flowcharts of the floating gate coupling compensation. Figure 21 is a flow diagram of a method for reading the next page data from a select, dice line, including floating gate coupling compensation, in a particular embodiment. Figure 22 is a flow diagram for reading a selected empty _ &< 疋 7L line without providing compensation in accordance with an embodiment. [Main component symbol description] 10 Transistor 10 C G Control gate 10FG Floating gate 12 First selection gate/transistor 12CG Control gate 127827.doc •68- 200845011

12FG Floating Gate 14 Transistor 14CG Control Gate 14FG Floating Gate 16 Transistor 16CG Control Gate 16FG Floating Gate 20CG Control Gate 22 Second Select Gate 22CG Control Gate 26 Bit Line Terminal / 汲 Terminal 27 Bit Line 28 Source Line Terminal 29 Source Line 30 Block 50 NAND String 100 Two-Dimensional Memory Cell Array 110 Memory Device 112 Memory Die 120 Control Circuit 122 State Machine 124 On-Chip Address Decoder 126 Power Control Mode Group 130A read/write circuit 127827.doc -69- 200845011

130B read/write circuit 132 line 134 line 140A column decoder 140B column decoder 142A line decoder 142B line decoder 144 controller 200 sensing block 202 bit line latch 204 sensing circuit 206 data bus 208 input Line 210 Sensing Module 212 Processor 214 Data Latch 216 I/O Interface 220 Common Portion 302 Adjacent Floating Gate 304 Adjacent Floating Gate 306 NAND Channel/Substrate 308 Source/Polar Region 310 Source /gt Polar Region 312 Source /gt; and Polar Region 127827.doc -70- 200845011 314 Control Gate 316 Bungary Side Adjacent Control Gate 320 Distribution 322 Distribution 324 Distribution 326 Distribution 328 Distribution 330 Distribution 127827.doc -71-

Claims (1)

200845011 X. Patent Application Range 1. A non-volatile memory system comprising: a first non-volatile storage element; - a second non-volatile storage element adjacent to the first non-volatile storage element; - a bit a line 'in communication with the first non-volatile storage element and the second non-volatile storage element; a set of data latches associated with the bit line; a management circuit coupled to the first non-volatile storage element The second non-volatile storage element, the green line and the group of data, the management circuit responds - requires ff to take (four) - the requirement of the non-volatile storage element, and the information from the second non-volatile storage element A first indication is stored in the group of negative materials. The management is performed in a specific state for a specific state = for reading = the first - non-volatile storage element, if corresponding to the group of shells The specific operation of the sensing operation of the data stored in the directory: during the period: the first non-volatile storage element is conducted and if the first indication is present in the circuit (4): the predetermined data is replaced in the group Information flash The information within the source, if the data from the non-volatile storage element is replaced, the management circuit replaces the first indication with the predetermined (four) from (four)-non-swipe (four) listing. A non-volatile memory system of the present invention, wherein the management circuit performs the plurality of sensing operations by means of the underlying state: by applying a first-read reference voltage to The first non-volatile storage element 127827.doc 200845011 simultaneously applies a first transfer voltage to the second non-volatile storage element to perform a first sensing operation, the first transfer voltage corresponding to the second non-volatile storage element a first set of data that may be stored; and applying a second read voltage to the first non-volatile storage element while applying a second transfer voltage to the second non-volatile storage element = 'performing a second sense The second transfer voltage corresponds to a second set of data that the second non-volatile storage element may store. Φ 3· The non-volatile memory system of claim 2, wherein: if the second non-volatile storage element is programmed to a first state after the first non-volatile storage element is programmed, the a sensing operation compensates for an apparent increase in threshold voltage of the first non-volatile storage element; and the second non-volatile storage element is programmed to a second state after the first non-volatile storage element is programmed Then, the second sensing operation complements the threshold voltage of one of the first non-volatile storage elements. 4. The non-volatile memory system of claim 1, wherein: • the brother and the first non-volatile storage element are multi-level storage elements capable of being in one of eight data states; possibly stored in the data latch of the group The different data includes eight sets of individual data corresponding to the eight data states; 'the management circuit performs the plurality of sensing operations by performing eight sensing operations corresponding to the eight data states, each sensing operation A different amount of compensation is provided when sensing the first non-volatile storage element based on a potential data state of the first non-volatile storage element. 5. The non-volatile memory system of claim 4, wherein the data latch comprises 127827.doc 200845011 four data networks; and the data from the second non-volatile storage component is stored in three data gates and the The indication is stored in a single data latch; the logic circuit replaces the data by using the predetermined data to overwrite the three data queries; and the Guangguan circuit is overwritten by the single data latch The first indication to replace the first indication with the second indication. The non-volatile memory system of member 1, wherein the management circuit performs the plurality of sensing operations for the specific state by using Performing a first sensing operation by applying a ___read reference voltage to the first non-volatile storage element, the first read reference voltage corresponding to (four) two I: a first group that may be stored by the volatile storage element Data, and: and a second read reference voltage is applied to the first non-volatile storage element: a second sensing operation is performed, the second read reference voltage corresponding to the second non-volatile storage element A second set of data that may be stored. The non-volatile memory system of claim 1, wherein: the processing circuit performs a plurality of sensing operations for a different state to read the non-volatile storage element, and each sensing operation for the different state corresponds to The different data that may be stored in the set of data latches of the third non-swollen (four) storage element; 2 during the particular one of the sensing operations for the particular state, the first one: the volatile storage element is not conductive And the first 127827 during the _specific period of the sensing operation for the 4 different sorrows corresponding to the data currently stored in the set of data for the _non-volatile storage S piece. Doc 200845011 When the non-volatile storage element is conductive, the management circuit replaces the data from the second non-volatile storage element with a different predetermined material. The non-volatile memory system of claim 1, wherein the management circuit: performs a plurality of sensing operations for a different state to read the second transmitting component for each sensing operation of the different state Corresponding to the different information stored in the set of data latches for the second non-volatile storage element; Determining whether the first non-volatile storage element is conducting during one of the plurality of sensing operations for the different states; determining whether the group of data is storing the second indication, and responding to the decision Whether the first non-volatile storage element is conductive and the set of data = whether the second indication is being stored, the data from the second non-volatile storage element is maintained in the set of data. 9. The non-volatile memory system of claim 1, wherein the data is present from the second non-volatile storage element and the first volatile material is in the sensing operation. Conducted during a first sensing operation, the first sensing operation not (d) the data currently stored in the set of lean latches; and after the first sensing operation, the management circuit flashes in the set of data The material from the second non-volatile storage element is maintained internally. 10. The non-volatile memory system of claim 1, wherein: the first non-volatile storage element is coupled to a first word line; the = two non-volatile storage element is coupled to a second word line; The indication of the shell material from the second non-volatile storage element is an indication from the second character line of the 127827.doc 200845011. U. The non-volatile memory system of claim 1, wherein: the first and second non-volatile storage elements are first and second n AND flash memory cells. - I2. A method of reading a non-volatile memory, comprising: responding to a request to read a first non-volatile storage element to read a non-volatile storage element; • storing a read in a set of data latches Taking data from the second non-volatile storage element; the data stored in the set of data flashes is a first indication from the second non-volatile storage element; performing a plurality of sensing operations for reading in a particular state The first non-volatile storage element, each sensing operation corresponding to a different material that may be stored in the set of data latches for the second non-volatile storage element; if corresponding to storage from the second non-volatile storage element The first non-volatile storage element is conducted during a particular one of the sensing operations of the data in the set of materials; and if the data is present in the m-phase from the second non-volatile storage element The indication of replacing the data from the second non-volatile storage element in the group (4) with the predetermined material for the particular state; and the right replacement from the second non-volatile material The data storage element, is used within the set of Q data from the shape data of the first line - indicating a second nonvolatile storage element to replace the first indication. 13. The method of claim 12, wherein the plurality of 127827.doc 200845011 sensing operations are performed for the particular state, comprising: *...a non-volatile storage element simultaneously applying - a first transfer voltage to the first The second non-volatile storage performs a first sensing operation 'the first transfer voltage corresponds to the first set of data that may be stored by the second non-volatile storage element; and the straw is applied to the first read reference voltage The first non-volatile storage element simultaneously applies a second transfer voltage to the second non-volatile storage: element:: Performing a speculative operation, the second transfer voltage corresponds to a second set of data that the second non-volatile storage element may store. 14. The method of claim 13, wherein: if the second non-volatile storage element is programmed to a first state after the staging of the first non-volatile storage element, the first sensing operation compensates for the first The non-volatile storage element has an apparent increase in threshold voltage; and if the second non-volatile storage element is programmed to a second state after the first non-volatile storage element is programmed, the second sensing operation compensates One of the first non-volatile storage elements has an apparent voltage increase. 15. The method of claim 12, wherein: "the younger brother and the non-volatile storage component are capable of being in a plurality of quasi-storage elements of eight slanting skin states; the shell may be stored in the set of data latches. The different data includes eight sets of individual data corresponding to the eight data states; the performing the plurality of sensing operations includes performing eight sensing operations corresponding to the eight data states, each sensing operation being based on the second The non-volatile storage element provides a different amount of compensation in the data state to sense the first non-volatile storage element 127827.doc 200845011. 16. The method of claim 15, wherein the set of data includes four Data flashing; the data from the second non-volatile storage element is stored in three data latches and the instructions are stored in a single data latch; and the replacement data uses the predetermined data to overwrite the three data The second indication is used to replace the first indication to overwrite the first indication stored in the single data latch. f 17. The method of claim 12, wherein the sensing operation comprises: Performing the plurality of the specific states: applying a first read reference voltage to the first non-volatile storage element: performing:: a first-sensing operation 'the first-reading reference voltage corresponding to the second non-volatile storage The component may store - the first group of data; and the error by the application - the second read reference voltage to the first nonvolatile storage = hold::: second sensing operation, the second read reference voltage corresponds to a non The second set of data may be stored by the volatile storage element. 18. The method of claim 12, further comprising: performing a plurality of sensing operations for a different state to read the first volatile storage element for the difference (4) Each of the operations is stored in the set of (4) different materials for the second storage element; the "the non-volatile storage element of the door if the sensing operation is used for the particular state" Unexpectedly, in the case of the sensing operations for the different states of the set of data _^= for the second non-volatile storage element, the specific one is _ 127827.doc 200845011 - Non-volatile storage element is conductive The material is replaced with the predetermined data to replace the data from the second non-volatile storage element. 19. The method of claim 12, further comprising: performing a plurality of sensing operations on the ten different pairs to read the first a non-volatile storage element associated with each sensing operation of the different states; the different data stored in the set of data for the second non-volatile storage element; Determining whether the first non-volatile storage element is conducted during the first sensing operation of the plurality of sensing operations in the different states; determining whether the group information is storing the second indication; Whether the non-volatile storage element is conductive and the set of data 疋=stores the second indication, maintaining the data from the non-volatile storage element in the set of data flashes. 2. The method of claim 12, wherein: when: the data is from the second non-volatile storage element, the first-system = ::: hair: _ is currently stored in the sense The transfer of the fault should be made in the group of information that the method further includes maintaining the information from the teacher: after the test operation, the data in the group is a non-volatile storage element. 127827.doc