200843302 、 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種數位變頻器（Digitai inverter)，尤 指一種數位變頻器之訊號補償方法。 【先前技術】 、艾頻為係作為電磁裝置的供電設備，以增進其操控特 性。^頻器的應用領域包括了不斷電系統、電子照明設;'、 • 平面顯不器背光板顯示照明、感應加熱、變頻電焊、各類 伺服及馬達驅動系統、電力電子系統的測試電源等。為了 使輸出端獲得正弦波電壓訊號，變頻器内部係先依據輸出 頻¥的而求，產生一正弦波形式的參考訊號，以正弦脈寬 调k (Sinusoidal pulse width modulation，SPWM)技術， 利用另一三角波比較訊號對參考訊號作調變，以產生一脈 寬調變訊號控制換流器將直流電壓轉換為正弦波交流輪出 §fL 5虎驅動負載^。 _ 理想變頻器的輸出訊號應為正負半週對稱的正弦波訊 號。然而’因變頻器内部元件的些微電氣特性差異，將造 成輸出訊號正負半週訊號不平衡。此不平衡現象可視為正 弦波加上一直流電壓偏差量，此電壓偏差量雖不致於對電 限性、電容性與整流性負載造成影響，然而，卻可能致^ 電感性負載飽和。電感性負載一旦飽和係如同短路，對變 頻.器而言，將造成相當大的負擔。 又 ^在類比控制變頻器中，可對參考訊號加上直流抵補電 壓’以消除輪出訊號的正負半週訊號不平衡現象。然而， 對於數位、交頻器而言，由於解析度的問題而無法將直流抵 5 200843302 4 、 補電壓直接加入參考訊號作補償。本案發明人有鑑於此， 從而提出本發明，针對數值變頻器輸出訊號的不平衡現象 提迚改善方案，以提升數位變頻器的效能。 【發明内容】 因此，本發明之目的係在於提供一種數位變頻器 (Digital inverter)及其訊號補償方法，其藉由分析輸出訊 號的電氣特性，來產生數位補償訊號疊加於參考訊號，係200843302, IX, invention: [Technical Field] The present invention relates to a digital converter (Digitai inverter), and more particularly to a signal compensation method for a digital converter. [Prior Art] Ai frequency is used as a power supply device for electromagnetic devices to enhance its handling characteristics. The application fields of the frequency converter include the uninterruptible power system and the electronic lighting device; ', • the flat panel display backlight display illumination, induction heating, frequency conversion welding, various servo and motor drive systems, test power supply for power electronic systems, etc. . In order to obtain the sine wave voltage signal at the output, the inverter internally generates a reference signal in the form of a sine wave according to the output frequency, and uses a sinusoidal pulse width modulation (SPWM) technique to utilize another A triangular wave comparison signal modulates the reference signal to generate a pulse width modulation signal control converter to convert the DC voltage into a sine wave AC wheel §fL 5 tiger drive load ^. _ The output signal of the ideal inverter should be a positive and negative half-cycle symmetrical sine wave signal. However, due to the slight electrical characteristics of the internal components of the inverter, the positive and negative half-cycle signals of the output signal will be unbalanced. This imbalance can be thought of as a sine wave plus a constant current voltage deviation. This voltage deviation does not affect the capacitive, capacitive, and rectifying loads. However, it may cause the inductive load to saturate. Once the inductive load is saturated, it is a short circuit, which will cause a considerable burden on the frequency converter. Also, in the analog control inverter, DC voltage can be applied to the reference signal to eliminate the positive and negative half-cycle signal imbalance of the turn-off signal. However, for digital and frequency ACs, due to the resolution problem, it is not possible to add DC to the reference signal for compensation. In view of this, the inventor of the present invention has proposed the present invention to improve the imbalance of the output signal of the numerical frequency converter to improve the performance of the digital frequency converter. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a digital inverter and a signal compensation method thereof for generating a digital compensation signal superimposed on a reference signal by analyzing electrical characteristics of an output signal.
可有效地對數位變頻器輸出訊號之正負半週訊號的不°平衡 現象作補償。 本發明係揭示一種數位變頻器之訊號補償方法。該方 法的步驟係首先，提供一數位變頻器，其中數位變頻哭 對一參考訊號作脈寬調變（Pulse width c〇mpensatln， PWM) ’以產生-輸出$號。其次，檢測輸出訊號，以债 測輸出訊號的正負半週訊號是否不平衡。隨後，當偵測到 輪出訊號的正負半週喊斜衡時，分析輪出訊號的電氣 特性，以產生一補償參數。接著，依據補償參數，產生一 數位補償減。最後，將數位補償參數疊加於參考訊號。 本發明更揭示一種數位變頻器，其包括一換流哭、一 補償訊號處理模組、一參考訊號產生模組、一合:&缸以 脈寬調變模組。換流器係根據一脈寬調‘訊號的控 以產生-輸出訊號。補償訊號處理模_耦接於換流 ，，補償訊號處理模組係對該輸以峨作檢測，以於制 ^輪出訊賴正負半週訊號不平衡時，產生―數位補償訊 Ϊ二生模組係產生—參考訊號。合成模組係耦 接於參考減產生餘以及補償訊號處理，以接收該 200843302 爹相及該數位補償訊號。合成模組係將該數位補償 —加W考訊號輪出。脈寬婦模組絲接於合成 模組：及換流器士間。脈寬調變模組係對合成模組所；出 之爹考訊號作脈寬調變，以產生該脈寬調變訊號。 以上之概述與接下來的詳細說明及附圖，皆 進一步說明本發明為達成駄目的所採取之方式、^段= 功效。而有發明的其他目的及伽，將^ 及圖式中加以闡述。 貝h兄月 【實施方式】 本發明係提出數位變頻器（Digitalinverter)之訊號補 償方法，以針紐位變頻賴丨訊號的正貞半週不平衡現 象作補償，俾以提升數位變頻器的效能。 請同時參閱第-圖以及第二圖，第一圖係為本發明所 揭綠位變頻器1G之系統架構示意圖，第二圖係為本發明 之參考訊號RW1與數位補償訊號CW1之波形圖。 如第一圖所示，數位變頻器1〇係耦接於一負载16， 數位變頻器1G係產生-正弦波形式的交流輸出訊號驅動 負載16。數位變頻器丨〇包括有一控制系統丨2與一換流器 14。控制系統12内部具有邏輯控制電路、訊號產生器、訊 號比較器等機制，以依據輸出訊號的頻率需求，產生一正 弦波參考訊號RW1 (請參閱第二圖），並以正弦脈寬調變 (Sinusoidal pulse width modulation，SPWM)技術，利用 另一三角波訊號對參考訊號RW1作脈寬調變，以產生二脈 寬調變訊號。換流器14中’電晶體qi、q2、q3、卩斗與 200843302 二極體D1、：〇2、；〇3、〇4共同構成—單 路，豆中，電曰_ 早相王橋式換流器電 /、包日日肢Q1、Q2、Q3、Q4係作 受控制系統12所輪出㈣作為開關70件，接 m、，u 見'調變訊號控制，作交互配料 通切換’以將直流電源14()的 =互配對¥ 號讀波形的輸出訊號，再透直過合參考訊 成的渡波器輪出驅動負載16。 ^ 心C1所構 第-圖中，控制系統12係耦接於換流器 以接收輸出訊號的回授訊號s卜 、輸、 的^^ m而回授訊號S2係回授輪出訊號 ?訊號S1係由―輕接於換流器14輸出 S1Γ*1應產生。控制系統12係檢測回授訊號 合包氣特性’以偵測輪出訊號的正負半週訊號是否 =4控制系統12偵測到輪出訊號的正負半週訊號不 衡便產生-數位補償訊號⑽（請參閱第二圖）疊 加於參料號RW1，輯所狀不平衡現㈣補償。 如第二圖所示，數位補償訊號㈣為一數位脈波訊 琥、，此數位補償訊號CW1係依據一補償參數所產生。所述 2償參數包括J數位補償訊號CW1的正負極性、訊號產 、、吩序ti、脈波寬度Wl與脈波高度匕。當控制系統^偵 冽到輪出訊號的正負半週訊號不平衡時，係進一步對回授 訊號Sb S2作積分運轉分析，以比較出輸出訊號中， ，正半週大於負半週，亦或為負半週大於正半週，從而決 疋數位補償訊號CW1的正負極性。於一具體實施例中，當 輪出訊號的正半週大於負半週時，控制系統12係產生一負 向的數位補償訊號CW1來疊加於參考訊號RW1，以對此 200843302 不平衡作補償；反之，當輸出訊號的負半週大於正半週時， 控制系統12係產生一正向的數位補償訊號CW1來疊加於 參考訊號RW1，以對此、不平衡作補償。控制系統12並依 據對回授訊號SI、S2的分析結果，演算出訊號產生時序 ti、脈波覓度％與脈波高度等參數，以依據此補償參數 產生數位補償訊號CW1，並將數位補償訊號CW1疊加於 參考訊號RW1。 、 接著，請參閱第三圖，該圖係為本發明所揭示之數位 變頻器10之訊號補償方法之步驟流程圖。其中相關之系统 架構與參數請同時參閱第一圖以及第二圖。如第三圖所 示，此訊號補償方法包括下列步驟： 首先，提供一數位變頻器10，此數位變頻器1〇係以 正弦脈寬調變技術對一參考訊號RW1作脈寬調變，以產生 一輪出訊號（步驟S300); 其次’檢測輸出訊號的電氣特性，以偵測輸出訊號的 正負半週訊號是否不平衡（步驟S302); 隨後，當偵測到輸出訊號的正負半週訊號不平衡時， 分析輸出訊號的電氣特性，以產生_補償參數（步驟 S304) ； 、 * 接著，依據補償參數，產生一數位補償訊號CW1 (步 驟S306 );以及 敢後’將數位補償訊號CW1疊加於參考訊號rwi(步 驟 S308)。 ’ ’ 所述之訊號補償方法於步驟S302更包括下列步驟： 首先，接收輸出訊號的回授訊號SI、S2 ;以及 9 200843302 其次，檢測回授訊號S1、S2的電氣特性，以偵測輸 出訊號的正負半週訊號是否不平衡。 所述之訊號補償方法於步驟S3G4中，更包括了比較輸 出减的正半週與負半週，以決定數位補償訊號cwi的正 負極性符制步驟。於—具體實施例中，#輸出訊號的正 半週大於負半週，係將該數位補償訊號CW1蚊為負極 性，當輸出訊號的負半週大於正半週，係將數位補償訊號 CW1決定為正極性。It can effectively compensate for the imbalance of the positive and negative half-cycle signals of the digital inverter output signal. The invention discloses a signal compensation method for a digital frequency converter. The method of the method is firstly to provide a digital converter, wherein the digital inverter cries a pulse width modulation (Pulse width c〇mpensatln, PWM) to generate-output the $ number. Secondly, the output signal is detected to determine whether the positive and negative half-cycle signals of the output signal are unbalanced. Subsequently, when the positive and negative half-cycles of the turn-off signal are detected, the electrical characteristics of the turn-off signal are analyzed to generate a compensation parameter. Then, based on the compensation parameters, a digital compensation subtraction is generated. Finally, the digital compensation parameters are superimposed on the reference signal. The invention further discloses a digital frequency converter comprising a commutation crying, a compensation signal processing module, a reference signal generating module, and a combination: & cylinder with a pulse width modulation module. The inverter is based on a pulse width adjustment of the signal to generate an output signal. The compensation signal processing module is coupled to the commutation, and the compensation signal processing module detects the transmission, so as to generate a "digital compensation signal" when the signal is unbalanced in the positive and negative half-cycle signals. The module is generated - reference signal. The composite module is coupled to the reference subtraction and compensation signal processing to receive the 200843302 phase and the digital compensation signal. The composite module is the digital compensation - plus the W test signal. The pulse width of the female module is connected to the synthesis module: and the converter. The pulse width modulation module is for the synthesis module; the reference signal is pulse width modulated to generate the pulse width modulation signal. The above summary, the following detailed description and the accompanying drawings further illustrate the manner in which the present invention is achieved, and the effect of the paragraph. Other purposes and gamifications of the invention are set forth in the drawings and drawings. The present invention is a signal compensation method for a digital inverter (Digital Inverter), which compensates for the positive half-cycle imbalance of the needle-point frequency conversion signal, so as to improve the performance of the digital inverter. . Please refer to the same figure and the second figure. The first figure is the system architecture diagram of the green bit inverter 1G disclosed in the present invention, and the second figure is the waveform diagram of the reference signal RW1 and the digital compensation signal CW1 of the present invention. As shown in the first figure, the digital inverter 1 is coupled to a load 16, and the digital inverter 1G generates an AC output signal driving load 16 in the form of a sine wave. The digital frequency converter includes a control system 丨2 and an inverter 14. The control system 12 has a logic control circuit, a signal generator, a signal comparator and the like to generate a sine wave reference signal RW1 (see the second figure) according to the frequency requirement of the output signal, and is modulated by a sinusoidal pulse width ( The Sinusoidal pulse width modulation (SPWM) technique uses another triangular wave signal to pulse width modulate the reference signal RW1 to generate a two-pulse width modulation signal. In the inverter 14 'the transistor qi, q2, q3, the bucket and the 200843302 diode D1: 〇 2; 〇 3, 〇 4 together constitute a single way, beans, electric 曰 _ early phase Wangqiao Inverter electric /, day and day limbs Q1, Q2, Q3, Q4 are controlled by the control system 12 (four) as a switch 70, connected m, u see 'modulation signal control, for interactive ingredient switching" The output signal of the DC power supply 14() is matched with the output signal of the ¥ sign, and then the wave-passing device of the reference signal is driven to drive the load 16. ^ In the first diagram of the heart C1, the control system 12 is coupled to the inverter to receive the feedback signal s, output, and output of the output signal, and the feedback signal S2 is used to feedback the round signal. S1 shall be generated by "lighting" the inverter 14 output S1Γ*1. The control system 12 detects the feedback signal and the characteristic of the packaged air to detect whether the positive and negative half-cycle signals of the turn-off signal are=4. The control system 12 detects that the positive and negative half-cycle signals of the turn-off signal are unbalanced to generate a digital compensation signal (10). (Please refer to the second figure) Superimposed on the reference number RW1, the current situation is unbalanced (4) compensation. As shown in the second figure, the digital compensation signal (4) is a digital pulse signal, and the digital compensation signal CW1 is generated according to a compensation parameter. The 2 compensation parameters include the positive and negative polarities of the J digital compensation signal CW1, the signal production, the order ti, the pulse width W1, and the pulse height 匕. When the control system detects that the positive and negative half-cycle signals of the turn-off signal are unbalanced, the integral operation analysis is further performed on the feedback signal Sb S2 to compare the output signals, the positive half-cycle is greater than the negative half-cycle, or The negative half cycle is greater than the positive half cycle, thereby determining the positive and negative polarity of the digital compensation signal CW1. In a specific embodiment, when the positive half cycle of the turn-off signal is greater than the negative half cycle, the control system 12 generates a negative digital compensation signal CW1 to be superimposed on the reference signal RW1 to compensate for the 200843302 imbalance; Conversely, when the negative half cycle of the output signal is greater than the positive half cycle, the control system 12 generates a positive digital compensation signal CW1 to be superimposed on the reference signal RW1 to compensate for the imbalance. Based on the analysis results of the feedback signals SI and S2, the control system 12 calculates parameters such as the signal generation timing ti, the pulse amplitude % and the pulse height, and generates a digital compensation signal CW1 according to the compensation parameter, and the digital compensation is performed. The signal CW1 is superimposed on the reference signal RW1. Next, please refer to the third figure, which is a flow chart of the steps of the signal compensation method of the digital frequency converter 10 disclosed in the present invention. Please refer to the first figure and the second figure for related system architecture and parameters. As shown in the third figure, the signal compensation method includes the following steps: First, a digital frequency converter 10 is provided, and the digital frequency converter 1 is pulse width modulated by a sinusoidal pulse width modulation technique to a reference signal RW1. Generating a round of signal (step S300); secondly, detecting the electrical characteristics of the output signal to detect whether the positive and negative half-cycle signals of the output signal are unbalanced (step S302); subsequently, when detecting the positive and negative half-cycle signals of the output signal, In the case of balance, the electrical characteristics of the output signal are analyzed to generate a _compensation parameter (step S304); , then, a digital compensation signal CW1 is generated according to the compensation parameter (step S306); and the digital compensation signal CW1 is superimposed on the daring The reference signal rwi (step S308). The signal compensation method described in the above step further includes the following steps: First, receiving the feedback signals SI, S2; and 9 200843302 of the output signals. Next, detecting the electrical characteristics of the feedback signals S1 and S2 to detect the output signals. Whether the positive and negative half-week signals are unbalanced. In the step S3G4, the signal compensation method further includes comparing the positive half cycle and the negative half cycle of the output subtraction to determine the positive and negative polarity signing steps of the digital compensation signal cwi. In the specific embodiment, the positive half cycle of the #output signal is greater than the negative half cycle, and the digital compensation signal CW1 mosquito is negative polarity, and when the negative half cycle of the output signal is greater than the positive half cycle, the digital compensation signal CW1 is determined. It is positive polarity.
為了實現上述補償機制，請參閱第四圖，該圖係為本 t月所揭示數位雙頻③、1Q之—具體實施例之系統架構示 意圖。如第四圖所示，數位變頻器10包括一控制系統12 以及-換流器U。控⑽統12包括了—參考訊號產生模 組m、一補償訊號處理模組122、一合成模組124以及一 脈寬調變模組126。換流器14係產生一輸出訊號驅動負載 I6。補償訊麟理餘m翻接於減g M，補償訊號 處理模組、122鑛輸^訊號作檢測，以則貞測到輸出訊號 =正負半週‘虎不平衡時，產生_數位補償訊號cwi。來 考訊號產生额m係依據變_驗則，產生—參考訊 號RW卜合成模!且124係_於參考訊號產生模組⑽^ 及補償訊號處理模組m ’以接收參考訊號RW1以及數位 補償訊號CW卜合成模組m係將數位補償訊號CW1義 加於參考訊號RW1輪出。脈寬調變模組126係輕接於^ 模組m以及換流 14之間。脈寬調變肋126係以正弦 脈寬調變技術’利用另—三角波對合成模組124所輸出之 參考訊號RW1作脈寬調變，以產生—脈寬調變訊號控制換 200843302 、4產生該輸出訊號驅動負載16。In order to achieve the above compensation mechanism, please refer to the fourth figure, which is a schematic diagram of the system architecture of the digital dual frequency 3, 1Q disclosed in the t-month. As shown in the fourth figure, the digital frequency converter 10 includes a control system 12 and an inverter U. The control system 10 includes a reference signal generation module m, a compensation signal processing module 122, a synthesis module 124, and a pulse width modulation module 126. Inverter 14 produces an output signal to drive load I6. Compensation 麟 理 理 m 翻 翻 减 减 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The test signal generation amount m is based on the change_test, and the reference signal RW is synthesized; and the 124 system is used in the reference signal generation module (10) and the compensation signal processing module m' to receive the reference signal RW1 and the digital compensation. The signal CW synthesis module m adds the digital compensation signal CW1 to the reference signal RW1. The pulse width modulation module 126 is lightly connected between the ^ module m and the commutation 14. The pulse width modulation rib 126 is modulated by a sinusoidal pulse width modulation technique using a reference signal RW1 outputted by the synthesis module 124 by another triangular wave to generate a pulse width modulation signal control for 200843302, 4 generation. This output signal drives the load 16.
償喊處賴組122⑽—檢測單元 224。檢析單元222以及-補償訊號產生單元 號的回授^TSGS，接於換流器14，以接收該輸出訊 號是否不;：。二= 貞！1該輸出訊號的正負半週訊 220。當檢、、…丈分析早70 222係輕接於檢測單元 平衡時，補ΓΓιΓ廳輸出訊號的正貞半週訊號不 析，以演曾二補口:疋222係對回授訊號S1、S2作分 波訊^减，所述之補償參數包括—數位脈 高度h 性、訊號產生時序11、脈波寬度Wl與脈波 _ 虎產生單元224係耦接於補償參數分析單 數償訊號產生單元224係依據補償參數，產生該 數位補彳員訊號CW1傳輸至合成模組124。 比之制單元22G係可利賴位訊號處理技術或類 ==對回授域S1、S2作處理，則貞測出輸出訊號的 /負半週訊號是否不平衡。所述之補償參數分析單元222 係巧數她號處理麟對⑽喊的電氣特性作分析， 以演算出償參數。所述之合賴組124射為一加饱 電路，以將數位補償訊號CW1疊加於參考訊號RW1。“ 按，數位變頻器H)中，包括參考訊號產生模組12〇 與脈寬調變模組m等機制的”技術係為習知，因此說 明書中便不再作贅述。此外，第—圖之換流器14係以一單 相全橋式換流11電路作為®例’财並非用以限制本發明 之範圍。 藉由以上貫例詳述，當可知悉本發明所揭示之數位變 11 200843302 • 頻11及其訊賴償方法’係對輸出訊號的回授訊號作 測，以於輸出訊號的正負半週訊號不平衡時，產生一數 補償訊唬噔加於苓考訊號，藉以對輸出訊號的正負半週 唬不平衡現象作補償，以提升數位變頻器的效能。。 惟，以上所述，僅為本發明的具體實施例之詳細朗 及圖式而已，並非用以限制本發明，本發明之所有範圍應 以下述之申請專利範圍為準，任何熟悉該項技藝者在本^ 明之領域内，可輕易思及之變化或修飾皆可涵蓋在以下丄 馨 案所界定之專利範圍。 圖式簡單說明】 圖； 第-圖係為本發明所揭示數位變頻器之系統架構示意 圖； 第二圖係為本發明之參考職與數位補償減之波形 變頻器之訊號補償方法 弟二圖係為本發明所揭示數位 之步驟流程圖；以及 之系===發明所揭示數位變頻器之-具體實施例 【主要元件符號說明】 10:數位變頻器 * ，120 :參考訊號產生模組 124 :合成模組 14 :換流器 12 :控制系統 122 ·補償訊號處理模組 126 :脈寬調變模組 MO :直流電源 12 200843302 16 :負載 222 ·•補償參數分析單元 'C1 :電容 L1 :電感 SI、S2 :回授訊號 CW1 ··補償訊號 ti:訊號產生時序 Wi :脈波寬度 220 :檢測單元 224 ·•補償訊號產生單元 D1〜D4 :二極體 Q1〜Q4 :電晶體 T1 :比流器 RW1 ··參考訊號 h:脈波高度Reimbursement group 122 (10) - detection unit 224. The feedback unit 222 and the feedback signal generation unit number TSTSGS are connected to the inverter 14 to receive whether the output signal is not; Two = oh! 1 The positive and negative half-cycle of the output signal 220. When the inspection, the ... analysis of the early 70 222 series lightly connected to the detection unit balance, the correct half-week signal of the output signal of the ΓΓ Γ room is not analyzed, to play the second two: 疋 222 series of feedback signals S1, S2 The compensation parameter includes a digital pulse height h, a signal generation timing 11, a pulse width W1, and a pulse wave. The tiger generation unit 224 is coupled to the compensation parameter analysis singular compensation signal generation unit 224. The digital supplemental signal CW1 is generated and transmitted to the synthesis module 124 according to the compensation parameter. Comparing the unit 22G with the reliance signal processing technology or class == for the feedback domains S1 and S2, it is determined whether the /negative half-cycle signal of the output signal is unbalanced. The compensation parameter analysis unit 222 analyzes the electrical characteristics of the number (10) shouting to calculate the compensation parameter. The group 124 is shot as a saturating circuit to superimpose the digital compensation signal CW1 on the reference signal RW1. In the "press, digital inverter H", the "technical system including the reference signal generation module 12" and the pulse width modulation module m is a conventional technique, and therefore will not be described in the specification. In addition, the inverter 14 of the first embodiment is a single-phase full-bridge converter 11 circuit as an example. It is not intended to limit the scope of the present invention. Through the above detailed description, it can be known that the digital variable disclosed in the present invention 11 200843302 • Frequency 11 and its feedback method 'measures the feedback signal of the output signal for the positive and negative half cycle signals of the output signal. In the case of unbalance, a digital compensation signal is added to the reference signal to compensate for the positive and negative half-cycle imbalance of the output signal to improve the performance of the digital inverter. . However, the above description is only for the purpose of the present invention, and is not intended to limit the scope of the present invention. In the field of this specification, changes or modifications that can be easily considered can be covered by the patent scope defined by the following Xinxin case. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of the system architecture of the digital frequency converter disclosed in the present invention; the second figure is the signal compensation method of the waveform converter of the reference position and digital compensation minus the waveform of the present invention. The flowchart of the steps of the digits disclosed in the present invention; and the system === digital converter of the invention disclosed in the invention - specific embodiment [description of main components] 10: digital converter *, 120: reference signal generation module 124: Synthetic module 14 : Inverter 12 : Control system 122 · Compensation signal processing module 126 : Pulse width modulation module MO : DC power supply 12 200843302 16 : Load 222 ·• Compensation parameter analysis unit 'C1 : Capacitor L1 : Inductance SI, S2: feedback signal CW1 · compensation signal ti: signal generation timing Wi: pulse width 220: detection unit 224 · compensation signal generation unit D1 to D4: diode Q1 to Q4: transistor T1: specific flow RW1 ··reference signal h: pulse height
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