TW200842699A - Signal processing - Google Patents

Abstract

A system (1) for calculating a convolution of a data function with a filter function utilizing an array (12) of processors (14) including first and last processors. A coefficient value based on a derivation of the filter function and a data value representative of the data function are multiplied to produce a current intermediate value. Except in the first processor, a prior intermediate value is then added to the current intermediate value. Except in the last processor, the data and current intermediate values are then sent to the next processor. Then the last processor's prior intermediate value, if any, is added to its current intermediate value to produce a result value, wherein the result values collectively are representative of the convolution of the data function with the filter function.

Description

200842699 訾 、 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 Properly stylized with modern digital processors for analysis. For example, :: in the analysis of linear time-invariant systems, such as circuits, optical devices, mechanical mechanisms, and many other systems, such analysis is becoming more and more useful today. Many of the broadest branches of mathematics and such as today's science and engineering = it = medium noun, transformation, are used to refer to an equation analysis technique. The concept of history change back to the mathematical function of mathematics. The age of the stipulations of m ‘ eight kings to deal with the function of the work of the nine, one of which is especially for Zhao double, one hundred other function to do. ' ' 'transformation can be used for a single equation or a whole set of 'where the 'transformed process is in another ^ in the different domain t: not the original equation to one of the T 叼 方 私 私The mapping of a ❶ is usually directly used to use them; f > _ & has a formula, the difficulty is more easily answered, the transformation can be carried out:: = two represents the integral transformation An inverse transform is performed to map the solution back to the original domain, and the usual form is defined as (1) g(a^)/m(a9t)dt a

VIII, κ (α,·〇 is often referred to as transformed, integral nucleus) 3019-9547-PF 5 200842699 The Laplace transform is a subset of the class and is usually particularly useful. Given a simple mathematical or functional narrative of a J 变换 transformation, Lapla: a functional narrative that simplifies the analysis of system behavior. The general form is defined as · 换 (2) z ( /(〇}=Je f(t)dt ο

20, substitution, (10)..., hour, integral and bound are redefined by equation (1). The Plass transform can be used only if s is large enough and specific ==, but these strips are flexible enough to have a functional form of a function that is actually found to be useful. A special function, for example, is not a variant of a single known function, but can be represented as a product of two functions, each of which is the result of a transformation of a known function /Γί; or ^, respectively. That is, (3) F(s)^mg(S) where g(t) must satisfy the same condition as f(t). From this association between F(s), f(t), and g(1), the relationship of the columns applies: ) ^(*y) - L{ |/(^ _ T)g(r)dT} ο It is called, the theorem of the CONVOLUTION THEOREM. It can be observed that the convolution theorem results in a transformation of the integral of only one variable. A technique similar to the numerical approximation of the integral of only the ’' variable can be applied. The equation for 歹 applies to the integral notation and the Riemann sum representation:

3019-9547-PF 6 200842699 (3) )f(t - r)g(T)dr = f{〇t_k )g(c )Δτ

0 k = Q where 'each and 〇 are arbitrarily selected in the third subinterval. In fact, the right hand side of the equation of equation (5) is approximated by the use of a very small Δτ and the knowledge that there is a certain order of error term and Δ τ depending on the selected numerical technique. Thus: (6) SS / ^ct-k )s(ck )Δτ = 2] f{ctk )g{ck )Ατ + 0(Arm) k=Q /:=0 • where m is the accuracy expressed by the sum The order (and also the number of precisions that can be expected) is the big mark in traditional mathematics. As suggested above, there are existing and possible uses in important applications that can be used to convert from gains. For example, one such application uses a combination of digital filtering performed in digital k-processing (DSP). Any filtering that can be represented as a mathematical function can be implemented using a digital ferrite, and this is a basis for modern DSP implementation. For example, digital filtering of data values sampled from a signal allows removal of unwanted portions of the signal or useful portions of the captured signal. The finite impulse response (fir) and infinite impulse response (HR) are used in two main types of digital filters in today's DSP applications, and the more common ones are FIR filters. Since internal feedback is not required, it would be such that, for example, an IR chopper responds unresponsively to a pulse, and the FIR filter pass is considered to be advantageous for use. Its name, limited, also means another advantage of the Fir filter. The pulse from this filter is finally fixed to zero and the error in the iterative total calculation used is not propagated. That is, the error term remains fixed throughout the calculation. This is an obvious advantage over the 丨IR filter, for example

3019-9547-PF 7 200842699 As in the 11R filter, the error may increase for each additional iteration output sum. Unfortunately, for many applications, the primary limitation of digital filters is that their speed is limited by the speed of the processor used for numerical calculations. For example, 'If high wave speed is required', this will make it impossible to complete the hardware mussels required for the digital filter. For almost all applications, and for a fractional electronic system it is usually true, that is, the higher the speed of use, the more difficult it is to handle consistent effects such as suppression of electromagnetic noise and heat dissipation. Therefore, improving the system we use to perform numerically-folded calculations will allow us to perform current and new signal processing with more speed, more economical, and in the basic and peripheral systems. SUMMARY OF THE INVENTION A method including a multi-computer processor is used in accordance with an embodiment of the present invention.

Calculated system. The intermediate value is added to the current intermediate value. The logic is provided to provide a system for the first feature of the present invention to provide a product of the product. Processor The last processor and each of which includes a coefficient value of one of the derivatives and an intermediate value representing the data. The first process provides a calculation to receive a previous intermediate value first w, and an array of processors other than the last processor for computing data functions and filters is provided, including the first logic, In a processor that will multiply the data value according to one of the filter function functions, a logic, which is represented in another processor

3019-9547-PF 8 200842699 and the current intermediate value is sent to another processor. A logic is provided to save j from a previous intermediate value of the last processor, if any; as a partial value of the previous part, and to add the previous partial value to the current processor The intermediate value is used to produce a result value. Thus, the write array is processed to the 2-series data values and a series of result values are generated which collectively represent the product function and the convolution of the filter function. An embodiment of the first feature provides a signal processor having means for providing a data value representative of the signal from the signal to be processed, and a system for calculating a function of calculating a product of the signal. . By way of example, the embodiment is a digital filter. A first feature of the invention also provides a method for calculating a result value in a product of a data function and a filter function. A sequence of coefficient values is obtained, which is based on the money function (four) number. The value of the coefficient value representing the functions is used in the pipeline of the processor of the computer including a first and last processor to multiply one of the coefficient values and the data value to produce the current ": value. The intermediate value of the front face of the meter which was previously executed in the other processor in the first processor is added to the current intermediate value. Except in the final processor, the data value and the current intermediate value are sent to a subsequent processor. The value of one arrow month J, if any, is added to the current intermediate value from the last processor to produce a - result value, where the previous partial value is from the previous middle of one of the last processors value. And the resulting value is output to a digital signal processor that utilizes this program. An embodiment of the feature also provides a method of processing a signal, the signal to be processed providing a data value representative of the signal, and

3019-9547-PF 9 200842699 This procedure for calculating the product of the data values by the filter function. A second feature of the present invention provides a process and a corresponding system for calculating the product of a data function and a filter function. - The coefficient values of the sequence are obtained, which are based on the number of v | θ ^ of the filter function, and the data value of a sequence is obtained, and the basin represents the data function. For each such value, each such coefficient value 7 is in the pipeline of the processor of the computer including a first and last processor: the coefficient value and the data value are multiplied to produce a current intermediate value. except

^: In process H, the intermediate value of the face of the previous execution of the previous execution in the processor is added to the current intermediate value. Except in the last processor 2, the data value and the current intermediate value are sent to the subsequent processing. A previous partial value, if any, is added to the intermediate value seen from the last processor to produce a _ result value, where the previous partial value is derived from the previous intermediate value. These resulting values are output to a digital signal processor that utilizes this process. An embodiment of the first feature provides a signal processing method and corresponding system comprising providing a data value representative of the signal from a signal to be processed, j for calculating the product of the data value by a filter function. For example, the process is a signal filtering process. The second feature of the present invention provides an improved system for calculating a product of a type in which a coefficient value representing a filter function and a sales value representing a data function are multiplied in the second to the processor. This improvement includes the coefficient values based on the derivative of the wave function. An embodiment of the second feature provides a signal processor having means for providing a data value representative of the signal from a finger to be processed, and for

3019-9547-PF 200842699 The chopping function calculates the 表示/言 of the data representing the signal, and the embodiment is a digital filter. , ^ system. For example, the third feature of the present invention also provides an improved process, in which the coefficient value represents a filter function, the data value represents a 々 is used for calculation, and the coefficient value and the data value are multiplied to generate an overall table two-material function. , the product of the type of computer's processor. The resulting value is based on the derivative of the filter function. The 'value' ❿啼th/feature-embodiment provides a reddish representation of the product from the -to-be-processed signal representing the convolution of the ^, SI ^ _ 枓 different 枓 value. For example, the process is a signal filtering process. The present invention also provides a computer program that, when run in an array of processors of a computer, causes the array to perform the processes of the first, second or third feature of the present invention. The array of computers can be located on a single semiconductor die. The computer program can be located on a carrier, - a recording medium in a computer, or an electric number, or a memory device. • As described herein and illustrated in the drawings, in view of the description of the modes of the present invention and the industrial applicability of the preferred embodiments, these and other objects of the present invention are well known to those skilled in the art. The advantages will become clearer. The purpose and advantages of this month will be more apparent from the following detailed description, taken in conjunction with the accompanying drawings. [Embodiment] The preferred embodiment of the present invention is implemented by a multi-computer processor.

3019-9547-PF 11 200842699 and especially in the general reference fold calculation system. As illustrated in the various figures herein, the preferred embodiment of the present invention in the drawings of FIG. 1 is described as simply saying that the present invention is an improved tampering system 1 〇, two proximity data functions and filtering The solution of the product's product. Using numerical techniques Stubborn calculations tend to require a large number of multiplications and additions. Two special ways to invent the phase of the invention greatly reduce this:

The overall time. First, W is allowed to complete in parallel, and "for the sake of J", the present invention allows the use of a new type of algorithm (4) to correct Hhm), which uses the filtered value and the value of the ^ which can be represented by fewer data bits. Considering the inherent limitations of the processor, it can be performed. <Figure 1 is a diagram depicting the deconvolution system 10 of the invention used in the array 12 of computer processors 14. Note the convolution system ι〇 itself, The external components of the support array 12 are generally omitted or depicted. However, it is understood that such components will appear in practical embodiments and they may in fact generally be common. For example, the figures are omitted. All details of the array power are provided and include the general form of external input device 16, input bus 18, output bus 20, and external output device 22. To simplify the table, the initialization and termination of the general calculations are not initially discussed. And the program instruction and the value of the convolution coefficient are deemed to have been loaded to the processor 14. The input device ^ is here considered to be only relevant to the input data value on which the convolution will be provided and the wheeling device 22 is here. Regarded as the only contribution expected value on the reception of this convolution to perform a wheel. The samples of the signal to be processed based input data values (e.g., filtering). Wheel

3019-9547-PF 12 200842699 The depleted material value is a signal sample that is processed (eg, filtered). At the beginning of the input device 16 and at the end of the output device 22, the flow path 24 is also apparent in the Figure 1 body. However, it should be understood that a different arrangement than this is also possible. For example, other start and stop positions are possible, and paths other than the described flow path 24 are also possible (and even more likely in alternative embodiments), and a single combination of I/ can be used instead. O loading

Set (not shown), for example, having input and output channels in communication with array 12. The intrinsic better hardware platform of the inversion system 10 has an array 12 of processors 14 in a single die 26, such as inteiiaSys

Corporation of Cupertino, California SEAforth-24A or SEAforth 4GA unit. SEAfc)rth_24A is used here in most of the examples (and the processing states 14 in these early cases can be properly referred to as "core" or "nodes"). To push a boss 4% a The components of the entire set of processors 14 are referred to individually as processors 14a-x, as shown, and each has a busbar that allows it to communicate with other processors 14 that are present, although The processors shown in Fig. 1 have busbars 28 to which they are connected to each other, and from the route of the flow path 24, it can be seen that not all of the busbars 28 must be used. In fact, the deconvolution system 10 The embodiment may be ά祛 & amp 、 、 、 % % % % 可 可 可 可 可 可 可 可 可 可 可 可 可 % % % % % % % % % % % % % % % % % % % % % % % Technology) is the processor η SEAf orth-24A in Figure 1 to deal with crying, which is the main internal processor of the core of A processing benefits... Often - independent operation of electricity: = everywhere G 术 逻辑 logic

3019-9547-PF 13 200842699 yuan (ALU 30), some read-only memory (R〇M 32), some random access memory (RAM 34), an instruction decode logic section ° data stack 4. And returning to stack 42 as soon as possible. Also included is a system 18: Ά register U register 44), a 9-bit "B" register (W memory TM 46) 9-bit program count register (P register 48) And an 18-bit I/O control and status register (I〇cs register 5〇). Further included is the four-way material (the overall material 52, respectively, the center of the material, ^ ^ the edge and corner nodes, the 淳 52 are each connected to a respective bus, 28 (and has 18 data lines, - read The line, and the write line _ are not separately displayed. The nodes in the SEAforth-24A device operate the communication and processing asynchronously in a particularly rigorous and efficient manner, making the device highly suitable for the inventive convolution system 1G. The embodiment is used up. However, it should be borne in mind that the use of this particular device, or even hardware close to its function, is not required. Similarly, it may be necessary to guard against how the data is actually in the array 12. "14" communication misunderstanding. For example, when considering communication between devices, a push or pull symbol can be used, but it should be remembered that communication is actually a cooperative behavior between devices. Figure 3a-C describes the use of a processor Figure 14 is a partial diagram of the inward, outward, and internal communication of Figure 14. Figure 3a shows how data is passed between the input device 6 and the processor 14a and between the processor 4a and the processor ^. How is the information ... between the processor and a processor over the processor ΐ4χ 14χ and the output device. FIG. 3 c, and show how the data between the processor and a processor 14i through i4j.

3019-9547-PF 14 200842699 Each processor 14 in Figures 3a-c is shown as having a general key information storage element. The SEAforth_24A device is characterized by RAM, r〇m, and scratchpad, which can be used to perform calculations in a programmatic manner. Here, it specifically refers to a general information storage component, which will be discussed, and may be any of ram, r〇m', scratchpad, and 埠. In the case of the processor 14a, the signal data π 60 is an important information holding element. In the case of processor Ubi, each of signal data element 60, integrated core filter element 62, and computed element 64 is a separate important information storage element. And in the case of processor 14x, result element 66 is an important information storage element. Now proceeding with Figure 3a, this shows how the data can enter the array 12. In the embodiment of the illustrated convolution system 1 ,, the processor is dedicated to receiving data from the input device 14 and providing it to the processor Ub. As such, the processor 14a can receive and store the data words from the input device 16 and then use the signal data elements 60 to provide an instance of these data words to the processor 14b, subject only to the performance of its RAM 34 and whether it has been properly programmed. limit. The communication and processing in the SEAf orth-24A device are asynchronous, so once the processor 14a enables the data to be utilized by the processor 14b, the processing at hand is conceptually "flowing" through the remainder of the array 12. Figure 3b shows How the data can be retrieved from the array 12. The processor 专用4 is dedicated to receiving data from the processor 14w and providing it to the output device 22. Thus, the processor 14x receives and stores the data word from the processor Uw, and The result element 66 is then used to provide the data word to the output device 22, again again subject to the performance of its RAM 34 and whether it has been properly routed

3019-9547-PF 15 200842699 Limitation of μ. Figure 7C shows how the signal data component 60 and the computed component 64 are typically moved between the processors, 14b-w, and also shows how the sum can be cumulatively stored in each processor 14 and then in the process of the fold calculation. Together, as detailed, each of the processors 14b-¥ can perform operations that facilitate overall calculations. In the case of processor 14b, this operation uses a new input body value (in its signal data element 〇6〇) and a pre-stored convolution coefficient value (in its integral core filter, wave element 62) ). In the other example of ιΜ寺, 'because there is nothing from the earlier calculation level,' the processor Ub does not need the -computed component 64. However, the simplified processing state for the program can have zero loading. A computing component 64. Similarly, for applications where the parent node multi-fold factor is processed (discussed now), the processor 14b can have and use a computing component 64. Next, in the case of the processor 14C-W By using the pre-stored value of the convolution coefficient, the input data values from the processing fronts 14 of the flow path 24 from their respective front faces, and an intermediate value also from the previous processor, each execution contributes to the entire The operation of the discount calculation. The value of the convolution coefficient is stored in the respective integral kernel filter and wave element 62, and the input data values are temporarily stored in the respective signal data elements 6G. The intermediate value is temporarily stored in each of the calculation elements 64. Figures 2 and 3a-c can be used to more generally view the processing of the 〇咐 24 24 device command If 14a-x and how the register can be used as just explained. For example, processor 14a uses its port 52d to pass the wheeled data value to the right to processor 14b, which can be placed in its data stack.

3019-9547-PF 16 200842699 Then, the processor 14b performs the operation that contributes to the convolution using the input data value now in its data stack 4 and the value of the convolution coefficient of the data stack 4 After processing @ 14b, the intermediate data value is placed on its bee 52d. A similar operation can then occur along the flow path 24 in the processor 14b_w. Although the nodes in the SEAf〇rth_24A device operate asynchronously, the operations in processor 14bi are here all conceptually considered to occur in parallel. Thus, substantially similar operations can be performed in processors 14i and Uj, just as the processor Ub has just explained, for example, only these will use the respective convolution coefficient values, process the intermediate data values, and use them along The enthalpy 52 of the flow path 24. Also substantially simultaneously, the processor uw will cause the output data value to be used to process $14 at its 埠52c to operate as described above. However, it should again be noted that RAM, R〇M, scratchpad, and 埠 can all be used programmatically in the drain Qrth_24A device and this previous example is only a number of processors 14 that can be programmed to achieve the same result. One of the modes FIG. 4a-f is a block diagram summarizing the calculation stages of the folds in the array 处理器 of the processor 14 such as FIG. Usually, the stage needs to: (1) multiply the data sample value and the convolution coefficient value in parallel; (2) calculate the sum of the products from the level (1); (3) pass through the array 12 (ie, Shifting the data sample value by pipeline, receiving the next data sample value entering the first node and discarding the data sample value from the last node; and (4) repeating as needed (ie, as explained in more detail now).

3019-9547-PF 17 200842699 Because the SEAf orth-24A device is characterized by RAM, ROM, scratchpad, and UI, all of which can be used for computationally performed calculations, and because the inventive deconvolution system 10 can Used in conjunction with other devices having smaller, larger, or Z-like properties and structures, the data storage elements of Figures 4a-f are generally referred to herein as "bins." To simplify the discussion below, the example hereby makes 2 identical number (specifically, 22 each) of the weight coefficient value, the sample data value, and the processor H used in the exclusive accumulation calculation. These Lu# styles may be rare in many "real world" applications, so considerations for alternative situations are now discussed, and in any case, one is fully understood below, using other equations for those skilled in the art. It is simple. Figure 4a shows the formal calculations at the level at which they are ready to begin. The value of the convolution coefficient (cd··· Cn ; a total of n + 1 values, of which in the SEAforth-24A device in Figures j and 3a-c, n = 21) has been loaded into the box (the whole is called For the c-box 72, specifically, the c-box zero is loaded into the other box (the whole is called the d-box 74, specifically the d-box 74 (..1〇, and the other boxes (the whole body is called For the r box 76, specifically the box r... 2^) has the content that was initially unimportant. In the discussion of Figures 4a-f and below, the index starts at zero and c stands for "coefficient"," d" stands for, data", "a" stands for "cumulative" intermediate value, and "r" stands for, the result". Figure 4b shows that the first data sample value has been received into the d-box 74 ((〇 The next level is calculated by the first result value (η) stored in the r box 76(()) through the entire length of the official line substantially simultaneously and in parallel as shown. Figure 4c shows the previous data sample value ( dQ) after it has been moved to d box

74 (u and the second data sample value (dl) has been received into the next 3019-9547-PF 18 200842699 level of the d-box 74 (〇). The second result value calculated to be stored in r |g 76n) The entire length of the (ri) pass line is again substantially simultaneously and in parallel as shown. Between Figure 4c and Figure 4d, the knives, grades, are conceptually reported as just stated. Figure 4d shows the last data sample value (dn) at the level it has been received into the d-box 74 (.). The calculation is again performed with the result value (rn) now stored in the box 76 (4) as shown. Art Figure 4e shows the next level. All of the data samples (d〇".dn) have been partially processed, and the last data sample value (dn) has been moved into the box 74(1) and the value of zero is placed in 4 boxes" (1). The calculation continues and a result value (rn+1) is stored in the r-box 76(n+1). There is another knife-level between Figure 4e and Figure 4f, which is conceptually just like Figure 4f shows the final data sample value (dn) at the end of its final processed level. After the calculation here, the (/7 young_7) result values are stored in ".1 76UH". And the processing is completed. The box 76 (^" now saves the complete result of the calculation of the fold performed here according to the data sample value (do..·d„) and /70% product coefficient c〇. Figure 5a-f A block diagram that summarizes the calculation steps of a new algorithm based on a new algorithm that appears again in array 12, such as processor 14 of Figure 1. Briefly, the new algorithm uses the derivative of the filter function. To emphasize this The value of the convolution coefficient used here is denoted by c, . . . , c, 1 (wherein, in the SEAfor1:h-24A device of FIGS. 1 and 3a-c, m=2i ; The reason why the lead is used when using different references to the index here is now discussed in 3019-9547-PF 19 200842699. Figure 5a shows the formal calculation at the level at which it is ready to begin. Derivative arbitrage coefficient values (c , ....c' 〇0 has been loaded into the box (the whole is called c, box 82, specifically the c' box 82U.10, zero is loaded into the other box (the whole is called d box) 84, specifically, the d box 84 (... π)), and the star one, the dry phase 86 and a set of result boxes (the whole is called the r box 88, specifically the box r 88 (〇 m) has content that is not initially important. A bit like the previous example, the index starts at zero, and,, c, ', represents, the coefficient, the derivative, "d, again represents the "material", "a" again Representation, cumulative, intermediate value, "representative" part '' (same as contributing to the result, part, and), and "representing the result". Figure 5b shows the first data sample value (d.) At the next stage where it is received into the box 84m. The calculation is to provide the first partial value (^) of the p-box 86 through the entire length of the pipeline. Simultaneously and in parallel as shown in the figure. However, unlike the variation of the conventional convolution algorithm shown in Figures 4a-f, the previous partial values are added here to the current partial values, and then this It is stored in the box (10) (4). Because there is nothing in this early stage, the previous '', however, zero is added to the first part value (p〇 to calculate the first result value stored in the r box 88m) (r.) Figure 5c shows that the previous data sample value (d.) has been moved to d-box 84(1) and the second f-sample value (di) has been received into d-Shao 84 (. The next _ level. The calculation is performed again with the entire length of the pipe line by the second portion of the value (p) that is now provided i 86 ± simultaneously and in parallel as shown. The previous partial value (p〇) is added to the current partial value (ρι), and then this is stored

3019-9547-PF 20 200842699 as a second result value (n) in the r box 88(1). Between the figure 5c and the 5d, it is conceptually reported as the level just stated. Figure 5d shows the final data sample value (d〇 after it has been received into phase 84 ((υ level. The calculation is again stored in the box 88(4) now - the double result value (rm) is not shown Figure 5e shows the next level. Now all the melons are processed in part (d{r"d〇, the last data sample value (d〇 has been moved into d box 84(1) and zero The value is placed in the box "(4). The calculation continues and a result value (rm+1) is stored in the r box 88 (m+1). There is another w level between Figure 5e and Figure 5f, the concept It is very similar to the level just described. Figure 5f shows the last data sample value (I) at the end of its final processing level. After the calculation here, the (__ plus result value (~) is stored in I · Box 88 (1) and the processing is completed. The box 88 (. 2m ” now saves the data sample value (de...d〇 and the heart derivative value of the derivative value (C' 折 the discount product performed here) The complete result of the calculation. In summary, from the above, it should now be clear that the inventive deconvolution system 1〇 allows the calculation of the necessary calculations to be done in parallel rather than in series. For example, in the simplified example just described, 22 processors 14 perform calculations in parallel. Note that all of the processors 14 in the SEAf〇rth_24A device can also be used, but because of the processor Ua and processor ι4χ will have to have two functions to suit the calculation and 1/〇. As mentioned at the beginning of this paragraph, the inventive deconvolution system 10 also allows

3019-9547-PF 21 200842699 The new type of algorithm is used to discuss its features. Figure 2 is a diagram depicting the products of the products using the current two methods. These figures provide a conceptual overview of the ones appearing in Figures 4a-f and 5a-f. Figure 6a shows a first graph (trace) 92 using conventional index coefficients and a second graph representing the use of derivative index coefficients (deviation (3) (4) (10) (10) (1), which is the user of the type that can be used: It can be used in the present invention. Figure 6b shows an early pattern 94 of input data executed using the two methods that have appeared so far (here another pattern one main 94 is now discussed). Figure 6c shows no The single-graph 96 of the results of the two methods discussed so far. In the particular example shown in the figure, the graph 92 is represented by the following equation: (7) w (〇 = 10cos2 2 Figure 幵 / 92 is represented by u' (t). Figure 94 # Α He 口 $ 94 is represented by the following equation: int (8) v(r) = 〇.8cos =94'...(1). Here, t is the step size., 01 ^yi n to 1 In the interval '" the step size of i is from uc, and "the number of data points passing through the filter function (in this case, 2_. The whole = in terms of 'Figure 6a-c shows how very the same result can be used so far) Any of the methods discussed is reached 'The result is shown as a graph here i other methods are also possible With a new kind of algorithm, for example, again, Figures 6a-c, derivative data functions, such as those represented as graphics μ, and - traditional filter functions 'for example, represented as graphics 92, can be rendered in graphics 96. The results will be the same again. The literature suggests that others consider this side.

3019-9547-PF 22 200842699 Law, although not implemented in the new manner disclosed herein. The use of function derivatives can also be used more logically. For example, the use of data and the derivative of the filter function is theoretically possible. Further, it is theoretically possible to use higher order derivatives of either or both of the data and the filter function. In fact, these methods may have limited real-world utility, but they are still covered by the spirit of Ben: Ming. In Figures 6a-c, the derivatives of the data and filter functions are represented by graphs 92' and 94' and have the results of those still in graph 96. • (iv) The required force of the function derivative leads to some important considerations in the case of ^^. In the calculation of the convolution, two materials are used, and the number of values usually exceeds the number of coefficient values used. Therefore, it is less necessary to obtain the derivative of the new age of the wave function. The force is usually less than the derivative of the data function. Furthermore, because of the special circumstances of the fire, this may be quite dilute 4 β i ”, and when the field performs multiple-fold calculations on the data samples that are usually different, the filter coefficient value is 赍B 4 重 重 重 重 重 伤The system can use Got's 'acquisition of the value of the wave coefficient in many applications'. This is the force of amortization, and more precisely, it is input as the design and the filter and wave value can be reduced. (10)-24A_ sets the binary number (for example 'even if it is stored in ROM 32 like the π device). Continue to refer to the figure with a significantly smaller vibration C' can be seen when the graphic 92, * graphic 94, amplitude range. Actual To: Tian Qianwei: Graphics 92 and Graphics W have large, less-usable bits. The graphic 92' & graphic 94, the value in the digital processor is: Consider the nature of the available tools, also Just another 1 hour, you can understand the importance of this point.

3019-9547-PF 23 200842699 The SEAf orth - 24A device is actually quite good in many other suitable devices. Here we will continue to use it to illustrate how the inventive folding system 10 can often help overcome some modern The inherent limitations of digital processors. For example, the convolution filter value in pattern 92 may have to be represented using a value of 丨8 bits, and the value used in the present invention in Figure 92 may be represented by a value of 9 bits or less. Similarly, it can be considered that the data sample values used in the pattern μ may have to be represented by values of 18 bits, and the values used in the drawing 94 of the present invention may use values of 9 bits or less. Representation j The present invention observes that using all of the 9-bit values would increase the speed of the convolution system 10 of the present invention by a factor of about 4 (4X). The digital processor is inherently limited in terms of the number of values that they can perform directly on the operation. For example, Intel's right 4 processor in mi year handles a 4-bit value, and now the processor in a PC directly handles 32 or 64-bit values. In addition, the multiplication of a woman's dilute and extraordinarily large value is usually one of the slowest operations that can be performed on most processors today. The inventors observed that the multiplication operation would occupy the execution time of the convolution algorithm 6〇_9〇%. The SEAf orth-24A device is not the same as the number of imaginary crying < a pair of exceptions to the general principle of the state. It uses the Forth language and relies on a numeric value represented by an 18-bit (or a 17-bit symbolic value) that has no value for the helmet. The value is like a 9-bit unsigned value (or The octet + symbol of the symbol value is not shown. For example, if a value requires 10 bits, it must therefore be clouded, s. Β_ /, and 18 bits - effectively processed. Looking again at Figure 2, you can see the alias π Λ ρ again. The Dan people have a processor 18 in the SEAf0rth_24A device with an 18-bit A temporary temporary state 44, a 9-bit beta temporary

3019-9547-PF 24 200842699 The memory 46, the 18-bit wide character in _32 and RAM 34, and the 18-bit wide 埠μ 〇 here are two 18 of the Forth language in processor 14. The equivalent of multiplying the value of a bit requires thirty-six opcodes of the following sequence (where ·· represents HOP or non-operating instructions and “+*,” indicating a plus-asterisk or bitwise multiplication instruction):

• Conversely, the equivalent of multiplying the value of one 18-bit and the value of a 9-bit in the Forth language in processor 14 requires eighteen arithmetic codes of the following sequence: The equivalent of the two 9-bit values of the Forth language requires the following nine arithmetic codes. (11) It is clear that from the point of view of the computational burden and the achievable speed, the equation (9) is The least favorite job, and the calculation of equation (11) is the favorite job. This can be said to be performed at speeds of lx, 2x and 4x, respectively. A more rigorous proof of the above conceptual basis is now proposed. A new kind of algorithm that can be used by the inventive convolution system 10 uses a derivative representation instead of a direct representation of the integral kernel (see, for example, for example Equation q) and prior art). The following is essentially a restatement of equation (5): (12) r{t) = jf(t - T)g(r)dr = limA_〇2/(c^)g (c,) Ar 〇k=0 3019-9547-PF 25 200842699 where ' /T b r) denotes the integral kernel. However, it is assumed that the integral kernel is changed by /, "divination. This will result in the following formula: (10) r ( ')= j/'〇-〇g(r)^r = lim". t/'D coffee) 〇*=〇 Now suppose that the integral kernel is a special low-pass filter or can be represented by a low-pass filter, then the following approximation is reasonable: (14) / {ct__k) = f( Ct^k)-/(ct_k_A7k ) and therefore:

t lim X \f{ct_k) ~ ^ )Ατ = ^^/(^ )Ar __ ^ ^^ Moxibustion=〇Λ=〇(15) Here, it is easy to see the first right side of the equation (14) equal sign The sum is wide (a). It is obvious that the second item on the right side of the equal sign is exactly the previous convolution value from exactly one time step, and this can be expressed as follows: δτ^2)Σ f (ct- k-AT )s(ck )Δτ = r(t -At) Therefore, the following relationship holds between the product of the direct integral kernel relationship and the derivative of the direct integral kernel relationship: (1?) Γ, (〇= Κ〇-^-Δ,)^,(〇= ,.(〇+ Γ(ί_ΔΓ) This is an important observation that understands that the use of the direct representation of the product is exactly the same as the index and the nose. The sum of the sum of the sum of ... and plus any that has been counted, the equalizer is the new type used in the sample. • Cn) can be used to apply this algorithm to the integrative system of the invention. Directly according to the wave coefficient 1

3019-9547-PF 26 200842699 Calculate the derivative coefficient value (c ’ in the following manner

C η +

Cl - Co ; C, 2 = C2 - Cl ; i) : C' =Co

C

Cn C 1 and C'... = 0 - Cn. However, Sc. The value is non-zero, so we easily get c'. = CD _ 〇 = Cfl. Similarly, if c. If it is zero, then we can easily get c,. = 0 — 0 = 0’ and there is no reason to combine the data-wave value with the value of zero because it does not contribute to the accumulated intermediate value (a.). Such inferences can be extended to any direct chopping value or any derivative of direct chopping value of zero' because it would not require a filter coefficient value if it would not contribute to the accumulation of the intermediate value in the Xiao node calculation. Combined with a special node. However, in addition to the first node, the parts of each node must still be explained. Now go back to why Sπ is used in Figure 4a_f and index continued use = Figure 4a-f, which is done to emphasize the key differences between using direct and derivative algorithms. As you can see in the last paragraph. To which 10,000 direct wave coefficient values U.... en) can be used, a derivative coefficient value (C ° . . c η+1) is required. Thus, for example, if one person applies 21 places = The application of the direct algorithm will require 22 processors for the same application using the derivative algorithm. Or, if one person will use 22 processors to apply the direct type algorithm, use the derivative algorithm. For the same application, 23 processors will be required. In the case of the SEAf orth-24A device in Figure and 3a c, this will require a processing benefit or a 1/〇 function to be incorporated into a processor. This allows 23 processes to be used by a derivative algorithm. This can cause minor problems when using a device with an η processor (such as SEAF ort), but it is using a 40 processor device (eg SEAf〇) Rth_4〇A) is less

3019-9547-PF 27 200842699 is a problem and it is in normal use. 80, 96, 128, etc. devices change rapidly. Note that the discussion here is simplified by using the same number of convolution coefficient values and sample data values. If there are 22 sample data values to be processed when using the direct type algorithm, then (1) the solid sample data values will be processed when the number algorithm is guided. Of course, 22 real (four) data values can be used and: padding the 23rd value of zero. However, more usually, because of the large number,

Sample data values that may be close to infinity will be used in most real-life applications, so this will not be a problem. The advantage of /k' to the direct representation of the number table is that the value required to represent the amplitude of the ¥ number is typically much smaller than the value used to represent the direct chop _. According to the disclosure of the SEAf orth_24A device, it is used again as an example to replace the data words that require all 18 bits to indicate that the amplitude value 'usually a 9-bit data word is sufficient. Making a 9-bit table cannot be considered sufficient for two requirements. The first is that the coefficient value is represented as an unsigned value of 9 bits (or a symbolic value of 8 bits). The second condition is that the sum of the direct coefficients of the continuous coefficients is represented by the unsigned value of 9 bits (or the value of the 8-bit 兀). In the case of a typical low pass filter, such as those made in the examples of Figures 6a-c, since the most significant bit is reserved as a new value, the derivative value will have to be represented by only 8 bits. As a general rule / # right problem value is an unsigned value or can be used as an unsigned value, and then the difference between the direct coefficient of the right and the right is less than 5 〗 2 units, the derivative is close to 疋 尔method. Otherwise, the difference between consecutive direct coefficient values must be less than 256 units. ^

3019-9547-PF 28 200842699. Here, FIG. 7 is a schematic diagram of the coded language of the direct filter 700 exemplified by Forth, the target hardware processor SEAforth-24A device. " Item 702 is the same as, ίο "equivalent to i〇CS鲂六Γ Γ", temporary compilation is 50 compilation instructions. This will specify where the data is read from and where it is written. Noteless, the I〇cs register 5 in the SEAf 〇rth-24A device can be read and written at the same time. To avoid confusion, those familiar with less sophisticated devices should keep this in mind when reading the instructions below. The item m is such that the "r# is the same as the compile command of the coefficient value. Here" is only used as an example value. This will be in the c-box 72 of the processor 14. Item 706 is annotated in the Forth language. Item 708 is a location tag in the Forth language. Item 710 is a sequence of Forth instructions that initialize processor 14 to perform a convolution calculation. Specifically, 1〇 is loaded to the top of the data stack; then, from there, it is taken out into the B register 4 6 to point to the scratch register 5L and then 'n is carried to the top of the data stack; A non-tool instruction will fill the instruction word using #18 bits here to contain this sequence of instructions. Item 712 specifies the starting point of the loop in which the three conditions of the towel are conditionally compiled. This depends on whether the program is designed for the processor 14 for the first (processor ub), the middle (any one of the processors 14c-v), or the last (processing _uw) in the pipeline. See also Figures 3a-c. Member 714 here specifies the compilation of the most typical case

3019-9547-PF 29 200842699 Point, that is, the case where the main processor 14 processes one of the processing states 14c-v. [Notes on the right side, the annotation on the right side of the instruction word in Figure 7-8 shows the data stacking and returning stack p and the old one, where the elements to the right are in the early stack. ^ Take the top. The additional explanation in the following description shows that this is transformed into a top-back and south-south-left and left-left structure of the top, which is encountered in many Forth original texts. In this way, the second architecture is provided to make this example easier to understand. ] Item 716 is a separate-sequence Forth instruction. Specifically, a data sample value (s) is read from the B register 46 and pushed onto the data stack (h--sh); then, a cumulative value (a) is also read and Pushed onto the data stack (sh-ash); then, the upper element on the data stack is taken out and pushed back to the stack (1) ·· ash — shR ·· —— a) on the upper part; then, in The upper element on the material pile is copied and pushed onto the data stack (7)·· sh--ssh R : a — a). Next is item 718, in which the upper element on the data stack is taken out and pushed onto the upper portion of the return stack (D ·· ssh--sh R : a--sa); then, a large multiplication is performed ("MULT", the definition is provided in the BIOS of the SEAforth-24A device). The last two elements of the data stack are used here as multipliers and multiplicands, and when the multiplicand is made like the data stack (D ·· sh —a' h R : sa--sa) When the two elements are the same, the upper element is replaced by the result (a ' ). Next is item 720, in which the upper element on the return stack is taken and pushed onto the data stack (D: a, h--sa, hR: sa - one 3); the upper element of the data stack is taken out and Write to B register 46 pointing

3019-9547-PF 30 200842699 〇>:Sa' hi' hR:a —3); the upper element of the return stack is taken out and pushed onto the data stack (D:a, aa,...b) And a non-transfer instruction fills the 18-bit instruction word used. Next is the item 722' where the 'top two elements of the data stack 7 are added together' the upper element is replaced by the new accumulation and (a,,) and the second element is sub- (four) low (D:aa , h — a,, 卜 r: —). ,

Following item 724, the main processor 14 is terminated by processor ΐ4. Conditional compilation of the code of the case of one of -v. Understanding the other two conditions shown in Figure 7 should now be simple. Since there is no cumulative value of W to be read and phase #, the processor (10) condition is relatively simple. And because the current data sample values do not need to be written to the "subsequent", the case of the processor 4v is relatively simple. The target system 726 is compiled for all processors 14bi to make the sequence 'where' data stacked. The upper element is pointed by the B register 46 (D: a, and is inserted into the item 712. ...) and then looped back to the derivative illustrated in Figures 8a-b. Figure 8a shows that the execution is conceptually similar) The encoding of the function of Figure 7 and the additional encoding used by the graphing. The encoding list of the filter 822, where (in addition to the 9-bit to 18-bit calculation 8b shows the derivative-based calculus as can be seen in Figure 8a Seen in the direct filter 700 is the same. Among them, 9 plus asterisks (''+*,, (instead of using the MULT definition is executed here, many of the codes are essentially discussed above, with one exception being item 802 , ) is used to perform a large multiplication of small multiplications).

3019-9547-PF 31 200842699 Item 8 0 4 is a sequence of Forth instructions that initializes the partial value (ρ) of the return pile to zero. Presented as 丄/, body and g, where a constant value is placed on the data stack (D: h--ph R :-); wonderful / M _ . ; on, and then pushed from there to On the top of the heap (D· ph h R · — p), the two non-computing instructions are used to fill in the instruction words. [Note] This particular method was chosen to make it easier to interface with the direct chopper 7GG, and the skilled programmer understands that there is a more efficient and precise way to handle this]. The 'item 806 operation then uses the additional addition of the current partial value (P). The current partial value (p) is taken from the return stack and pushed onto the data heap (D,, 'h--pa,, hR:p-); the first non-operational instruction takes: the time before the next-instruction; The upper two elements of the data stack are added together, wherein the upper element is replaced by the sum of the next part (p') and the cumulative sum (a, ,), and the second element is replaced by the next lower element: pa , h--P' hR: -) is substituted; and the second non-operational instruction is padded with the instruction word of the bit. • Item 808 then reserves the cumulative sum (a, ,) in the return stack to be proud of the next part of the value (p,). The cumulative sum (a,,) is copied (D ·· 3 hpa hR .); the next part of the value (p,) is taken from the data stack and pushed back to the stack (D ·· a,,,, hr ·~ , and the two non-operational instructions fill the 18-bit instruction word. Returning now to Figure 8b, this shows the extra code that is used for the "integrator" step when using the derivative-type algorithm. Note that here In the special case, this code will run on the extra processor 14. Item 810 is an annotation in the Forth language and item 812 is F〇r

3019-9547-PF 32 200842699 Location marker in the language. This code can be conditionally compiled via the addition of appropriate compiler instructions to the code in Figure 8a, or it can be compiled separately. Item 814 is a sequence of Forth instructions that first pass the value of IQ to B register 46, and secondly to the value of $3F (埠 address) to a register 44.

Item 816 is another sequence of Forth instructions. Specifically, the lean material stack is zeroed. The upper elements on the stacks are copied and pushed onto the lean stack, and then this is done again (which is independent of what the upper element is). Then, the two topmost elements are taken from the data stack, mutexed or computed, and the result (zero) is pushed back onto the data stack. Item 818 specifies the starting point of the loop. Item 820 is another sequence of Forth instructions. Specific and ancient, one broadcast

The port UL 攸B register 4 6 is read and pushed onto the data stack; then, the last two elements on the greedy stack are added and replaced by the upper element (and the second element is compared to the next element) The lower element is replaced); then, the upper element on the data stack is copied and pushed onto the data stack; and then the upper element is taken from the data stack and written to the A register 44 pointing. This: The net result is output and is also saved, and a copy is also saved (cumulative) for the next execution of the loop. Person Project 822 is looped back to Project 818 there. As can be seen, the derivative type algorithm used by the convolution system 10 of the present invention requires very few extra codes. Although the various embodiments have been described above, it is to be understood that the invention is not to be construed as limited by the scope of the embodiments of the invention described herein.

3019-9547-PF 33 200842699 Meaning. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram depicting a deconvolution system of the invention used in an array of computer processors; FIG. 2 (technical technique) is one of the processors in FIG. 1, particularly here Many of the IntellaSys corp〇rati〇n 〇f used in

A pattern of the main internal features of the core of the SEAF〇rth-24A processor in Cupertino, California; / Figure 3a-c is a partial diagram depicting the inward-outward, and internal communication of the processor in Figure 丨Which figure? _ ^ The picture is not poor, how to pass the input device and the first processor between the fisherman, the younger brother and the second processor, Figure 3b shows how the data through the second w And between the last processor and the final processor and the output #罟J ® device, and Figure 3c shows how the data is processed by the two examples used in the financial center, Figure 4 a - f is outlined in the figure 1 to the calculation level of the block diagram; the processing of the array of the distribution system is outlined according to the block diagram of the new calculation algorithm of the new algorithm reappearing in the column of the processor such as μ; Describe the pattern of the product using the two methods shown in Figures 4a-f and 5a-f. The 传 of the 1-pass number, /, Figure 6a 』 does not indicate the use of the traditional depreciation of the brother-one graph and the use of the derivative fold The 6b of the product coefficient shows the first graph of the input (4) of the derivative data y ^ and the second graph port bC of the poor material.

3019-9547-PF 34 200842699 The result of a single graph; in, 8b is shown in a different diagram of the schema, or a similar component or step. Figure 7 is a list of codes suitable for use in a direct filter. And Figures 8a-b are coded tables suitable for use in a derivative waver, and Figure 8a shows a function that is conceptually similar to the figure. The encoding is illustrated and illustrated by an additional encoding used by a derivative-based algorithm. The same reference symbol is used to indicate the same

[Description of main component symbols] 10: Deconvolution system; 12: Array; 14 · Processor; 1 6 · External input device; 18: Input bus; 20: Output bus;

22 · External wheeling device; 2 4 · Flow path; 2 6 · Grain; 28: Bus bar; 3Q: #术逻辑单元; 3 2 'only § buy memory; 34 · Random access memory; 36: Instruction decode logic section; 38: instruction area;

3019-9547-PF 35 200842699 40 : Data stack j 42 : Return stack 9 44, 46, 48, 50: temporary storage 3S · σπ , 52 : 珲; 60 : signal data component; 62 : integral nuclear filter component; 64 : Calculated component 66: Resulting component 9 Ί2, 74, 76, 82 '84, 86^88: box; 92 > 92, 94 94', 96: graphics; 700, 822: filter. 3019-9547-PF 36

Claims (1)

200842699 X. Patent application scope: Array of processors, including: ##Batch function and filter function, including the first and last parts, the processor includes: ° τ dry material The λ2 heart is multiplied according to the derivative value of the filter function and the data value of one of the Bebe function to generate a current intermediate value. In the processor other than the processor, the logic is used to receive a 刖The median value of the face, 1 捍 4 z, the table is not in the other of the processor, the intermediate value of the previous (4) is added to the current intermediate value; and the processing other than the withdrawal of the money, the data Value and 兮 "AA uses the value of ", and the value is sent to another processor; and the value, if ΓΓ / is used to save the middle october force from the front of the last processor: words as a front The partial value 'and the previous part: ° "the current server value of the last processor; and ν'α where 'the array of processors receives a series of data values and produces tampering. The result value, which collectively represents the data function and the wave function, is the system of claim 1 wherein the processor performs the processing in a focused manner.卞 Γ 1 牛 L as in the system of claim 1, wherein the processor performs processing asynchronously. F4. The system of claim 1, wherein the processor is in communication with each other asynchronously 3019-9547-PF 37 200842699. • As in the system of claim 2, 3, or 4, in the bean, the processor of the multiple occupies the semiconductor die of the single. For example, the system of the patented dry cofferdam 5, wherein all of the arrays treated by this occupy the semiconductor die. The system of any one of claims 116, wherein the processing H each further comprises a wave storage element to preserve the coefficient value. 8' The system of any one of the claims of the present invention, further comprising - logic 'for receiving the data value from the outside of the system into the first processor. A system as claimed in any one of claims 1 to 8 further comprising a logic ' external portion of the result value of the last processor. The system of any one of the preceding claims, wherein the logic for storing the previous intermediate value is located in the last processor. ° 11. A method for counting the result values in the data function and the convolution of the filter and wave functions, the method comprising: (a) obtaining a sequence of coefficient values based on the derivative of the filter function; b) for a data value representing the data function: (Ο For each of the coefficient values, in the pipeline of the processor of the computer including the first and last processing states: (A) the coefficient value and the data value Multiplying to produce a current intermediate value; 3019-9547-PF 38 200842699 (B) In addition to the first processor, the intermediate value before the calculation previously performed in the other of the processors is added The current intermediate value; and (C), except in the last processor, the data value and the current intermediate value are sent to a subsequent processor; and (1) a previous partial value, if any Adding the current intermediate value from the last processor to generate a result value, wherein the previously repaired partial value is from a previous intermediate value of one of the last processors; and (1 1 1 ) The resulting value is output to a digital signal using this process 12. A method for calculating a product of a data function and a filter function, the method comprising: (〇 = to a sequence of coefficient values 'based on the derivative of the filter function; (b) 彳 to one The data value of the sequence representation data function: (C) For each of the data values: Lu (1) For each of the coefficient values, in the pipeline of the processor including the first and last processors of the processor: (A)胄 the coefficient value and the lean value are multiplied to produce an intermediate value; j (B), except in the first processor, will represent the previous execution of the calculation in the processor The intermediate value is added to the current intermediate value; and (C) the data value and the current intermediate value are sent to a subsequent processor in addition to the last processor; and 3019-9547-PF 39 200842699 ( Ii) a previous partial value, if there is a current intermediate value of the processor to produce a - knot:: to the subsequent partial value from the last processor before the intermediate value of the 'the face is not; (4) accumulating the result value of (C) as a product; (e) rounding the fold to a digital signal processing using this method 13. The method of claim 12, (c) (1) (A) is to perform 0 for a plurality of the data in the plurality of processors, wherein the value is simultaneously 14 The method of the present invention, wherein the (c) (1) (1) is performed simultaneously in the plurality of the processing materials. 1 5 - a system for calculating a product, wherein: at least one processor multiplies a coefficient value representing a filter function by a data value representing a data function; Where: the coefficient value is based on the derivative of the filter function. 16. The system of claim 15, wherein the system further comprises a plurality of the coefficient values being multiplied in parallel by the plurality of data values. 17. A method for calculating a product in a processor of a computer, wherein: the coefficient value represents a filter function; the data value represents a data function; and the coefficient value and the data value are multiplied to produce a result The value, which is the whole 3019-9547-PF 40 200842699, represents the fold; and wherein: the coefficient value is based on a derivative of the filter function. The method of processing the clause 17 of the patent scope of 1|8 is further included in the plural number 19; and the plurality of data values are simultaneously performed. The signal processor 'includes a system as claimed in any one of claims 1 to 10, broad, and I6, and means for providing the data value of the slave signal. .2〇· A method for processing signals, including deriving the data value of the 亍仁号 from a nickname and the new 撼 宙 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( 17, the item filter L1 device, such as the signal processor of the 19th patent scope, which is the method of applying for the patent 20% of the patent, and the signal-filtering 23 computer program, ♦ + ^ B4 # r Field runs in the array of computer processors to enable the array to execute the patent application--method. Close m to 14, 2G, 22 of any of the 25 such as: the carrier 'as contained in the patent scope 23 The program of the item is recorded on the program of 24 items, which is a recording medium 3019-9547-PF 41