200841398 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體電路結構及其製造方法，特別 是有關於一種半導體元件及其製造方法。 【先前技術】 隨著積體電路領域的快速發展，高效能、高積集度、 低成本、輕薄短小已成為電子產品設計製造上所追尋之 Φ 目標。對目前的半導體產業而言，為了符合上述目標， 往往需要在同一晶片上，製造出多種功能的元件。 將高壓元件與低壓元件整合在同一晶片上，例如系 統單晶片（system on chip，簡稱SOC)是可以達到上述要求 的種方法。然而’為了能夠承受較高的崩潰電壓 (breakdown voltage)，高壓元件中閘氧化層的厚度往往 遠厚於低壓元件中閘氧化層的厚度。這麼一來，將使^ 高壓元件與低壓元件的整合製程當中，出現種種難題广 為了因應閘氧化層厚度不同的需求，一般的作法是 先形成一整層厚度約大於300埃的高壓閘氧化層，然後 利用微影蝕刻的方式，移除低壓元件區部分的高壓閉'氧 化層。之後，再形成低壓元件區之低壓閘氧化層。而且， ，於高壓閘氧化層同樣會龍於高壓元件區上預定進^ 離子植入的區域，如源極/及極區、井區接點摻雜區等丁 因此，為了便於控制離子植入的濃度、深度與輪廊’ 往需要再以另-道《彡侧_，雜這魏域上 壓閘氧化層。此種方法需要的光罩鮮，不但县= 造流程、增加製程的複雜度，也會提高製造成本。、衣 6 200841398 【發明内容】 有鑑於此’本發明提供一種半導體元件的製造方 ^ ’利用同一道製程，於移除低壓元件區上介電層的同 時’一併移除高壓元件區中，預定形成源極/没極區與井 區接點摻雜區上的介電層。 、&本發明提出-種半導體元件，在高壓元件區巾，預定形 成％^區之基底上所設置的介電層，與低壓元件區中之閘介 ⑩電層約略相同，有助於後續掺質植入的製程。 本發明提出一種半導體元件的製造方法，先提供基 底’基底包含了高壓元件區與低壓元件區，且高壓元件 區具有源極/汲極預定區、接點預定區與通道預定區。於 ί底土2▲層第一介電層。然後，移除低壓元件區之 第门龟層门日守，一併移除源極/没極預定區、接點預 疋區之第—介電層。接著’至少於低壓元件區上形成-層第二介電層，其中第二介電層的厚度小於第-介電層 I的厚度。繼而，⑨通道預定區與低壓元件區上分別形成 ►祕，而後，於源極极極預定區之基底中形成源^= m—實施例，，上述之半導體元件的製造 接點麵之㈣括繼__定區與 方本在ί”之一實施例中，上述之半導體元件的製造 ]介電層的形成方法包括熱氧化法。 方本在it明之—實施例中，上述之半導體元件的製造 方法、、中私除低壓元件區之第—介電層，同時，一说 200841398 移除源極/没極予f $ ρ . 例如是先於第―、介電:上;：定-介電層的方法 出低壓元件區、、^ 成―層案化光阻層，裸露 電層。再移除裸及^定^與接點預定區之第—介 在本發明之二1:::"電層以及圖案化光阻層。 =植=於移除裸露出之第-介電層之前，崎- 方法在上述之半導體元件的製造 刀^回壓兀件區與低壓元件區。 方法，實施例中’上述之半導體元件的製造 其中^壓元件區包括_N型元件區與_p = 方法在::明之—實施例中，上述之半導體元件的夢造 型兀件區、？型元件區與健元件區。 刀 方法在之—I施财，上叙半導體元件的f造 元件區構綱場_，分隔^型 括分F、7i祝/、 低壓兀件區，且這些場氧化層更包 二二沒極預定區、接點預定區與通道預定區。 方法之—實施例中，上述之半導體科的f造 在ίΓ介電層的形成方法包括熱氧化法 方法ίΓ狀中，上述之半導體元件的製造 方法，其中，閘極的材質包括摻雜多晶矽。’狄 本發明提出-種半導體元件，包括了基底、高壓電 8 200841398 日日體二屢井區、井區接點摻雜區、低壓電晶體與介電 具：高塵元件區與低壓元件區。高壓電晶體設 置、同LTD件區之基底上，高㈣晶體包括由下而上堆 疊設置的—高壓間介電層與-閘極，以及設置於閘極兩 ，之-源極从麵。絲絲設置於高壓元件區之基底 。井區接點摻麵則設置於高壓井區之基底中。低麼 電晶體設置魏壓元件區之基底上，健電晶體包括由 下而上堆豐設置的低_介電層與閘極。介電層設置於 =/及極區與井區接點摻魏之基底上，低 二t於高墨閉介電層的厚度，且介電層與低壓閘介^層 的厚度約略相等。 在本發明之-實_巾，上述之铸體元件，其中 "包層與健閑介電層是在目—個㈣巾所形成的。 在本發明之一實施例中，上述之半導體元件，其 "電層與低壓閘介電層的形成方法包括熱氧化法。〃 在本發明之一實施例中，上述之半導體元件，其中 中设置有多個隔離結構，分隔高壓元件區與低墨元 在本發明之—實施例巾，上述之半導體元件，高壓 凡件區包括一Ν型元件區與一Ρ型元件區。 、古在本發明之一實施例中，上述之半導體元件，其中， =些隔離結構為多個淺溝渠隔離結構，分隔ν型元件 區、ρ型元件區與低壓元件區。 土 _在本發明之一實施例中，上述之半導體元件，其中， 廷些隔離結構為多個場氧化層’分隔Ν型元件區/、、ρ型 9 200841398 元件區與低壓元件 極、源，麵財區接二化層更包括分隔閑 所需之i 體其製造方法，可以減少製程 分區域之介電層，而無 件區上之部分介電層。再仙另—道光罩，除去高屢元 明之上述和其他目的、特徵和優點能更明顯易 丁寺寸牛較佳實施例，並配合所附圖式，作詳細說明如 下。 【實施方式】 圖1A至圖id為本發明_實施例之一種半元 的製造方法。 請參照圖1A，此製造方法例如是先提供基底1〇〇， ^底100包含有南壓元件區1〇2與低壓元件區1〇4，且高 壓元件區102具有源極/汲極預定區1〇2a、接點預定區 1〇沘與通道預定區102c。基底100例如是矽基底，高壓 元件區102之基底1〇〇中例如是已形成有高壓p井n2a 與咼壓N井112b，以作為後續N型電晶體與p型電晶體 的井區。兩壓P井112a的摻質例如是硼或二氟^化等ρ 型摻質。高壓N井112b的摻質例如是砷離子或磷離子等 N型摻質。低壓元件區104之基底100中例如是同樣形 成有低壓P井114a與低壓N井114b。 在一實施例中，基底100中還形成有多個隔離結構 120 ’分隔高壓元件區1〇2與低壓元件區1〇4，隔離結構 200841398 ⑽也用來分隔高壓元件區1()2中之高壓p井收與高 ^井mb。隔離結構no例如是淺溝渠隔離結構或是 葱氧化層，其材質為絕緣材質，其例如是氧化石夕。至於 其形成方法為熟悉本領域者所週知，於此不多贅述。、 在本實施例中，隔離結構120例如是場氧化層，其 不僅用來隔離相鄰的電晶體，更可以將高壓元件^ 1〇2 的源極/汲極預定區购、接點預定區㈣與通道預定 區1 〇2c隔離開來。 、 另外，由於高壓元件區102上之電晶體需要承受較 大的電，，為了避免因高壓所產生的漏電或不正常導 通’於鬲壓P井112a之源極/汲極預定區1〇2a中，還會 =成N型漸進(grade)區116a、N型漂移(钿均區n6b，^ ，壓P井112a之通道預定區102c中形成N型通道摻雜 區n6c。另外，於鬲壓^^井112b之源極/汲極預定區l〇2a 中，則形成P型漸進(grade)區118a、p型漂移(drift)g 118b’以及於高壓时mb之通道預定區隐中形 型通道摻雜區118c。 請繼續參照圖1A，於基底100上形成一層介電層 ^30。介電層130的材質例如是氧化石夕，其形成方法例如 是熱氧化法或化學氣相沈積法。 然後，請參照圖1B，移除低壓元件區1〇4之介電層 130同日守，一併移除源極/沒極預定區102a、接點預定 區^之介電層130，以於通道預定區1〇乂之基底 上疋義出一層高壓閘介電層135。移除這些區域之介電層 13〇的方法例如是先於基底100上形成一層圖案化罩幕層 200841398 (未繪示）’裸露出低壓开株 盥接點苑^ · 件區0源極/汲極預定區102a % ’然後利用濕式磁彳法或乾式_法 阻移除圖案化光阻層。 兄祀、云九 繼t請繼續參照圖1B，至少於低壓^件區綱上 Π'"電層_，這層介電層14〇a就是作為低壓元 件之低壓閘介電層之用，介雷 一 Π0的厚度。在—&斜丨1 140a的厚度小於介電層 在貝轭例中，介電層140a的厚度例如是 用=丨電壓約3伏特之低壓元件來說，較常 用，度例如“5埃。介電層隱的材質例如是氧化 幵/成方法例如疋熱氧化法。由於源極級極預定區 搬a、、接關定區咖之介電層⑽在上—步驟已經 除击裸露出這些區域之基底！〇〇，因此，在熱氧化法的過 耘中，源極/汲極預定區1〇2a與接點預定區1〇沘之基底 100上也同時會形成—層介電層14〇b。 之後’請參照圖lc，於通道預定區102c與低壓元件 區104之基底100上分別形成閘極151與閑極⑹。間極 15卜161的材質例如是摻雜多晶石夕’其形成方法例如是 先形成-層共形的摻雜多砂層（树示），然後再進行微 影侧製程⑽成之。其巾，雜多晶⑦層例如是利用 化學氣相沈積法形成一層未摻雜多晶矽層後，進行離子 植入步驟以形成之，當然也可以採用臨場植人摻質的方 式以化學氣相沈積法形成。 在形成閘極151、161之後，還可以在閘極151、161 侧壁形成間隙壁153、163，間隙壁153、163的材質例如 12 200841398 疋氧化矽之類的介電材料，其形成方法例如是先在基底 100上形成一層間.隙壁材料層（未繪示），然後進行等向性 蝕刻，移除部分間隙壁材料層，以形成閘極侧壁之間隙 壁153、163。為了增加導電性，閘極151、161上還可以 形成金屬矽化物(未繪示），如石夕化鎢。 接下去，請參照圖1D，進行摻質植入製程，以於源 極/汲極區預定區！02a之基底1〇〇中形成源極/汲極區155 φ 與井區接點摻雜區I57。其中，源極/汲極區155的位置 例如疋與先满之漸進區（〗1、11 ga)至少有部分重疊。芦 壓元件區102之基底100上例如是形成有不同導電型的 電晶體，在南壓P井112a上會形成N型電晶體，在高壓 N井112b上會形成卩型電晶體。 在一實施例中，例如是先進行一道p型離子植入製 程，於高壓N井112b中形成p型的源極/汲極區155，於 鬲壓P井112a中形成P型的井區接點摻雜區157。當然， 低壓N井114b中也可以一併形成P型的源極/汲極區165。 之後進行一道N型離子植入製程，於高壓p井 中形成N型的源極/汲極區155,於高壓N井112b中形成 N型的井區接點摻雜區157。當然，低壓p井u4a中也 可以一併形成N型的源極/汲極區ι65。至於後續形成接 觸窗與井區接點(pick-up)的步驟，為熟知本技藝者所周 知，於此不贅述。 因為原本形成於源極/；；及極預定區與接點預定 區102b上的介電層130已經在移除低壓元件區1〇4之介 電層130的同時被移除了 .，因此，在進行上述離子植入 13 200841398 製程之μ，不必再使用另一道光罩製程以打開這些區 域。所形成的摻雜區濃度與輪廓也可以受到良好的控 制。換&之，本實施例之半導體元件的製造方法可以節 省一返光罩而縮短製造流程，並且降低製造成本，此外， 還有助於後續摻質植入製程的控制。 以下說明本發明一實施例之一種半導體元件。 請參照圖1D，此半導體元件包括基底1〇〇、高壓井 區' 南壓電晶體15G、井區接點摻雜區157、低壓電晶體 160與介電層140b。 基底具有高壓元件區102與低壓元件區1〇4。高 壓井區設置於高壓元件區102之基底1〇〇中。在一實施 例，高壓井區例如是有高壓？井112a與高壓1^井112b， 設置於高壓元件區102上，以配合不同導電型的高壓電 晶體150。 面壓電晶體150包括由下而上堆疊設置的高壓閘介 龟層135與閘極151 ’以及設置於閘極151兩侧之高壓井 區中之源極/汲極區155。高壓閘介電層135的材質例如 疋氣化發，其厚度例如是大於500埃，例如介於7〇〇〜900 埃’視元件的需求而定。閘極151的材質例如是摻雜多 晶石夕、金屬或金屬石夕化物等材質。閘極151兩侧還可以 設置有間隙壁153,間隙壁153的材質例如是氧化石夕之， 的介電材料。 〜 源極/汲極區155例如是N型摻雜區或p型摻雜^ 咼壓P井H2a之中的源極/汲極區155為N型摻雜^ 其例如是含有濃度為ΙχΙΟ15/立方公分的砷離子或鐵離’ 14 200841398 的#質，設置於高壓P井ll2a上之高壓電晶體15〇為N 型之電晶體。高壓N井112b之中的源極/汲極區155為p 型掺雜區，其例如是含有濃度| lxl〇15/立方公分的爛離 子，a又置於网壓:Νί井112b上之高壓電晶體15〇為p型之 電晶體。 高壓井區(高壓P井112a與高壓^井112b)之中，還 «又置有井區接點格雜區157，依照不同導電型井區，而為 修 P型或N型的井區接點摻雜區157。 低壓元件區104之基底1〇〇中例如是設置有低壓井 區(低壓P井114a與低壓N井114b)。低壓電晶體16〇設 置低壓井區之基底1GG _L。低壓電晶體16G包含有由下 而上堆疊設置的低壓閘介電層140a與閘極161，以及閘 極163兩側之低壓井區中的源極/汲極區165。低壓閘介 電層140a的厚度小於高壓閘介電層135的厚度，其例如 是40〜1〇〇埃之間，例如是65埃。 介電層140b設置於高壓元件區1〇2之源極/汲極區 _ 155與井區接點摻雜區157之基底1〇〇。介電層14此與 低壓介電層140a的厚度約略相等。在一實施例中，介電 層140b例如是與低壓閘介電層14〇&在同一步驟中所^ 成的。 高壓元件區102與低壓元件區1〇4之間設置有隔離 結構120。隔離結構120例如是場氧化層或是淺溝渠隔離 結構，其材質例如是氧化矽。隔離結構12〇還可以設置 =高壓元件區102之基底1〇〇中，隔離高壓卩井n2a與 高壓N井i12b。在一實施例中，高壓元件區1〇2之源極/ 200841398 汲極區155、閘極151、井區接點摻雜區157之間也可以 設置有場氧化層之隔離:結構12〇。 θ綜上所述，上述實施例中，利用同一道光罩，將低 壓兀件區104與高壓元件區1〇2之源極/汲極預定區 102a、j妾點預定區1〇2b上之介電層13〇 一併移除。因此， 在後續形麵（祕/祕區1$5、賴接轉雜區157) 的步驟前，無須再以另一道光罩，將高壓元件區102之 _ 源極/汲極預定區l〇2a、接點預定區1〇2b上之介電層13〇 除去，而可以直接進行摻質植入的步驟。如此一來，不 仁可以卜低製造成本、縮短製造流程，對於後續的摻質 輪廓與濃度也可以獲得更好的掌握。 ，然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何所屬技術領域中具有通常知識者， 在不脫離本备明之精神和範圍内，當可作些許之更動與 捫飾口此本發明之保護範圍當視後附之申請專利範圍 所界定者為準。 _ 【®賴單說明】 圖认至® 1D是—本發明一實施例之—種半導體元 的製造流程剖面圖。 【主要元件符號說明】 100 ··基底 102 •南壓元件區 104 :低壓元件區 102a ·源極/；;及極預定區 102b :接點預定區 16 200841398 102c :通道預定區 112a :高壓P井 112b :高壓N井 114a :低壓P井 114b :低壓N井 116a : N型漸進區 116b : N型漂移區 116c ·· N型通道摻雜區 ® 118a : P型漸進區 118b ·· P型漂移區 118c ·· P型通道摻雜區 120 :隔離結構 130、140b :介電層 135 :高壓閘介電層 140a :介電層（低壓閘介電層） 150 :高壓電晶體 Φ 151、161 :閘極 153、163 :間隙壁 155、165 ··源極/汲極區 157 :井區接點摻雜區 160 :低壓電晶體 17BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an integrated circuit structure and a method of fabricating the same, and more particularly to a semiconductor device and a method of fabricating the same. [Prior Art] With the rapid development of the field of integrated circuits, high efficiency, high integration, low cost, light weight and shortness have become the Φ targets pursued in the design and manufacture of electronic products. For the current semiconductor industry, in order to meet the above objectives, it is often necessary to manufacture a plurality of functional components on the same wafer. The high voltage component and the low voltage component are integrated on the same wafer, for example, a system on chip (SOC) is a method that can meet the above requirements. However, in order to be able to withstand higher breakdown voltages, the thickness of the gate oxide layer in the high voltage component tends to be much thicker than the thickness of the gate oxide layer in the low voltage component. In this way, there will be various difficulties in the integration process of high-voltage components and low-voltage components. In order to meet the different requirements of the thickness of the gate oxide layer, it is common practice to form a whole layer of high-voltage gate oxide layer with a thickness of more than 300 angstroms. Then, the high voltage closed 'oxide layer of the low voltage element region portion is removed by means of photolithography etching. Thereafter, a low-voltage gate oxide layer of the low-voltage element region is formed. Moreover, in the high-voltage gate oxide layer, the region of the high-voltage element region is also scheduled to be implanted into the ion implantation region, such as the source/pole region, the well region doping region, etc., so that the ion implantation is facilitated. The concentration, depth and the corridor of the ship's need to be further--"the side of the _, the impurity of the Wei domain on the gate oxide layer. This method requires a fresh mask, not only the county = manufacturing process, increasing the complexity of the process, but also increasing the manufacturing cost.衣衣6 200841398 SUMMARY OF THE INVENTION In view of the above, the present invention provides a semiconductor device manufacturing process using the same process to remove the dielectric layer on the low voltage device region while removing the high voltage device region. A dielectric layer on the source/noodle region and the well region doped region is predetermined to be formed. And the present invention proposes a semiconductor element in which a dielectric layer disposed on a substrate on which a predetermined region is formed is approximately the same as a gate dielectric layer in a low voltage device region, which facilitates subsequent Process for implanting dopants. The present invention provides a method of fabricating a semiconductor device in which a substrate is provided to include a high voltage device region and a low voltage device region, and the high voltage device region has a source/drain predetermined region, a contact predetermined region, and a channel predetermined region. The first dielectric layer of the 2 ▲ layer in the subsoil. Then, the first tortoise gate of the low-voltage component area is removed, and the source/dipole predetermined area and the first dielectric layer of the contact pre-defect area are removed. Next, a second dielectric layer is formed on at least the low voltage device region, wherein the thickness of the second dielectric layer is less than the thickness of the first dielectric layer 1. Then, a predetermined area is formed on the 9-channel predetermined region and the low-voltage device region, and then a source is formed in the substrate of the source pole extreme predetermined region, and the manufacturing contact surface of the semiconductor device is (4) In one embodiment of the invention, the method for forming a dielectric layer described above includes a thermal oxidation method. In the embodiment of the present invention, the semiconductor device described above Manufacturing method, in the middle of the low-voltage component area - the dielectric layer, at the same time, one said 200841398 remove the source / no pole to f $ ρ. For example, before the first -, dielectric: upper;: Ding - Jie The method of the electric layer is to output the low-voltage component region, the layer-forming photoresist layer, and the bare electrical layer. Then remove the bare and the predetermined portion of the contact and the contact region - in the second aspect of the present invention: 1::" The electrical layer and the patterned photoresist layer. = 植= Before removing the exposed first-dielectric layer, the S-method is used in the manufacturing of the above-mentioned semiconductor device to return the component region and the low-voltage device region. In the embodiment, the manufacturing of the above-mentioned semiconductor device includes the _N-type device region and the _p = square The method is as follows: in the embodiment, the above-mentioned semiconductor component is composed of a dream-shaped component, a component-shaped component, and a healthy component. The knife method is in the case of I-Fin, and the semiconductor component of the semiconductor component is described. _, the separation ^ type bracket F, 7i wish /, low-pressure component area, and these field oxide layer is more than two or two no-predetermined area, contact predetermined area and channel predetermined area. Method - in the embodiment, the above The semiconductor device is formed by a method of forming a semiconductor device, wherein the material of the gate includes a doped polysilicon. Including the basement, high-voltage electricity 8 200841398 Japanese-Japanese body two-well well area, well-site contact doping area, low-voltage transistor and dielectric: high-dust component area and low-voltage component area. High-voltage transistor setting, On the base of the LTD component area, the high (four) crystal includes a high-voltage dielectric layer and a gate set from bottom to top, and a gate-side and a source-side surface. The filament is disposed on the high-voltage component. The base of the zone. In the base of the high-voltage well region, the low-voltage transistor is disposed on the substrate of the Wei-voltage component region, and the health-electric crystal includes a low-dielectric layer and a gate electrode arranged from the bottom to the top. The dielectric layer is disposed at the =/ and the pole. The thickness of the dielectric layer is lower than the thickness of the high-voltage dielectric layer, and the thickness of the dielectric layer and the low-voltage gate dielectric layer are approximately equal. The casting element, wherein the "cladding and the hard dielectric layer are formed in a (four) towel. In one embodiment of the invention, the semiconductor component, "electric layer and low voltage thyristor The method of forming the electric layer includes a thermal oxidation method. In one embodiment of the invention, the semiconductor element described above, wherein a plurality of isolation structures are disposed, the high voltage element region is separated from the low ink element in the present invention. In the above semiconductor component, the high voltage component region includes a germanium type element region and a germanium type element region. In one embodiment of the invention, the semiconductor device described above, wherein the plurality of isolation structures are a plurality of shallow trench isolation structures separating the ν-type element region, the p-type device region and the low-voltage device region. In one embodiment of the invention, the above semiconductor device, wherein the isolation structure is a plurality of field oxide layers 'separating the 元件-type device region /, ρ-type 9 200841398 component region and the low-voltage component pole, source, The surface layer of the surface area includes the manufacturing method of the i body required for separation, and the dielectric layer of the process sub-area can be reduced, and part of the dielectric layer on the un-partition area. In addition, the above-mentioned and other objects, features and advantages of Gao Feiyuan can be more obvious, and the preferred embodiment of the Dingsi inch cattle is described in detail with the accompanying drawings. [Embodiment] Figs. 1A to 1D are diagrams showing a method of manufacturing a half element according to an embodiment of the present invention. Referring to FIG. 1A, the manufacturing method is, for example, first providing a substrate 1 , the bottom 100 includes a south voltage device region 1〇2 and a low voltage device region 1〇4, and the high voltage device region 102 has a source/drain region. 1〇2a, the contact predetermined area 1〇沘 and the channel predetermined area 102c. The substrate 100 is, for example, a germanium substrate, and the substrate 1 of the high voltage element region 102 is, for example, a high-pressure p-well n2a and a compacted N-well 112b formed as a well region of a subsequent N-type transistor and a p-type transistor. The dopant of the two-pressure P well 112a is, for example, a p-type dopant such as boron or difluorochemical. The dopant of the high pressure N well 112b is, for example, an N-type dopant such as arsenic ion or phosphorus ion. The base 100 of the low voltage component region 104 is, for example, likewise formed with a low pressure P well 114a and a low pressure N well 114b. In an embodiment, the substrate 100 is further formed with a plurality of isolation structures 120' separating the high voltage element region 1〇2 and the low voltage device region 1〇4, and the isolation structure 200841398 (10) is also used to separate the high voltage device region 1()2. The high pressure p well receives the high well mb. The isolation structure no is, for example, a shallow trench isolation structure or an onion oxide layer, and the material thereof is an insulating material, which is, for example, an oxide oxide. As for the method of forming it, as is well known in the art, it will not be repeated here. In this embodiment, the isolation structure 120 is, for example, a field oxide layer, which is not only used to isolate adjacent transistors, but also can be used to purchase and contact the predetermined source/drain of the high voltage component ^1〇2. (4) It is isolated from the planned area of the passage 1 〇 2c. In addition, since the transistor on the high voltage element region 102 needs to withstand a large amount of electricity, in order to avoid leakage or abnormal conduction caused by the high voltage, the source/drain predetermined area 1〇2a of the pressure P well 112a is pressed. In the case of the N-type progressive region 116a, the N-type drift (the 钿-average region n6b, ^, the channel P-precipitated region 102c of the pressure P-well 112a forms an N-type channel doping region n6c. ^^ In the source/drain predetermined region l〇2a of the well 112b, a P-type grade region 118a, a p-type drift (118), and a channel-predetermined region in the high-pressure mb are formed. Channel doping region 118c. Referring to FIG. 1A, a dielectric layer 30 is formed on the substrate 100. The material of the dielectric layer 130 is, for example, oxidized oxide, and the forming method thereof is, for example, thermal oxidation or chemical vapor deposition. Then, referring to FIG. 1B, the dielectric layer 130 of the low-voltage device region 1〇4 is removed, and the source/defective predetermined region 102a and the dielectric layer 130 of the contact predetermined region are removed. A layer of high voltage gate dielectric layer 135 is formed on the substrate of the predetermined area of the channel. For example, a method of removing the dielectric layer 13 of these regions is performed, for example. A patterned mask layer 200841398 (not shown) is formed on the substrate 100. 'Naked low-voltage opening contact point garden ^ · Part area 0 source/bungee predetermined area 102a %' and then using wet magnetic boring method Or dry _ method to remove the patterned photoresist layer. Brothers, Yun Jiuji, please continue to refer to Figure 1B, at least on the low-voltage component area Π '" electric layer _, this layer of dielectric layer 14〇a It is used as the low-voltage gate dielectric layer of the low-voltage component, and the thickness of the dielectric layer is less than 0. The thickness of the dielectric layer 140a is smaller than that of the dielectric layer in the case of the yoke, and the thickness of the dielectric layer 140a is, for example, For a low-voltage component having a voltage of about 3 volts, it is more commonly used, for example, "5 angstroms. The material of the dielectric layer is, for example, a yttria/forming method such as a thermal oxidation method. Since the source-level electrode is moved to a predetermined region, The dielectric layer (10) of the junction area has been removed from the base of these areas! 〇〇, therefore, in the thermal oxidation process, the source/drainage predetermined area 1〇2a is connected A layer of dielectric layer 14〇b is also formed on the substrate 100 of the predetermined area. After that, please refer to FIG. A gate electrode 151 and a dummy electrode (6) are respectively formed on the substrate 100c and the substrate 100 of the low-voltage device region 104. The material of the interpole 15b 161 is, for example, doped polycrystalline stone, which is formed by, for example, forming a first-layer conformal blend. a heterogeneous sand layer (tree), and then a lithographic side process (10). The towel, heteropoly 7 layer, for example, is formed by chemical vapor deposition to form an undoped polysilicon layer, and then subjected to an ion implantation step. Forming, of course, can also be formed by chemical vapor deposition by means of on-site implantable dopants. After forming the gates 151, 161, spacers 153, 163 can also be formed on the sidewalls of the gates 151, 161, spacers The material of 153, 163, for example, 12 200841398 介 疋 的 dielectric material, for example, is formed by first forming a layer of interlayer material (not shown) on the substrate 100, and then performing isotropic etching, shifting A portion of the spacer material layer is formed to form the spacers 153, 163 of the gate sidewalls. In order to increase the conductivity, metal halides (not shown) such as Shihua tungsten may be formed on the gates 151, 161. Next, please refer to Figure 1D for the dopant implantation process to the predetermined area of the source/drain region! A source/drain region 155 φ and a well region doped region I57 are formed in the substrate 1 of 02a. The position of the source/drain region 155, for example, at least partially overlaps with the progressive region (1, 11 ga). The substrate 100 of the squeezing element region 102 is, for example, formed with a transistor of a different conductivity type, an N-type transistor is formed on the south P-well 112a, and a 卩-type transistor is formed on the high-pressure N-well 112b. In one embodiment, for example, a p-type ion implantation process is first performed, a p-type source/drain region 155 is formed in the high-pressure N well 112b, and a P-type well region is formed in the P-well 112a. Doped region 157. Of course, the P-type source/drain region 165 can also be formed together in the low-voltage N well 114b. An N-type ion implantation process is then performed to form an N-type source/drain region 155 in the high-pressure p-well and an N-type well contact-doped region 157 in the high-pressure N-well 112b. Of course, the N-type source/drain region ι65 can also be formed together in the low-voltage p-well u4a. The steps for subsequently forming the contact window and the pick-up of the well region are well known to those skilled in the art and will not be described herein. Because the dielectric layer 130 originally formed on the source/; and the extreme predetermined region and the contact predetermined region 102b has been removed while removing the dielectric layer 130 of the low voltage device region 1〇4, therefore, In the above-mentioned ion implantation 13 200841398 process μ, it is no longer necessary to use another mask process to open these areas. The concentration and profile of the doped regions formed can also be well controlled. In other words, the method of fabricating the semiconductor device of the present embodiment can save a mask and shorten the manufacturing process, and reduce the manufacturing cost, and further contribute to the control of the subsequent dopant implantation process. A semiconductor device according to an embodiment of the present invention will be described below. Referring to FIG. 1D, the semiconductor device includes a substrate, a high voltage well region, a south piezoelectric crystal 15G, a well contact doping region 157, a low voltage transistor 160, and a dielectric layer 140b. The substrate has a high voltage element region 102 and a low voltage element region 1〇4. The high-pressure well region is disposed in the substrate 1 of the high-voltage element region 102. In one embodiment, is the high pressure well zone having a high pressure, for example? The well 112a and the high voltage well 112b are disposed on the high voltage element region 102 to match the high voltage transistors 150 of different conductivity types. The surface piezoelectric crystal 150 includes a high voltage gate dielectric layer 135 and a gate electrode 151' which are stacked from bottom to top and a source/drain region 155 which is disposed in a high voltage well region on both sides of the gate electrode 151. The material of the high voltage thyristor layer 135 is, for example, a gas-filled hair, and the thickness thereof is, for example, greater than 500 angstroms, for example, between 7 〇〇 and 900 angstroms. The material of the gate 151 is, for example, a material such as doped polycrystalline stone, metal or metal cerium. A spacer 153 may be further disposed on both sides of the gate 151, and the material of the spacer 153 is, for example, a dielectric material of oxidized stone. ~ The source/drain region 155 is, for example, an N-type doped region or a p-type doped region. The source/drain region 155 of the P-well H2a is an N-type doping, which is, for example, a concentration of ΙχΙΟ15/ The cubic centimeter of arsenic ions or iron is separated from the '14 200841398', and the high-voltage transistor 15 设置 placed on the high-pressure P well ll2a is an N-type transistor. The source/drain region 155 of the high voltage N well 112b is a p-type doped region, which is, for example, a rotten ion having a concentration of | lxl 〇 15 / cubic centimeter, and a is placed on the network pressure: Νί well 112b The piezoelectric crystal 15 is a p-type transistor. In the high-pressure well area (high-pressure P-well 112a and high-pressure ^ well 112b), there is also a well-connected grid-like area 157, which is used to repair P-type or N-type wells according to different conductive well areas. Doped region 157. The base 1 of the low voltage component region 104 is, for example, provided with a low pressure well region (low pressure P well 114a and low pressure N well 114b). The low-voltage crystal 16〇 sets the substrate 1GG_L of the low-pressure well region. The low voltage piezoelectric crystal 16G includes a low voltage gate dielectric layer 140a and a gate electrode 161 which are stacked from bottom to top, and a source/drain region 165 in a low voltage well region on both sides of the gate electrode 163. The thickness of the low voltage gate dielectric layer 140a is less than the thickness of the high voltage gate dielectric layer 135, which is, for example, between 40 and 1 angstrom, for example, 65 angstroms. The dielectric layer 140b is disposed in the source/drain region _155 of the high voltage device region 1〇2 and the substrate 1〇〇 of the well contact doping region 157. The dielectric layer 14 is approximately equal in thickness to the low voltage dielectric layer 140a. In one embodiment, dielectric layer 140b is, for example, formed in the same step as low voltage gate dielectric layer 14 & An isolation structure 120 is disposed between the high voltage element region 102 and the low voltage element region 1〇4. The isolation structure 120 is, for example, a field oxide layer or a shallow trench isolation structure, and the material thereof is, for example, hafnium oxide. The isolation structure 12A can also be placed in the substrate 1 of the high voltage element region 102 to isolate the high pressure well n2a from the high pressure N well i12b. In one embodiment, the isolation of the field oxide layer may be provided between the source of the high voltage device region 1〇2/200841398, the drain region 155, the gate 151, and the well contact doping region 157: structure 12〇. In the above embodiment, in the above embodiment, the source/drainage predetermined area 102a, j of the low-voltage element region 104 and the high-voltage element region 1〇2 is used in the predetermined area 1〇2b of the high-voltage element region 1〇2 by the same mask. The electrical layer 13 is removed together. Therefore, before the step of the subsequent shape (secret/secret area 1$5, splicing the miscellaneous area 157), it is no longer necessary to use another reticle to set the source/drain predetermined area l〇2a of the high voltage element region 102. The dielectric layer 13〇 on the contact predetermined area 1〇2b is removed, and the step of dopant implantation can be directly performed. In this way, it is possible to reduce the manufacturing cost and shorten the manufacturing process, and to obtain a better grasp of the subsequent dopant profile and concentration. The present invention has been disclosed in the above preferred embodiments. However, it is not intended to limit the invention, and any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1D is a cross-sectional view showing a manufacturing process of a semiconductor element according to an embodiment of the present invention. [Description of main component symbols] 100··Substrate 102 • South voltage element region 104: Low voltage element region 102a • Source/;; and pole predetermined region 102b: Contact predetermined region 16 200841398 102c: Channel predetermined region 112a: High voltage P well 112b: high pressure N well 114a: low pressure P well 114b: low pressure N well 116a: N type progressive zone 116b: N type drift zone 116c · · N type channel doped zone ® 118a : P type progressive zone 118b · · P type drift zone 118c · P-type channel doping region 120: isolation structure 130, 140b: dielectric layer 135: high voltage gate dielectric layer 140a: dielectric layer (low-voltage gate dielectric layer) 150: high voltage transistor Φ 151, 161: Gate 153, 163: spacer 155, 165 · source/drain region 157: well junction doping region 160: low voltage transistor 17