TW200839906A - Method of fabricating back-illuminated imaging sensors using a bump bonding technique - Google Patents

Abstract

A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The method for manufacturing the imaging device includes the steps of providing a substrate comprising an insulator layer, and an epitaxial layer substantially overlying the insulator layer; fabricating at least one imaging component at least partially overlying and extending into the epitaxial layer; forming a plurality of bond pads substantially overlying the epitaxial layer; fabricating a dielectric layer substantially overlying the epitaxial layer and the at least one imaging component; providing a handle wafer; forming a plurality of conductive trenches in the handle wafer; forming a plurality of conductive bumps on a first surface of the handle wafer substantially underlying the conductive trenches; and bonding the plurality of conductive bumps to the plurality of bond pads.

Description

200839906 IX. Description of the Invention: [Technical Field] The field of the invention is a semiconductor device fabrication and device structure. More specifically, the present invention relates to a backlighting image array device and a method of constructing such a device. [Prior Art] CMOS or CCD image sensors are important in a variety of sensing and imaging applications in a wide range of applications including shoulder, commercial, industrial, and space electronics. Imagers based on charge coupled devices (CCDs) are currently the most widely used. The CCD is used for front or back lighting configurations. Front-illuminated ccd imagers are cost-effective to manufacture compared to backlight CCD imagers, as previous lighting devices dominated the consumer imaging market. Front side illumination, although traditionally used in standard imagers, has significant performance limitations, such as low fill factor/low sensitivity. The problem of low fill factor/low sensitivity is generally due to shadows due to the presence of opaque metal bus bars and absorption by the array circuit structure formed in the pixel region on the front surface. Therefore, in a large image (high resolution) front illumination imager, the area of action of the pixel is typically small (small fill factor). • Thinned back-illuminated semiconductor imaging devices are more advantageous than front-illuminated imagers because of their high fill factor, better charge generation, and better overall efficiency of collection, and are suitable for small pixel arrays. One of the properties of a back-illuminated semiconductor imaging device is to quickly drive the charge carriers generated by light or other emitters incident on the back side to the front side to avoid any horizontal drift that would otherwise smear. It is also desirable to have the resulting carrier before it reaches the front side. 123052.doc 200839906 Because such recombination reduces the overall efficiency of the device, such a need can be provided by providing a thin semiconductor layer in this layer.

to realise. The field should extend to the back surface so that the resulting ::: (used electronics or holes) can be quickly driven to the front side. This requires additional processing on the side of the month, which increases the complexity of the process. Once the thin-film semiconductor wafer is packaged and thinned, a "flash gate" will be added after the thinning: This is required for the backside flash gate for critical thickness control. Another technique includes A thin dopant layer is grown on the crystal by using molecular beam worms (MBE). Another conventional method for providing a desired electric field establishes a doping gradient inside the thinned semiconductor layer by implanting the layer on the back side and then performing appropriate heat treatment for annealing and activation. These methods may not be easily included in conventional semiconductor casting processes and require more expensive custom processing. ,

Recombination is minimized and sensitive. There are other challenges in the manufacture of a thin backlit imager: for example, a thinned backside imager can have an inherent dangling bond present on the dove back surface, which can cause the generated electrons to recombine on the back surface. Therefore, if the back side of the thinned imager is not processed to reduce the intercept, the quantum efficiency (QE) may be degraded. Wafer thinning brings yield problems, such as stresses in thinned wafers due to non-uniformity in the thickness of the cat's crystal layer. Based on these and the above reasons, the manufacturing cost under conditions for mass production of backlighting imagers is much higher than for those used in front-illumination imagers. In the co-pending U.S. Patent Application Serial No. 11/35, No. 546, Jianshi is used to manufacture a cost-effective process for manufacturing a backlit CCD/CMOS imager based on an insulator. 1230009.doc 200839906 The full text of the disclosure is based on the reference, and the manufacturing method proposed in the application of this application not only solves the above (four), but also has several better than other construction schemes for the f-lighting CCD/C erasing imager. Advantages, including: The method is fully compatible with the existing CGD/(:MQS imaging program. • The proposed method does not require any special backside processing.

• Can crystal's buried oxide layer is used as a natural stop layer for high output thinning procedures. • The thickness of the epitaxial layer grown by using this program is precisely controlled. Compared with the conventional method, this is the same day, and the combination of stopping the oxide insulating layer can produce a very uniform thickness. The method of the instrument allows for multi-level metal processing. • The device manufactured by the proposed method can be thoroughly tested prior to applying the wafer thinning/lamination step, thereby reducing the major cost in a production environment. Some imaging systems incorporate filters and microlenses into the image sensors to produce wavelength dependent signals. To date, this has mostly been done in conjunction with a front illumination imager. Even for the method suggested above: σ The manufacture of filters and microlenses for thinning moonlight imagers is a complex procedure. The alignment of the filter/microlens on the back side with the pixels on the front side is critical. The alignment of the back side and the front side is possible, but the alignment is accurate and the vocalization is small. In addition, the combination and sealing of such back-thin imagers with the wires of the filters increases the complexity of the procedure. 123052.doc 200839906 Accordingly, an apparatus and method for fabricating a backlighting imager, though not required, is incorporated into the filter, microlens, and wire bonding techniques with greater cost efficiency. SUMMARY OF THE INVENTION A method for fabricating a back-illuminated imaging device using a semiconductor-on-insulator (S0I) substrate and a resulting device for manufacturing the imaging device include the following Step: Provide Ο

(J) comprising an insulator layer and a substrate substantially covering the epitaxial layer of the insulator layer, fabricating at least one image, at least partially covering and extending into the epitaxial layer, and covering the shell a plurality of bonding layers of the stupid layer; manufacturing a dielectric layer substantially covering the epitaxial layer and the at least one imaging component; providing a processing circle, forming a plurality of conductive bumps in the processing wafer Formed on a first surface of the circle of 冓= circle substantially under the conductive trenches; and combining the plurality of conductive bumps with the plurality of bonding pads. The back-illuminated semiconductor imaging device produced by the worm layer comprises An insulator layer; a germanium/shell covering the insulator layer; at least one imaging component formed to at least partially cover the epitaxial layer and extend into the epitaxial layer; a layer: a layer formed into a substance Overlying the at least one imaging (four) and being crystalline:: providing a plurality of bonding pads substantially covering the dielectric layer; and disposing a conductive trench having a conductive trench formed therein, the conductive trenches being combined with the plurality of turns Mat At least one imaging component having at least one imaging component having at least one imaging pad covering at least one of the bonding pads of the epitaxial layer, at least one 123052.doc 200839906, the binding layer at least partially covering the An imaging area, wherein the processing wafer is formed to form a plurality of conductive trenches, the via holes etched in the handle wafer, the conductive vias are filled with a conductive material; and one of the handle wafers is disposed The surface is smoothed by filling the vias with a conductive material by means of an electroplating or sputtering technique. The conductive material may be a metal such as gold, tin or a crane. Formed to at least partially cover and extend into the layer of protrusions. The alignment key in the layer of the insect layer is formed by printing a bond on a top portion of the layer of insects; using a trench etching process; The surname is engraved in the lower worm layer under the key pattern until the last name of the Shi Xi is stopped by the lower insulator/buried oxide layer, and the hunting is performed by a bismuth oxide, carbonized nitrogen and polycrystalline hard Come - come The open imaging trenches. The imaging components may include any combination of cm〇s imaging components, charge coupled device (CCD) components, photodiodes, avalanche light diodes, or optoelectronic crystals. The optical components may include any Combination of calendering sheets and microlenses. EMBODIMENT The following specific examples are intended to serve as exemplifications and are not to be construed as limiting, and the drawings are not necessarily drawn to scale. 5 illustrates one of the procedures for fabricating a backlit imager with a slit 4 and one of the resulting structures, and is a careful example. FIG. 1 illustrates that in the art, it is sometimes referred to as a semiconductor-on-insulator (s). 〇I) base

The initial substrate 10 of the board is placed on the board. The starting SOI substrate 10 (shown in Figure 1) is a handle wafer 25 for providing support between the electrodes, an insulator layer 20 (which may be a buried oxide layer) and 123052.doc 200839906 b The seed layer 15 is composed. In this embodiment, the handle wafer μ can be used to fabricate one of the standard germanium wafers of the integrated circuit. Alternatively, the handle wafer 25 can be any substrate having sufficient rigidity to be comprised of materials that are compatible with the method steps disclosed herein. The insulator layer can comprise a stone oxide having a thickness of about 1 micron. In other embodiments, the thickness of the insulator layer 20 can range from about 1 〇 nm to about 5 〇〇〇 (10). The seed layer 15 may be composed of (4) having a thickness of from about 5 nm to about (10) nm.

U SOI substrates are commercially available and are manufactured by a variety of conventional methods. In one method, thermal yttrium oxide is grown on a tantalum wafer. Two such wafers are in contact with the oxidized surface and raised to a high temperature. In some variations, a potential difference is applied across the two wafers and the oxides. The effect of such processing is that the oxide layers on the two wafers flow into each other to form a single stone bond between the wafers. Once the bond is completed, the slabs on one side are polished and polished to the desired thickness of the seed layer 15, while the 7 on the opposite side of the oxidant forms the handle wafer 25. The oxide forms the insulator layer 20, and the other method of fabricating an SOI substrate is to start with obtaining a more standard semiconductor-on-insulator (SOI) wafer in which the seed layer 15 is formed. The thickness is in the range of about 1000 nm from about (10) (four) (four). A thermal oxide is grown on the semiconductor substrate by a conventional method. As the oxide layer grows, the semiconductor substrate is consumed by the Fujito 栌^^<> The oxide layer is then selectively etched away leaving a semiconductor substrate having a thickness of one of the desired seed layer thicknesses. An SOI substrate (referred to as Smart CutTM) manufactured by an alternative method 123052.doc -11 · 200839906 is sold by Soitec, S.A. The seed layer 15 may comprise germanium (Si), germanium (Ge), a SiGe alloy, a third to fourth semiconductor, a second to sixth semiconductor, or any other semiconductor material suitable for use in fabricating optoelectronic devices. Γ: Referring now to Figure 2, an epitaxial layer 30 is formed on the seed layer 15 by using the seed layer 15 as a template. Depending on the material of the seed layer 15, the epitaxial layer % may be coated with (9), germanium (Ge), SiGe alloy, a third to fourth semiconductor, a second to sixth semiconductor or any other semiconductor suitable for fabricating optoelectronic devices. Material: The epitaxial layer 30 may have a thickness from about "destroyed rice to about 5 〇 micron. The resistivity of the crystal layer can be controlled by controlling the crystal growth process." The seed layer 3〇 prints an alignment key on the insect layer 3〇 and engraves into the insect layer 3〇. The alignment keys 45 can be used to align the subsequent layers during the imager process and also It can be used to align the calendered sheets on the back side after the crystal solids are thinned. The alignment keys can be used to align the subsequently deposited layers with high precision in meters or less. 4 5 can also be used to ask the gentleman, open,,, ϋ a pad area to the i-line, and the back side of the device to be produced. By using the kedan 彡] to etch with a shirt, the key pattern 50 is printed on the top portion 5 5 of the epitaxy ^. It is possible to use a trench etching process to etch by using electricity 4 Engraved in the Lord, ^ ^ in the lower layer of the epitaxial layer 30 under the 5 key pattern 5 直至 until the worms are cut off due to the lower part of the lower edge of the body / buried oxide layer 20 and then stopped. An insulating material (for example, a bismuth telluride, tantalum carbide, tantalum nitride or polycrystalline spine) is used to fill the open trench 57. Referring now to Figure 4, the conventional semiconductor fabrication method is used at 123052.doc -12 - 200839906 One or more imaging components 60 are fabricated on the stray layer 30. These imaging components 60 may include any combination of charge coupled device (CCD) components, CMOS imaging components, photodiodes, avalanche light diodes, optoelectronics Crystal or other optoelectronic cleft. The imaging assembly 60 can include CCD and CMOS components fabricated in separate regions of the cat day layer 30 using conventional masking methods. Other electronic components, such as CMOS transistors, can also be included. (not shown), bipolar % carcass (not shown), capacitor (not shown) or resistor (not shown).

The CJ aligns the imaging components 6 on the worm layer 30 by using the alignment keys 45 as a guide. When several imagers are fabricated on the wormhole layer 3G, one or more dicing channels μ may be present in the first day layer. As a preliminary step in the process of hooking up a second handle wafer by bump bonding (described below), a dielectric layer 67 made of a lithium oxide or nitride may be deposited thereon. The imaging component 60 and the alignment keys=2 are not blocked on the dielectric layer 67 covering the imaging components by any imaging component 72 of any imaging component of the current system. The pattern forms a plurality of (conductive) metal bond pads 7〇. Referring now to Figures 4 and 5', there may be further processing of the back side of the first device junction (4) and the need to add a second handle wafer 75 to the side 77 to provide a further machine; It: To the 篦 驻 ^ ^ ^ ^ ^ 槭 。 。 。 。 Adding the second to the front side 77 of the device structure 73 to bump the second handle wafer 75::: The bond pad on the front side 77 can be: the second handle wafer 75 can be: Any suitable material (Example 1, ^ is made of mechanically supported any suitable metal (eg, gold, tin, crane, etc.)::). The daytime seed layer 80 can be deposited on the first side 85 of one of the first disposal wafers 75 of 123052.doc 200839906. The resulting second device structure 88 is now ready to be bonded to the first device structure. Referring now to Figure 6, a plurality of vias 90 are defined and etched into one of the second sides 95 of the second handle wafer 75. The via holes 9 are aligned with the bonding pads 7 of the first device structure 73. Referring now to Figure 7, the vias 90 are filled with a suitable conductive material by electromine or sputtering to form a filled metal trench 100. If the second handle wafer 75 is made of tantalum, then the power supply is insulated between the second handle wafer 75 and the filled metal trench. As a by-product of the electroplating or sputtering process, the excess metal 105 can protrude from the metal trenches on the second side 95 of the second handle wafer 75 and hang over the metal trenches such as ▲. Referring now to Figure 8, any of the sacrificial genus is removed and the surface of the second side 95 of the second handle wafer 75 is made smooth and flat by utilizing a chemical mechanical polishing procedure (CMp). A metal layer 110 / is deposited on the second side 95 of the second handle wafer 75 and the filled metal trench 100. Referring now to FIG. 9, a plurality of defined metal trenches 100 are defined by a lithography process and by etching away portions A of the metal layer 110 from the second surface of the second handle wafer 75. Bond pad 115. Referring now to Figure 10, a plurality of metal bumps 12 are formed on the mating pads 115 on the first side of the second handle wafer. The metal bumps 120 are made of a suitable metal such as indium. The second device structure μ is now ready to be bonded to the first device structure 73. Referring now to Figure u, the second device structure 88 is shown in combination with the bumps of the first device structure 73. After aligning the structures 73, 88 by using the bond pads as keys, the second handle wafer is a metal bump 123052.doc -14·200839906 120 and the second device structure 88 on the front side 77 The combination of the mats is combined. Bonding is effected by applying a suitable elevated pressure to the aligned structures 88, 73 and a suitable temperature. Due to the applied pressure and elevated temperature, the metal bumps 120 are fused with the bond cymbals 70 to form a strong metal joint between the lands 2 and 73. To provide mechanical support between the structures ", 73, the resulting gap 13" between the structures 88, 73 is filled with a suitable epoxy/glue to form a single imager structure 135. Referring to Figures 12 and 13 'A subsequent step of the procedure includes removing the first disposal wafer 25. The wafer 25 is no longer needed to provide mechanical stability. Partial mechanical polishing and subsequent chemical etching, mechanical Grinding or one of these methods is combined to effect removal of the wafer defect. By chemical etching, the handle wafer 25 can be selectively removed without removing the insulator layer 2 to produce the imager structure 135. One of the smooth back sides 137. The insulating layer 2 is used as an etch stop layer. The imager structure 135 (Fig. 13) is then flipped for further processing. Referring now to Figure 14, the alignment keys can be utilized 45 as a precision guide, the optical assembly 140 is coupled to the back side 137 of the imager structure 135. The or plurality of optical components can include filters and microlenses to produce wavelength dependent signals. Figure 15, if There are cutting channels 65 for fabricating a plurality of imagers, which may be used as guides for cutting the imaging structure 135 into a plurality of separate imaging structures 15A. The bonding wires 14 are then bonded. 5 is combined with the combination 塾11 5. The bump-bonding manufacturing technique for the illuminating imager of the present invention provides a significant advantage of one of the front-illumination imagers manufactured by other techniques. Figure 16 A top plan view of a front illumination imager 155 is shown. Since the front illumination imager 155 needs to have an unobstructed imaging area 175 to allow incident light to fall on imaging pixels (not shown) within the imaging area 175, The bond pads 160 are distributed around the outer periphery 165 of the top of the front illumination imager ι 55. The size of the front illumination imager 1 55 needs to be reduced, which requires a reduction in the pixel size in the imaging area 175. Since the size of the bond pads 160 cannot be reduced, the ratio of the area occupied by the bond pads 与6〇 to the image area Ο 170 is increased. Figure 17A shows a bump knot in accordance with the present invention. One of the back illumination imagers 180 is constructed in a top plan view, and FIG. 17B is a side view. A plurality of bond pads 185 can be distributed over the imaging area 19A and aligned with the vias 195 of the support wafer 200. Since light enters only through the back side 205 of the imager ι8〇, the bond pads 185 and vias I% can be placed in the region 210 of the front side 2 15 of the imager 180 without affecting collection. In the case of light like I, prime (not shown). In this way, the overall size of the imager 180 can be reduced. The cut wafer can be packaged by using conventional ball grid array or bump bonding techniques. . It is understood that the exemplary embodiments are merely illustrative of the invention, and those skilled in the art can devise many variations of the specific embodiments described above without departing from the invention. Therefore, all such variations are intended to be included within the scope of the appended claims and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of an on-insulator (SOI) substrate used in a shoe-skin order for an illumination imaging device of 123052.doc 16 - 200839906 according to an embodiment of the present invention; 2 shows the step of forming an epitaxial layer on the seed layer of the SOI substrate of FIG. 1; 0, T according to the embodiment of the present invention in the step of the stupid alignment key; FIG. 4 shows Fabricating - or a plurality of imaging components on the epitaxial layer and printing the position between the alignment keys shown in FIG. 3 in the stray layer and (iv) bonding pad regions;

Figure 5 shows a step of preparing a second disposal wafer to be attached to one of the device sides of the imaging assembly shown in Figure 4; Figure 6 shows the combination of Figure 2 shown in Figure 2 The step of etching the via holes at the position where the pad regions are aligned; FIG. 7 shows the step of filling the via holes shown in FIG. 6 with a conductive material by electroplating or sputtering to form a filled metal trench; FIG. 8 shows the second The step of treating the surface of the second side of the wafer to be smooth and depositing metal on the second side; FIG. 9 shows the definition of a plurality of bond pads on the filled metal trench on the second surface of the second handle wafer Step 10; FIG. 10 illustrates a step of opening a plurality of metal bumps on the bonding pad on the first side of the second processing wafer; FIG. 11 illustrates the second processing wafer structure and the S〇 The step of combining the I device wafer structure bumps to produce a composite imager structure; FIG. 12 shows the steps of removing the first processing wafer belonging to the initial SOI wafer structure shown in FIG. 1; 123052.doc 17 200839906 FIG. Displaying the imager structure that flipped the composite for further processing Figure 14 shows the step of bonding the optical component to the back side of the resultant imager structure by using the alignment keys as guides; Figure 15 shows the fabrication of metal contacts and the bonding wires attached to the composite Figure 16 is a top plan view of a front illumination imager with a bond pad disposed adjacent its outer periphery to provide an unobstructed imaging area; A is a top plan view of one of the backlighting imagers constructed in accordance with the present invention, wherein the bonding cassette can be placed in the pixel area on the front side of the imager, thereby enabling a reduction in overall size; and FIG. 17B is FIG. A side view of one of the illustrated backlighting imagers showing the location of the vias in the front side imaging region. [Main component symbol description] 10 initial substrate / starting SOI substrate 15 seed layer 20 insulator layer / insulator / buried oxide layer 25 disposal wafer 30 stray layer 45 alignment key 50 key pattern 55 epitaxial layer 3 0 Top portion 57 Ditch 60 Imaging assembly 123052.doc -18. 200839906 65 Cutting channel 67 Dielectric layer 70 (conductive) Metal bond pad 72 Imaging area 73 First device structure 74 Back side 75 of first device structure 73 Circle 77 First Device Structure 73 Front Side 80 Seed Layer 85 Second Treatment Wafer 75 First 88 Second Device Structure 90 Via 95 Second Treatment Wafer 75 Second 100 Filled Metal Ditch 105 Excess Metal 110 metal layer 115 bonded 塾 120 metal bump 130 gap 135 imager structure 137 back side 140 of imager structure 135 optical component 145 bonded wire 150 separated imaging structure 123052.doc -19 - 200839906 155 160 170 175 180 185 190 195 Ο 200 205 210 215 front illumination imager combined with pad front illumination imager 155 top / imaging area imaging area back illumination imager combined pad Image area Via hole Support wafer Imager 180 back side Front side 2 1 5 area Imager 180 front side u 123052.doc -20-

Claims (1)

200839906 X. Patent Application Range: L A method for manufacturing a backlight semiconductor imaging device, 1 the following steps: 匕έ providing a substrate comprising: an insulator layer; and a stupid layer substantially covering the An insulator layer; at least partially covering and extending into the epitaxial layer; ν an imaging group 〇〇 forming a plurality of bonding pads substantially covering the epitaxial layer; manufacturing covering the epitaxial layer and the at least one imaging component The dielectric layer provides a handle wafer; 曰 forming a plurality of conductive trenches in the handle wafer; and forming a plurality of conductive bumps on the -first surface substantially on the handle wafer; The galvanic wood combines the plurality of conductive bumps with the plurality of bonding pads. The method of claim 1, wherein at least the imaging component has an imaging region, wherein substantially the plurality of the epitaxial layers are covered At least one bond pad of the bond pad also at least partially covers the imaged area. The method of claim 2, further comprising forming a plurality of substantially covering the stretch layer The method of aligning the keys. The method of claim 3, wherein the step of forming a plurality of alignment keys substantially covering the epitaxial layer further comprises the step of: printing the key pattern on top of one of the stray layers Partially; by using a trench remnant procedure to engrave under the key pattern 123052 200839906 stupid layer until the etched 矽 due to the lower insulator layer; and filling with an electrically insulating material 5. The method of claim 4, wherein the electrically insulating material is one of tantalum oxide, tantalum carbide, tantalum nitride, and polycrystalline germanium. 6. The method of claim 1, wherein the wafer is processed The step of forming a plurality of guide trenches further includes the steps of: etching via holes in the handle wafer; filling the via holes with a conductive material; Ο Let the first surface of the 4 handle wafer be smoothed. 7. The method of claim 6, wherein the via holes are filled with a conductive material by using one of electroplating and sputtering techniques. The method of claim 1, further comprising the steps of: forming a plurality of bond pads substantially covering a second surface of the handle wafer; and attaching the plurality of bond wires to substantially cover the handle wafer The plurality of bonding pads of the second surface. 9::: The method of claim 8, wherein the step of forming a plurality of bonding defects substantially covering the surface of the handle wafer further comprises the step of depositing a conductive material on the handle wafer The second surface is loaded; and the conductive material is patterned and engraved to dispense the plurality of bonding pads in the filled metal trench. 10. The method of claim 9, wherein the electrical material is made of a metal. 123052 200839906 11 The method of claim 10, wherein the metal is one of gold, tin and tungsten. The method of claim 3, further comprising the step of fabricating at least one optical component substantially covering the epitaxial layer and closest to the insulating layer by using the plurality of alignment keys as a guide. 13. The method of claim 12, wherein the step of fabricating the at least one optical component comprises the step of fabricating the filter and the microlens in any combination. The method of claim 12, further comprising the step of forming a substantially covering dielectric layer to the imaging component and the doped layer prior to the step of forming a plurality of bonding pads substantially covering the imaging region . 5. The method of claim 14, further comprising forming a plurality of electrically conductive bond pads substantially prior to the step of combining the plurality of metal bumps with the plurality of bond pads at least partially covering the imaged region The steps of substantially filling the first surface of the wafer under the conductive trench. 16. The method of fabricating one or more imaging components in the method of claiming, comprising: assembling the imaging assembly, the charge coupled device (CCD) component, the optical diode, the avalanche photodiode, or the optoelectronic device in any combination. Step K of the crystal, wherein the method of fabricating at least one imaging component in the worm layer further comprises the step of: forming a second imaging group at least partially covering and extending into the worm layer: The V imaging assembly and the second imaging assembly are formed substantially between the alignment keys. 18' The method of claim 1, wherein the disposal wafer is made of tantalum, aluminum nitride, and one of 123052 200839906. 19. The method of claim (1), wherein the step of combining the plurality of metal bumps with the plurality of bond pads at least partially covering the imaged region further comprises applying a predetermined pressure and temperature to the substrate and the handle wafer. Step 20. Control the method as in claim 1. Wherein the resistivity of the I layer is affected by the stray crystal profile 21. A back-illuminated semiconductor imaging device comprising: an insulator layer; an epitaxial layer substantially covering the insulator layer; at least an imaging component formed to at least partially cover and extend into the 0-worm layer a dielectric layer formed to substantially cover the at least one imaging component and the doped layer; a plurality of bonding pads substantially covering the dielectric layer; and a handle wafer having a conductive layer formed therein Ditches, the conductive trenches are combined with the plurality of bonding pads. 22. The backlight semiconductor imaging device of claim 21, wherein the at least one imaging component has an imaging region, and wherein at least a plurality of bonding pads substantially covering the dummy layer also at least partially cover the Imaging area. 23. The backlighting semiconductor imaging device of claim 22, further comprising a plurality of alignment keys formed to at least partially cover and extend into the layer. 24. The backlight illumination semiconductor imaging device of claim 23, wherein the material alignment key is filled with - xixi oxidizing 123052 200839906, obstructing, nitriding 7 and more. 25. The backlight illumination semiconductor imaging device of claim 23, further comprising substantially a plurality of bonded germanium under the conductive trenches and substantially covering the conductive trenches. 26. The backlit semiconductor imaging device of claim 21, further comprising a viscous material filling a gap between the handle wafer and the dielectric layer. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 28. As requested in item 27, the backlight is Fengmo Pingshi you#. A monthly 3,000 V body imaging device in which the metal is one of gold, tin and tungsten. 29. The backlighting semiconductor imaging device of claim 21, further comprising at least one optical component fabricated to substantially cover the silicon dioxide layer and closest to the insulating layer. 30. The backlight illumination semiconductor imaging device of claim 29, wherein the at least one optical component comprises any combination of light and microlenses. Kj 31. The backlight illumination semiconductor imaging device of claim 3, further comprising a plurality of metal contacts combined with a conductive trench such as a 亥 之 。 3 3 3 3 3 3 3 21 21 21 21 坐 坐 坐 坐 坐 坐 坐a ..., a conductive conductor imaging device, wherein the processed wafer is made of one of tantalum, aluminum nitride, and ceramic. The epitaxial layer package 33. The illumination semiconductor imaging device of claim 21 has a stone The insulator layer comprises an oxide. The one or more 34. The backlight illumination semiconductor imaging device of claim 21, ..., the imaging component comprises any combination of CMOS imaging components, charge coupled devices, and light —polar body, avalanche light diode or photoelectric crystal 123052