200839704 P061063 SEZ1T W 23517twf. doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是關於一種晝素電路，且特別是關於一種玎應 用於廣視角（Wide-View Angle, WVA)顯示器之晝素電路與 顯示面板。 【先前技術】 在習知的廣視角技術中，會將晝素分為上下兩部分， φ 分別以不同電壓驅動，使上邊與下邊的液晶轉角不同而達 到視角擴大的效果。圖1為根據傳統技術之廣視角晝素之 電路圖，單一畫素由子晝素11〇、12〇所構成，子晝素no 用以控制晝素的上邊液晶轉角程度，而子晝素12〇則用來 控制畫素的下邊液晶轉角程度。在驅動時，為使子晝素U0 的液晶電容CL1與子晝素120的液晶電容CL2有不同的 晝素電壓，習知技術是由閘極驅動器（Gate Driver)提供 耦合電壓VST1、VST2至補償電容CST1、CST2，以提高 或降低液晶電容CL 1、CL2的跨壓來達成。 ‘上述廣視角技術應用在WOA ( wire on array )的架 構上日守，則如圖2所示，圖2為根據傳統技術之驅動電路 圖。閘極驅動為210、220所輸出的♦禺合電壓vsti、VST2 是根據參考電壓VST而產生，當參考魏VST經由面板 走線傳導時，會因為玻璃走線阻抗（電阻RbR2、R3即 為走線上的寄生電阻）過大，使得每—顆閘極驅動器所提 供的輕合電壓vm、VST2有差異，而在閘極驅動器21〇 與閘極驅動器220之間的顯示區域造成色度不均的現象。 5 200839704 P061063SEZ1TW 23517twf.doc/n 由於WO A架構可節省成本，因此f知的 便無法同時間顧成本與顯示品質。 _視角技術 【發明内容】 本發明是在提供一種晝素電路，利用資、 來改變不同子晝素的驅動電屢，以造成廣視㈣黑方式 本發明是在提供—翻歸面板，料 資结 =不同子晝素的液晶電容，使上下邊液線來 成廣視角的效果。 9得肖不同而造 本發明是在提供一種顯示面板，以不 掃描不同的子畫素，使同一掃描線的子=描線來 〜發明提出—種晝素電路，包括畫素、第—子 線、昂二子資料線以及掃插線。其中，金 ^ :與第二子畫素;第-子資料線對應於; 子全^ 弟—子貝料線輸出第—子晝素電壓至第- 辛弟二子貧料線輪出第二子畫素電壓至第二子書 中弟—子晝素電壓與第二子晝素電壓具有-電壓i 第-=;實=中電路更包括資料線、 線之間，《控於弟-_信號。第二 第1 6 200839704 P061063SEZ1TW 23517twf.doc/n 資料線與資料線之間，並受控於第二切換信號。其中，第 一開關與第二開關根據第一切換信號與第二切換^號，調 整第一畫素電壓與第二畫素電壓之輸出時間。 ^ 在本發明-實施例中’上述第—子晝素包括液晶電 谷、電晶體以及補償電容。電晶體耦接於第一子資料線與 液晶電容之間，並受控於該掃描線，補償電絲液晶電容 並聯耦接第一開關與共用電壓之間。 、 本發明-實施例中’上述第二子晝素包括液晶電 谷、毛晶體以及補償電容。電晶體祕於第二子資料線與 液晶電容之間，並受控於該掃描線，補償電容輕晶電容 並聯耦接第一開關與共用電壓之間。 /、 在本發明—實施例中，上述第—子晝素與第二子晝素 :jr置，且第一子晝素電壓對第—子晝素所造成之液 =I大心二子晝素電壓對第二子晝素所造成之液晶跨 朽次ίί明ί出示面板，包括第—掃描線以及複數 二，、中’第—掃描線對應於複數個第—畫素，每 祉合弟—晝素包括第—子晝素與第二子晝素，而每一個資 子資料線與一第二子資料線，其中第-子 而第Ίΐ輪出第—子畫素電壓至相對應之第—子晝素， 子查去!料線用以輸出第二子晝素電壓至相對應之第二 值了’…、中第—畫素電壓與第二晝素電壓具有-電壓差 在本發明—實施例中，上述顯示面板包括第二掃描 7 200839704 P061063SEZ1TW 23517twf.doc/n 線，對應於複數個第二晝素，每一個第二晝素包括一第三 子晝素與-第四子晝素。其中第—子資料線輪出第三子^ :„應之第三子晝素’第二子資料線輪出第四； 四晝素電壓具有差值。 -素^與弟 在本發明一實施例中，上述每一個資料線更包括第一 ，關與第二開關。其中第—開關耦接於相對應之資料線與 第-子資料線之間，並受控於—第—切換信號；第二開/關 耦接於相對應之資料線與第二子資料線之間，並受控於一 第二受控信號。其中第—開關與第二開關根據第—ς換信 號與第二切換信號，調整第一晝素電壓與第二晝素電壓之 輸出時間。200839704 P061063 SEZ1T W 23517twf. doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a halogen circuit, and more particularly to a 玎 application for Wide-View Angle (WVA) displays Alizarin circuit and display panel. [Prior Art] In the conventional wide viewing angle technique, the element is divided into upper and lower parts, and φ is driven by different voltages, so that the liquid crystal corners of the upper side and the lower side are different to achieve the effect of widening the angle of view. 1 is a circuit diagram of a wide viewing angle element according to the conventional technology. A single pixel is composed of sub-small elements 11 〇 and 12 , , and a sub- 昼 element no is used to control the degree of liquid crystal corner of the upper side of the element, while the sub-pixel 12 〇 Used to control the degree of liquid crystal corner under the pixels. In driving, in order to make the liquid crystal capacitor CL1 of the sub-single U0 and the liquid crystal capacitor CL2 of the sub-single 120 have different pixel voltages, the conventional technique is to provide the coupling voltages VST1, VST2 to the compensation by the gate driver (Gate Driver). Capacitors CST1, CST2 are achieved by increasing or decreasing the voltage across the liquid crystal capacitors CL1, CL2. ‘The above wide viewing angle technology is applied to the WOA (wire on array) architecture, as shown in Fig. 2, and Fig. 2 is a driving circuit diagram according to the conventional technology. The gate voltage is 210, 220. The output voltages vsti and VST2 are generated according to the reference voltage VST. When the reference Wei VST is conducted through the panel trace, the resistance of the glass trace (the resistors RbR2 and R3 are taken). The parasitic resistance on the line is too large, so that the light-closing voltages vm and VST2 provided by each of the gate drivers are different, and the display region between the gate driver 21A and the gate driver 220 causes chromaticity unevenness. . 5 200839704 P061063SEZ1TW 23517twf.doc/n Since the WO A architecture can save costs, it is impossible to understand the cost and display quality at the same time. _Viewing technology [Summary of the Invention] The present invention is to provide a halogen circuit, which utilizes capital to change the driving power of different sub-units to cause a wide-view (four) black mode. The present invention is provided in a reversal panel. Junction = liquid crystal capacitors of different sub-small elements, so that the upper and lower liquid lines can be used to achieve a wide viewing angle. The invention is provided by providing a display panel so as not to scan different sub-pixels, so that the sub-pictures of the same scanning line are invented by the invention - a pixel circuit including a pixel and a first sub-line , Ang Erzi data line and sweep line. Wherein, the gold ^: and the second sub-pixel; the first-sub data line corresponds to; the sub-quantity - the sub-bean line outputs the first sub-single voltage to the first - the Xindi two sub-material line rounds out the second sub- The pixel voltage to the second sub-book - the sub-single voltage and the second sub-single voltage have a voltage - the first -=; the real = middle circuit also includes the data line, between the lines, "control the brother - _ signal . Second No. 1 6 200839704 P061063SEZ1TW 23517twf.doc/n Between the data line and the data line, and controlled by the second switching signal. The first switch and the second switch adjust the output time of the first pixel voltage and the second pixel voltage according to the first switching signal and the second switching signal. ^ In the present invention - the embodiment - the above-mentioned first sub-halogen includes a liquid crystal cell, a transistor, and a compensation capacitor. The transistor is coupled between the first sub-data line and the liquid crystal capacitor and controlled by the scan line, and the compensation wire liquid crystal capacitor is coupled in parallel between the first switch and the common voltage. In the present invention - the second sub-halogen includes the liquid crystal cell, the hair crystal, and the compensation capacitor. The transistor is secreted between the second sub-data line and the liquid crystal capacitor, and is controlled by the scan line, and the compensation capacitor light crystal capacitor is coupled in parallel between the first switch and the common voltage. In the present invention, in the embodiment, the first sub-halogen and the second sub-halogen: jr are set, and the first sub-dinon voltage is caused by the first sub-halogen. The voltage is applied to the liquid crystal of the second sub-plasma. The panel is displayed, including the first scan line and the second number, and the middle 'the scan line corresponds to the plurality of first pixels. - The halogen includes a first sub-salm and a second sub-salmon, and each of the sub-data lines and a second sub-data line, wherein the first sub- and the third sub-pixel sub-pixel voltage are corresponding to The first - sub-salmon, the sub-check! The material line is used to output the second sub-salvin voltage to the corresponding second value '..., the first-pixel voltage and the second pixel voltage have a - voltage difference in this In an embodiment of the invention, the display panel includes a second scan 7 200839704 P061063SEZ1TW 23517twf.doc/n line corresponding to the plurality of second pixels, each of the second elements including a third sub-genogen and a fourth sub- Russell. The first sub-data line rounds out the third sub-^: „the third sub-small element of the second sub-data line turns out the fourth; the tetracycline voltage has a difference. In the example, each of the data lines further includes a first switch, a second switch, and a second switch, wherein the first switch is coupled between the corresponding data line and the first-sub data line, and is controlled by the first-switching signal; The second on/off is coupled between the corresponding data line and the second sub data line, and is controlled by a second controlled signal, wherein the first switch and the second switch are based on the first switch signal and the second switch Switching signals to adjust the output time of the first pixel voltage and the second pixel voltage.
本發明提出一種晝素電路，包括晝素、第一子掃描 線、第一子掃描線以及資料線。其中晝素具有第一子書素 與第二子晝素，第一子掃描線對應於第一子晝素，而第二 子掃描線對應於第二子晝素。當第一子掃描線致能時，輸 出第一子晝素電壓至第一子晝素，當第二子掃描線致能 ，輸出弟一子掃描線至第二子晝素，其中第一子書素電 壓與弟一子晝素電壓具有一電壓差值。 在本發明一實施例中，上述畫素電路更包括掃描線、 第一開關以及第二開關。掃描線用以致能第一子掃描線與 第二子掃描線，第一開關耦接於掃描線與第一子掃描線之 間，並受控於第一切換信號。第二開關耦接於掃描線與第 一子掃描線之間，並受控於第二切換信號，其中第一開關 8 200839704 P061063SEZ1TW 23517twf.doc/n 與第二開闕根據第一切換信號與第二切換戶號 整第一 子掃描線與第二子触線賴能相。^^ 本發明提出一種顯示面板，包括複數個第一畫素、第 知描線以及複數個資料線。其中每一個第一書素具有一 第一子畫素與一第二子畫素，第一掃描線對應於第一晝 素，且包括一第一子掃描線與一第二子掃描線。其中第一 子掃描線與第二子掃描線交錯耦接於上述第一畫素之第一 =畫素與第二子畫素。而上述資料線配合第一子掃描線與 第一子掃描線之致能時間，輸出相對應之第一子畫素電壓 ^上述第一子晝素，輸出相對應之第二子晝素電壓至上述 第二子晝素，其中第一子晝素電壓與第二子晝素電壓具有 一電壓差值。 ^本，明因採用資料寫入的方式來改變上下邊液晶的 驅動電壓，可避免因WOA結構而造成色度不均的現象。 在驅動上’子晝素的驅動電壓直接由源極驅動器作調整， 以資料馬入的方式，配合子掃描線或子資料線的電路架 構’可準確調整晝素上下邊液晶的轉角程度，而造成廣視 角的效果。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉本發明之較佳實施例，並配合所附圖式， 作詳細說明如下。 【實施方式】 —實施例_ 圖3為根據本發明第一實施例之晝素電路圖，晝素電 9 200839704 P061063SEZ1TW 23517twf.doc/n 路300包括晝素（由第一子晝素31〇與第二子晝素32〇所 構成）、第一子資料線SDL1、第二子資料線SDL2以及掃 描線SL1。第一子晝素310包括電晶體M1 (例如薄膜電 晶體，thin film transistor)、液晶電容CL1 (由液晶兩側 電極所形成）以及補償電容CST1。第一子晝素320包括 %曰日體M2 (例如薄膜電晶體，thin transistor )、液晶 電谷CL2(由液晶兩侧電極所形成）以及補償電容CST2。 φ 將單一晝素分為第一子晝素310與第二子畫素320，主要 是為了讓上下邊的液晶產生不同的轉角，而形成廣視角的 效，，其區分方式則例如為上下配置，將晝素上半部配置 為第一子晝素310,將畫素下半部配置為第二子晝素32〇。 ^在第一子晝素31〇中，電晶體Ml耦接耦接於第一子 資料線SDL1與液曰曰電各CL1之間，並受控於掃描線sli， 補仏私谷CST1與液晶電容CL1並聯耦接電晶體M1與共 用電，VC0M之間。在第二子畫素32〇巾，電晶體奶耦 接於第二子資料線SDL2與液晶電容CL2之間，並受控於 讚掃描線SL2，補償電容CST2與液晶電容①並聯^電 晶體M2與共用電壓vc〇M之間，共用電壓vc〇m可等 於接地電壓或一特定電壓值。 掃描線SL1耦接於電晶體MlMi的閘極，以掃描子 畫素310、320,第一子資料線SDU與第二子資料線舰] 分別，應於第-子晝素31〇與第二子晝素32G。當掃描線 SL=描第一子晝素31〇與第二子晝素32〇時（掃描線犯 致能時），第一子資料線SDL1輪出第一子晝素電麗州 200839704 P061063SEZ1TW 23517twf.doc/n 至第一子晝素310，第一子資料線SDL2輪出第二子查素 電壓SV2至第二子晝素320,其中第—子晝素電^^與 第二子晝素電壓SV1具有一電壓差值，例如第一子晝素電 壓SV1大於第二子晝素電壓SV2或第一子晝素電壓SV1 小於第二子晝素電壓SV2。 在本發明另一實施例中，若第一子晝素31〇位 於晝素上邊，弟一子晝素320位於晝素下邊，當正極 ⑩ 性驅動時，可使第一子晝素電壓SV1大於第二子晝素電 壓SV2，當負極性驅動時，可使第一子晝素電壓SV1小於 第一子晝素電壓SV2，以達成廣視角的效果。此外，第一 子晝素310與第二子晝素320的配置方式並無限制， 亦可左右方式配置，或採取對角配置皆可。在驅動 時，第一子晝素310與第二子晝素320所需的電壓差 值皆可利用本實施例之技術手段，以資料寫入的方式 加以實現。 • 第二實施例 圖4為根據本發明第二實施例之顯示面板之等 效電路圖。顯示面板400包括晝素401〜403 (其餘 晝素未繪示），掃描線SL1、SL2、資料線DL1、DL2， 其中每一資料線DL1、DL2均包括第一子資料線SDL1 與第二子資料線SDL2。以資料線DL1為例，資料線 DL1經由開關（電晶體SM1)耦接於第一子資料線 SDL1，經由開關（電晶體SM2)耦接於第二子資料線 11 200839704 P061063SEZ1TW 23517twf.doc/n SDL2。關於晝素401〜403之結構則請參照圖3實施 例之說明，在此不加累述。 每一掃描線SL1均對應複數個晝素，當掃描線 SL1掃描面板中的晝素（例如晝素401、403)時，資 料線（例如資料線DL1〜DL2 )會在一掃描線時間内， 依序驅動第一子晝素（如410)與第二子晝素（如420 ) 或是依序驅動第二子晝素（如420)與第一子晝素（如 410)。在本實施例中，將驅動第一子晝素（如410) 的驅動電壓稱為第一子晝素電壓，將驅動第二子晝素 (如420 )的驅動電壓稱為第二子晝素電壓。每一資 料線DL1、DL2所輸出的第一子晝素電壓與第二子晝 素電壓會依照不同晝素而有所差別。 接下來，以晝素401為例，說明本實施例之操 作方式。當掃描線SL1掃描晝素401時，切換信號 SW1致能以導通電晶體SM1，資料線DL1會先輸出第 一子晝素電壓SV1，並經由第一子資料線SDL1輸出 至第一子晝素410，然後切換信號SW2致能以導通電 晶體SM2 5貢料線DL1將驅動電遥調整為弟二子晝素 電壓SV2，並經由第二子資料線SDL2輸出至第二子 晝素420。其中，第一子晝素電壓SV1與第二子晝素電壓 SV2具有一電壓差值，使第一子晝素410與第二子晝素420 的液晶轉角不同。上述第一子晝素電壓SV1與第二子晝 素電壓SV2的輸出順序並不限定’亦可先輸出第二子 晝素電壓SV2，然後再輸出第二子晝素電壓SV1，僅 12 200839704 P06I063SEZ1TW 23517twf.doc/n 需配合切換信〇以、The present invention provides a halogen circuit comprising a halogen, a first sub-scan line, a first sub-scan line, and a data line. Wherein the halogen has a first sub-study and a second sub-tendin, the first sub-scanning line corresponds to the first sub-tendin, and the second sub-scanning line corresponds to the second sub-tendin. When the first sub-scanning line is enabled, the first sub-plasma voltage is outputted to the first sub-tendin, and when the second sub-scanning line is enabled, the sub-scanning line is outputted to the second sub-tendin, wherein the first sub-pixel The book voltage has a voltage difference from the voltage of the child. In an embodiment of the invention, the pixel circuit further includes a scan line, a first switch, and a second switch. The scan line is configured to enable the first sub-scan line and the second sub-scan line, and the first switch is coupled between the scan line and the first sub-scan line and controlled by the first switching signal. The second switch is coupled between the scan line and the first sub-scan line, and is controlled by the second switch signal, wherein the first switch 8 200839704 P061063SEZ1TW 23517twf.doc/n and the second switch are according to the first switching signal and the first switch The second sub-scanning line is connected to the second sub-line. ^^ The present invention provides a display panel comprising a plurality of first pixels, a first description line, and a plurality of data lines. Each of the first pixels has a first sub-pixel and a second sub-pixel. The first scan line corresponds to the first pixel and includes a first sub-scan line and a second sub-scan line. The first sub-scanning line and the second sub-scanning line are alternately coupled to the first pixel and the second sub-pixel of the first pixel. And the data line cooperates with the enabling time of the first sub-scanning line and the first sub-scanning line, outputs a corresponding first sub-pixel voltage, the first sub-tendin, and outputs a corresponding second sub-plasma voltage to The second sub-tendin, wherein the first sub-salect voltage has a voltage difference from the second sub-halogen voltage. ^ Ben, Ming uses the method of data writing to change the driving voltage of the upper and lower liquid crystals, which can avoid the phenomenon of uneven chromaticity caused by the WOA structure. In the driving, the driving voltage of the sub-small element is directly adjusted by the source driver, and the circuit structure of the sub-scanning line or the sub-data line can accurately adjust the degree of the corner of the liquid crystal on the upper and lower sides of the pixel. The effect of a wide viewing angle. The above and other objects, features, and advantages of the present invention will become more apparent from the <RTIgt; [Embodiment] - Embodiments FIG. 3 is a circuit diagram of a pixel device according to a first embodiment of the present invention. A battery element 9 200839704 P061063SEZ1TW 23517twf.doc/n Road 300 includes a pixel (by the first sub-unit 31 and the first The second sub-form 32 is formed, the first sub-data line SDL1, the second sub-data line SDL2, and the scan line SL1. The first sub-cell 310 includes a transistor M1 (e.g., a thin film transistor), a liquid crystal capacitor CL1 (formed by electrodes on both sides of the liquid crystal), and a compensation capacitor CST1. The first sub-alloy 320 includes a % 曰 body M2 (eg, a thin transistor), a liquid crystal valley CL2 (formed by electrodes on both sides of the liquid crystal), and a compensation capacitor CST2. φ Dividing a single element into a first sub-tendin 310 and a second sub-pixel 320, mainly for the purpose of allowing the liquid crystals of the upper and lower sides to have different corners, thereby forming a wide viewing angle, and the distinguishing manner is, for example, a top-and-bottom configuration. The upper part of the pixel is configured as the first child element 310, and the lower part of the picture element is configured as the second child element 32〇. In the first sub-cell 31, the transistor M1 is coupled between the first sub-data line SDL1 and the liquid-electrode CL1, and is controlled by the scan line sli, complementing the private valley CST1 and the liquid crystal The capacitor CL1 is coupled in parallel between the transistor M1 and the shared power, VC0M. In the second sub-pixel 32 wipes, the transistor milk is coupled between the second sub-data line SDL2 and the liquid crystal capacitor CL2, and is controlled by the praise scan line SL2, and the compensation capacitor CST2 is connected in parallel with the liquid crystal capacitor 1 ^the transistor M2 Between the shared voltage vc〇M, the common voltage vc〇m can be equal to the ground voltage or a specific voltage value. The scan line SL1 is coupled to the gate of the transistor M1Mi to scan the sub-pixels 310, 320, the first sub-data line SDU and the second sub-line ship respectively, respectively, and should be in the first sub-single 31〇 and the second Zizi 32G. When the scan line SL=the first sub-small element 31〇 and the second sub-small element 32〇 (when the scanning line is activated), the first sub-data line SDL1 rotates the first sub-dielectric element Lizhou 200839704 P061063SEZ1TW 23517twf .doc/n to the first sub-salm 310, the first sub-data line SDL2 rotates the second sub-character voltage SV2 to the second sub-salm 320, wherein the first sub-element and the second sub-halogen The voltage SV1 has a voltage difference value, for example, the first sub-element voltage SV1 is greater than the second sub-element voltage SV2 or the first sub-element voltage SV1 is smaller than the second sub-element voltage SV2. In another embodiment of the present invention, if the first sub-salm 31 is located on the pixel, the dice-capital 320 is located below the pixel, and when the positive electrode is driven by 10, the first sub-segment voltage SV1 is greater than The second sub-single voltage SV2, when driven by the negative polarity, can make the first sub-segment voltage SV1 smaller than the first sub-segment voltage SV2 to achieve the effect of wide viewing angle. In addition, the arrangement of the first sub-cells 310 and the second sub-cells 320 is not limited, and may be configured in a left-right manner or in a diagonal configuration. When driving, the voltage difference required between the first sub-cell 310 and the second sub-element 320 can be realized by means of data writing by using the technical means of the embodiment. • Second Embodiment Fig. 4 is an equivalent circuit diagram of a display panel according to a second embodiment of the present invention. The display panel 400 includes pixels 401 401 403 (the remaining elements are not shown), scan lines SL1, SL2, data lines DL1, DL2, wherein each of the data lines DL1, DL2 includes a first sub-data line SDL1 and a second sub- Data line SDL2. Taking the data line DL1 as an example, the data line DL1 is coupled to the first sub-data line SDL1 via a switch (transistor SM1), and is coupled to the second sub-data line 11 via a switch (transistor SM2). 200839704 P061063SEZ1TW 23517twf.doc/n SDL2. For the structure of the elements 401 to 403, please refer to the description of the embodiment of Fig. 3, and the description will not be repeated here. Each scan line SL1 corresponds to a plurality of pixels. When the scan line SL1 scans the pixels in the panel (for example, the pixels 401 and 403), the data lines (for example, the data lines DL1 to DL2) are within a scan line time. The first child element (such as 410) and the second child element (such as 420) are sequentially driven or sequentially driven by the second child element (such as 420) and the first child element (such as 410). In this embodiment, the driving voltage for driving the first sub-tendin (such as 410) is referred to as a first sub-tendin voltage, and the driving voltage for driving the second sub-element (such as 420) is referred to as a second sub-tendin. Voltage. The first sub-plasma voltage and the second sub-guine voltage output by each of the data lines DL1, DL2 may differ according to different elements. Next, the operation mode of this embodiment will be described by taking the pixel 401 as an example. When the scan line SL1 scans the pixel 401, the switching signal SW1 is enabled to conduct the current crystal SM1, and the data line DL1 first outputs the first sub-plasma voltage SV1, and is output to the first sub-element via the first sub-data line SDL1. 410, then the switching signal SW2 is enabled to adjust the driving power to the second sub-segment voltage SV2 by the conducting current crystal SM2 5 tributary line DL1, and output to the second sub-cell 420 via the second sub-data line SDL2. The first sub-halogen voltage SV1 and the second sub-halogen voltage SV2 have a voltage difference, so that the liquid crystal rotation angles of the first sub-cell 410 and the second sub-halogen 420 are different. The output order of the first sub-segment voltage SV1 and the second sub-small voltage SV2 is not limited to 'the second sub-element voltage SV2 may be output first, and then the second sub-element voltage SV1 is output, only 12 200839704 P06I063SEZ1TW 23517twf.doc/n needs to cooperate with the switch letterhead,
號SW1、SW2的致能時二，能時間即可。切換信 子晝素電壓SV1或第二子全用以調整相對應之第一 同理，W應於掃^線12素的\壓=2的輸出時間。 包括兩個子晝素（可稱其為第=的息素（如402)，同樣 440)，分別配置於畫素的上下二子晝素430與第四子晝素 素402時，資料線况丨同樣备當掃描線SL2掃描晝 畫素電壓與第四子晝素電壓二壓差值的第三子 讓其具有廣視肖效果。轉作：素402中的子畫素’ 在此不加累述。 木作即，杯照上述圖4說明， -料例中，當畫素4qi 4於正極性驅動時’ 二枓綠DL1會增加一電壓調整值八¥至第一子晝素電 壓SV1二並使第二子晝素電壓SV2降低一電壓ς整值 △ V ^旦素401處於負極性驅動時，資料線dli會 1加兒壓調整值Δν至第二子晝素電壓SV2，並使 第一子晝素電壓SV1降低一電壓調整值av，電壓調 整值為正數。換言之，第一子晝素電壓SV1與第 一子畫素電壓S72之間的電壓差值為兩倍的電壓調 整值AV。在同一晝素中，利用電壓調整值av，可使 旦素中的上下子晝素（例如第一子晝素410與第二子 晝素420 )的液晶電容產生不同的跨壓，而影響上下 兩邊的液晶轉角，進而達成廣視角的效果。若欲得到 相反的電壓調整效果，僅需將電壓調整值AV設定為 負值即可。關於第一子晝素電壓SV1的第二子畫素電 13 200839704 FUblUbJbEZITW 23517twf.doc/n 壓SV2的調整機制，可藉由時序控制器（Timer control)或源極驅動器（source driver)直接對寫 入資料（電壓）進行調整皆可。 接下來，以信號波形來說明資料線DL1與切換 信號SW1、SW2之間的關係。圖5為根據圖4之信號 波形圖。圖5為正極性驅動下之實施例，其中當切換 信號SW1致能時，資料線DL1輸出增加電壓調整值△ V之第一子晝素電壓SV1，然後輪到切換信號SW2致 能，資料線DL1則輸出減去電壓調整值AV之第二子 晝素電壓SV2。其中第一子晝素電壓SV1與第二子晝 素電壓SV2的電壓差值為兩倍電壓調整值AV。電壓 調整值Δν則可依照設計需求而定。 當掃描線（如SL1、SL2)依序掃描面板中之畫 素（如401〜403)時，資料線（如DL1、DL2)則會 在同一掃描線時間内，以不同的驅動電壓（第一子畫 素電壓與第二子晝素電壓）調整個別晝素中子晝素， 讓晝素的上下兩邊液晶可以有不同程度的轉角，而造 成廣視角效果。應由本發明之揭露，在本技術領域具 有通常知識者，應可輕易推知其於個別晝素的驅動過 程，在此不加累述。 第三實施例 上述第第一、二實施例是利用子資料線來個別 驅動子晝素，以達到廣視角的效果。在本發明另一實 14 200839704 FUOiUbibEZITW 23517twf.doc/n 施例中，亦可利用子掃描線，分開子晝素的掃描時 間’讓同一條資料線對不同子晝素輸出不同的驅動電 壓。_ 6為根據本發明第三實施例之晝素電路圖。書 素電路600包括晝素（由第一子晝素610與第二子晝素620 所構成）、資料線DL1、第一子掃描線SSL1以及第二子 知描線SSL2。第一子畫素610與第二子晝素620分別包括 電晶體Ml、M2、液晶電容CL1、CL2、補償電容csi、 CS2，其電路結構之說明請參照圖3之說明，其主要差別 在於第一子畫素610的電晶體Ml是受控於第一子掃描線 SSL1，而第二子晝素620的電晶體M2是受控於第二子掃 描線SSL2。 當第一子掃描線SSL1致能時，資料線DL1輸出第一 子晝素電壓SV1至第一子晝素610,當第二子掃描線SSL1 致能時，資料線DL1輸出第二子掃描線SSL2至第二子晝 素620。其中第一子晝素電壓SV1與第二子晝素電壓SV2 具有一電壓差值。其中第一子晝素電壓SV1與第二子晝素 電壓SV2在不同驅動極性下之調整方式與其電壓差值的設 定則請參照上述一、二實施例之說明，在此不加累述。 茗四實施例 上述圖6之實施例亦擴充應用至整個顯示面 板，圖7為根據本發明第四實施例之顯示面板之等效 電路圖。顯示面板700包括晝素701〜703 (其餘畫 素未繪示），掃描線SL1、SL2、資料線DL1、DL2, 15 200839704 FUbiUbiSEZITW 23517twf.doc/n 其中每一掃描線SL1、SL2均包括第一子掃描線SSL1 與第二子掃描線SSL2,以對應於第一子晝素（如710) 與第二子晝素（如720 )。以掃描線SL1為例，掃描 線SL1經由開關（電晶體SM1)耦接於第一子掃描線 SSL1，經由開關（電晶體SM2)耦接於第二子掃描線 SSL2。其中電晶體SM1受控於切換信號SW1，電晶體 SM2受控於切換信號SW2。關於晝素701〜703之結構 則請參照圖6實施例之說明，在此不加累述。 第一子掃描線SSL1與第二子掃描線SSL2交錯 耦接於所對應之畫素（如701、703 )之第一子晝素 710、730與第二子晝素720、740。如圖7所示，第 一子掃描線SSL1耦接於第一子晝素710與第二子晝 素740，而第二子掃描線SSL2則耦接於第二子晝素 720與第一子晝素730。此種交錯配置的方式可讓顯 示面板700適用於點反轉之驅動模式。由於相鄰晝素 的驅動極性相反，因此在同一晝面（f rame )中，當 第一子晝素710所接受的第一子晝素電壓SV1為提高 時，其相鄰晝素703的第二子晝素740所接受的第二 子晝素電壓也需提高。同理，第二子晝素720所接受 的第二子晝素電壓SV1與第一子晝素730所接受的第 一子晝素電壓SV1則皆為降低。 換言之，相鄰晝素的第一子晝素（如710)與第 二子晝素（如740 )的驅動電壓調整方式相同，而第 二子畫素（如720 )與第一子晝素（如730 )的驅動 16 200839704 FU610b3bEZlTW 23517twf.doc/n 電壓調整方式相同。因此，利用交錯的耦接方式，當 第一子掃描線SSL1致能時，資料線DL1、DL2僅需以 相同的調整方式（增加晝素電壓或是降低晝素電壓） 來驅動第一子晝素710與第二子晝素740即可。同 理，當第二子掃描線SSL2致能時，資料線DL1、DL2 僅需以相同的調整方式（增加晝素電壓或是降低晝素 電壓）來驅動第二子晝素720與第一子晝素730即 可。同理類推，其餘子掃描線的配置方式相同，在此 不加累述。 接下來，進一步說明本實施例之技術手段， 配合切換信號SW1、SW2，掃描線SL1可於一掃描線 時間内，依序掃描晝素（如701)中之第一子晝素710 與第二子晝素720。在掃描線SL1致能時，若切換信 號SW1致能，則第一子掃描線SSL1隨之致能，若切 換信號SW2致能，則第二子掃描線SSL2則隨之致能。 資料線（如DL1、DL2 )則輸出相對應的晝素驅動電 壓（第一子晝素電壓與第二子晝素電壓）至相對應的 第一子晝素與第二子晝素。其中，在同一晝素中，其 第一子晝素電壓與第二子晝素電壓具有一電壓差 值，藉由調整第一子晝素電壓與第二子晝素電壓，使 同一晝素中之上邊液晶與下邊液晶轉角程度不同，以 達到擴大視角之效果。關於在正極性驅動與負極性驅 動時之電壓調整方式，則請參照上述第二實施例之說 明。 17 200839704 ruoiuojiEZlTW 23517twf.doc/n 同理，對應於掃描線SL2的晝素驅動方式亦相 同，主要皆為利用電晶體SMI、SM2來切換子掃描線 的致能時間，使同一晝素中之第一子晝素與第二子晝 素可在不同時間内被資料線寫入不同的驅動電壓，以 '造成不同液晶轉角程度，而擴大視角。若將晝素702 ‘ 内所包括之子畫素分別稱為第三子晝素750與第四 子畫素760，則資料線DL1會分別輸出相對應之第三 子畫素電壓與第四子晝素電壓至第三子晝素730與 第四子晝素740,且第三子晝素電壓與第四子畫素電 壓具有相同之電壓差值。其餘晝素之驅動方式同理類 推，在此不加累述。在本技術領域具有通常知識者應 可輕易推知上述實施例在不同驅動方式（如點反轉、 列反轉、行反轉等）之實施方式，在此不加累述。 接下來，以信號波形來說明資料線DL1與切換 信號SW1、SW2之間的關係。圖8為根據圖7之信號 波形圖。圖8為正極性驅動下之實施例，其中當切換 _ 信號SW1致能時，資料線DL1輸出增加電壓調整值八 V的第一子晝素電壓SV1至晝素701的上邊子晝素 (第一子晝素710)，資料線DL2輸出增加電壓調整 值的第二子晝素電壓SV2至晝素703的下邊子晝 素（第二子晝素740 )。當切換信號SW2致能時，資 料線DL1則輸出減去電壓調整值AV之第二子晝素電 壓SV2至晝素701的下邊子晝素（第二子晝素720 )， 資料線DL2輸出降低電壓調整值AV的第一子畫素電 18 200839704 jeUblUO^^EZlTW 23517twf.doc/n 壓SV1至畫素703的上邊子晝素（第一子畫素730)。 其中在同一晝素中所接收之第一子畫素電壓SV1與 第二子晝素電壓SV2之間的電壓差值為兩倍電壓調 整值AV，電壓調整值AV則可依照設計需求而定。 圖8與圖5主要差別在於圖8中之切換信號SW1、SW2 是用於切換子掃描線的致能時間，而圖5中之切換信 號SW1、SW2是用於切換資料信號的輸出路徑（不同 子資料線）。 在實際應用中，可配合源極驅動器對書素升壓 的控制，先進行下邊子晝素的寫入，再進行上邊子晝 素的寫入。圖9為根據本發明第四實施例之點反轉之 訊號波形圖。F ( N)表示第N個畫面，f ( N+1 )表示 第N+1個晝面。在第N個晝面中，資料線dli會根據 掃描線SL1、SL2的掃描時間，依序輪出相對應的書 素驅動電壓。以掃描線SL1為例，在掃描線時間T1 中，經由調整切換信號SW2、SW1的致能時間，可依 序致能子掃描線SSL2、SSL1，讓資料線DLi依序輸 出第二子晝素電壓SV1、第一子畫素電壓SV1至相^ 應的子晝素中，兩者具有一電壓差值。接著，當掃描 線SL2致能時，在掃描線時間T2中，經由調^切^ 信號SW2、SW1的致能時間，可依序致能子掃描線 SSL2、SSL1，讓資料線DL1依序輸出負極性驅動之 二子晝素電壓SV2與第-子晝素電壓SV1至相對應的 子晝素中’其中第二子晝素電壓SV2與第一子畫素带 19 200839704 ruoiuo^EZlTW 23517twf.doc/n 壓svi同樣具有一電壓差值。 圖1G為根據圖9之信號波形圖。當子掃 SSL2致能時，資粗綠m 綠 οπο ^ ^貝科線DL1會輸出第二子畫素電壓 ，θ 10(a)所示：當子掃描線ssu致能時， Π1提高驅動電壓以輸出第-子晝素電壓SV卜 如圖（b)所不，盆φ楚 ^ > ^ , 具甲弟一子晝素電壓SV1與第-早 畫素電壓SV2相差雨位+两〜卞 為m)，則調整值Λν。若資料電壓 2本(丄弟—子晝素電壓VI為V(X)+AV，第二子 旦”包堊V2為ν(χ)—△ V，使第一子書盘二 素的液晶跨壓相差兩俨# +颅 旦’、ζ、— 旦 仰左陶借的電壓調整值AV。當铁，力 實施例中，對於子晝素的電壓調整:、4 之—的驅動電壓’同樣可造成上下邊液晶 接下來以晝面的局部晝素驅動狀況，進一 ί說=\同驅動極性下，各子晝素的電壓調整狀 悲。圖11為根據本實施例之晝面驅動電壓示意圖。 Ε 11。中J堇以—2*2之晝素結構為例，說明在點反 轉之驅動模式下’各子晝素的驅動電壓調整方式。圖 至面，其中+表示正極性驅動，—表示負極性驅動，而 每一掃描線SL1、SL2的上下邊各為_子晝素（如 1110 1120) ’子晝素111〇與子晝素1⑽形成一單 位晝素’資料線DL1〜DL4用以輸出驅動 各子 畫素。 20 200839704 ruoiuo^SEZlTW 23517twf.doc/n 在正極性驅動時，位於上邊的子晝素（如1 1 1 0 ) 的驅動電壓會增加一電壓調整值AV，而位於下邊的 子晝素（如1120)的驅動電壓會減少一電壓調整值 △ V。反之，在負極性驅動時，位於上邊的子晝素（如 1130)的驅動電壓會降低一電壓調整值AV，而位於 下邊的子晝素（如1140)的驅動電壓會增加一電壓 調整值AV。藉此，不論是正極性驅動或是負極性驅 動，皆可使位於上邊的子晝素的液晶跨壓大於位於下 邊的子畫素的液晶跨壓，而形成擴大視角的效果。 藉由上述實施例之說明，在本技術領域具有通 常知識者應可輕易推知，不論在何種顯示模式下（如 點反轉、列反轉、行反轉等），皆可利用本發明之技 術手段，以資料寫入的方式改變晝素上下邊的液晶跨 壓，而達到擴大視角的目的。 綜合上述，本發明利用資料寫入的方式，使晝 素的上下邊液晶具有不同的液晶跨壓而達到擴大視 角的功效。在實際應用上，可避免習知技術中，因玻 璃走線阻抗過大而在相鄰閘極驅動器之間的顯示區域 造成色度不均的現象。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域具有通常知識者，在不脫 離本發明之精神和範圍内，當可作些許之更動與潤飾，因 此本發明之保護範圍當視後附之申請專利範圍所界定者為 準。 【圖式簡單說明】 21 200839704 F06I063SEZ1TW 23517twf.doc/n 圖1為根據傳統技術之廣視角晝素之電路圖， 圖2為根據傳統技術之驅動電路圖。 圖3為根據本發明第一實施例之畫素電路圖 圖4為根據本發明第二實施例之顯示面板之等效電路圖。 圖5為根據圖4之信號波形圖。 圖6為根據本發明第三實施例之晝素電路圖。 圖7為根據本發明第四實施例之顯示面板之等效 圖8為根據圖7之信號波形圖。 包路圖。 圖10為根據圖9之信號波形圖。 圖11為根據本實施例之晝面驅動電壓示音圖。 【主要元件符號說明】 VST卜VST2 :耦合電壓 VST :參考電麗 VCOM :共用電壓 DL1〜DL4 :資料線 SL1、SL2 :掃描線 SDL1 :第一子資料線 SDL2 :第二子資料線 SSL1第一子掃描線 SSL2第二子掃描線 SV1 :第一子晝素電壓 SV2:第二子晝素電壓 CL1 、CL2 :液晶電容 22 200839704 P061063SEZ1TW 23517twf.doc/n CSTH、CST2:補償電容 R1、R2、R3 :電阻 Μ 1 、M2、SMI、SM2 :電晶體 △V :電壓調整值 SW1、SW2 :切換信號 F (N):第N個晝面 F (N+1):第N+1個晝面 T1T2 :掃描線時間 110、120、1110〜1140 :子晝素 210、220 :閘極驅動器 300 :晝素電路 310、410、610、710、730 :第一子晝素 320、420、620、720、740 :第二子畫素 400 :顯示面板 401 〜403、701 〜703 :畫素 430、750 :第三子晝素 ⑩ 440、760 :第四子晝素 600 :晝素電路 700 :顯示面板 23When the number of SW1 and SW2 is enabled, the time can be used. The switching signal voltage SV1 or the second sub-quantity is used to adjust the corresponding first principle, and W should be at the output time of the pressing voltage 12 of the scanning line. Including two sub-vegetations (which can be called the first = statin (such as 402), the same 440), respectively, when the upper and lower bismuth 430 and the fourth sucrose 402 of the pixel are arranged, the data line condition 丨Similarly, when the scan line SL2 scans the third sub-pressure difference between the 昼 pixel voltage and the fourth sub-plasma voltage, it has a wide-view effect. Conversion: Sub-pixels in prime 402' are not described here. Wood, that is, the cup is illustrated in Figure 4 above. In the example, when the pixel 4qi 4 is driven in the positive polarity, the second green DL1 will increase a voltage adjustment value of eight ¥ to the first sub-single voltage SV1 and The second sub-single voltage SV2 is reduced by a voltage ς value ΔV. When the 401 is in the negative polarity driving, the data line dli will add a voltage adjustment value Δν to the second sub-plasma voltage SV2, and the first sub-sub The halogen voltage SV1 is lowered by a voltage adjustment value av, and the voltage adjustment value is a positive number. In other words, the voltage difference between the first sub-single voltage SV1 and the first sub-pixel voltage S72 is twice the voltage adjustment value AV. In the same pixel, by using the voltage adjustment value av, the liquid crystal capacitances of the upper and lower sub-tenors in the denier (for example, the first sub-halogen 410 and the second sub-halogen 420) may be different in cross-voltage, and affect the upper and lower sides. The liquid crystal corners on both sides achieve a wide viewing angle. To get the opposite voltage adjustment effect, simply set the voltage adjustment value AV to a negative value. The second sub-pixel power 13 of the first sub-single voltage SV1 200839704 FUblUbJbEZITW 23517twf.doc/n The adjustment mechanism of the SV2 can be directly written by the timing controller or the source driver. The data (voltage) can be adjusted. Next, the relationship between the data line DL1 and the switching signals SW1, SW2 will be described by a signal waveform. Fig. 5 is a waveform diagram of the signal according to Fig. 4. 5 is an embodiment of positive polarity driving, wherein when the switching signal SW1 is enabled, the data line DL1 outputs a first sub-element voltage SV1 that increases the voltage adjustment value ΔV, and then turns on the switching signal SW2 to enable the data line. DL1 outputs a second sub-element voltage SV2 minus the voltage adjustment value AV. The voltage difference between the first sub-single voltage SV1 and the second sub-single voltage SV2 is twice the voltage adjustment value AV. The voltage adjustment value Δν can be determined according to the design requirements. When the scan lines (such as SL1, SL2) sequentially scan the pixels in the panel (such as 401~403), the data lines (such as DL1, DL2) will have different driving voltages in the same scan line time (first) The sub-pixel voltage and the second sub-plasma voltage) adjust individual neutron elements, so that the upper and lower sides of the liquid crystal can have different degrees of rotation, resulting in a wide viewing angle effect. It should be noted by the present invention that those skilled in the art should be able to easily infer the driving process of individual elements, and will not be described here. Third Embodiment The first and second embodiments described above use sub-data lines to individually drive sub-stimuli to achieve a wide viewing angle. In another embodiment of the present invention, the sub-scanning line can be used to separate the scanning time of the sub-small elements to cause the same data line to output different driving voltages to different sub-units. _ 6 is a pixel circuit diagram according to a third embodiment of the present invention. The pixel circuit 600 includes a pixel (consisting of the first sub-cell 610 and the second sub-pixel 620), a data line DL1, a first sub-scan line SSL1, and a second sub-line SSL2. The first sub-pixel 610 and the second sub-pixel 620 respectively include transistors M1 and M2, liquid crystal capacitors CL1 and CL2, and compensation capacitors csi and CS2. For the description of the circuit structure, please refer to FIG. 3, the main difference is The transistor M1 of one subpixel 610 is controlled by the first sub-scan line SSL1, and the transistor M2 of the second sub-cell 620 is controlled by the second sub-scan line SSL2. When the first sub-scanning line SSL1 is enabled, the data line DL1 outputs the first sub-segment voltage SV1 to the first sub-cell 610, and when the second sub-scanning line SSL1 is enabled, the data line DL1 outputs the second sub-scanning line SSL2 to the second child element 620. The first sub-single voltage SV1 and the second sub-halogen voltage SV2 have a voltage difference. For the adjustment of the first sub-single voltage SV1 and the second sub-small voltage SV2 under different driving polarities and the voltage difference, please refer to the description of the first and second embodiments, and no further description is provided here. Fourth Embodiment The above embodiment of Fig. 6 is also extended to the entire display panel, and Fig. 7 is an equivalent circuit diagram of the display panel according to the fourth embodiment of the present invention. The display panel 700 includes pixels 701 703 703 (the remaining pixels are not shown), scan lines SL1, SL2, data lines DL1, DL2, 15 200839704 FUbiUbiSEZITW 23517twf.doc / n each of the scan lines SL1, SL2 includes the first The sub-scan line SSL1 and the second sub-scan line SSL2 correspond to the first sub-element (such as 710) and the second sub-element (such as 720). Taking the scan line SL1 as an example, the scan line SL1 is coupled to the first sub-scan line SSL1 via a switch (the transistor SM1) and to the second sub-scan line SSL2 via a switch (the transistor SM2). The transistor SM1 is controlled by the switching signal SW1, and the transistor SM2 is controlled by the switching signal SW2. Regarding the structure of the elements 701 to 703, please refer to the description of the embodiment of Fig. 6, which will not be described here. The first sub-scanning line SSL1 and the second sub-scanning line SSL2 are interleaved and coupled to the first sub-cell 710, 730 and the second sub-tend 720, 740 of the corresponding pixel (eg, 701, 703). As shown in FIG. 7, the first sub-scanning line SSL1 is coupled to the first sub-cell 710 and the second sub-cell 740, and the second sub-scanning line SSL2 is coupled to the second sub-cell 720 and the first sub-segment Alizarin 730. This staggered configuration allows the display panel 700 to be adapted for the dot inversion drive mode. Since the driving polarity of the adjacent pixels is opposite, in the same plane (frame), when the first sub-tendin voltage SV1 accepted by the first sub-tend 710 is improved, the neighboring element 703 is The second sub-salectin voltage accepted by the diterpenoid 740 also needs to be increased. Similarly, the second sub-satellite voltage SV1 received by the second sub-satellite 720 and the first sub-satellite voltage SV1 accepted by the first sub-satellite 730 are both reduced. In other words, the driving voltage of the first sub-element of the adjacent pixel (such as 710) and the second sub-tenor (such as 740) are adjusted in the same manner, and the second sub-pixel (such as 720) and the first sub-element ( Such as 730) drive 16 200839704 FU610b3bEZlTW 23517twf.doc / n voltage adjustment is the same. Therefore, with the interleaved coupling mode, when the first sub-scanning line SSL1 is enabled, the data lines DL1 and DL2 only need to be driven in the same manner (increasing the voltage of the pixel or lowering the voltage of the pixel) to drive the first sub-turn. The element 710 and the second sub element 740 can be used. Similarly, when the second sub-scanning line SSL2 is enabled, the data lines DL1 and DL2 only need to be driven in the same manner (increasing the voltage of the pixel or lowering the voltage of the pixel) to drive the second sub-plasma 720 and the first sub-segment. Alizarin 730 can be. Similarly, the other sub-scan lines are configured in the same way, and are not described here. Next, the technical means of the embodiment is further described. With the switching signals SW1 and SW2, the scan line SL1 can sequentially scan the first sub-cell 710 and the second of the pixels (such as 701) within a scan line time.昼素素720. When the scan line SL1 is enabled, if the switching signal SW1 is enabled, the first sub-scan line SSL1 is enabled, and if the switching signal SW2 is enabled, the second sub-scan line SSL2 is enabled. The data lines (e.g., DL1, DL2) output corresponding pixel drive voltages (the first sub-segment voltage and the second sub-small voltage) to the corresponding first and second sub-halogens. Wherein, in the same pixel, the first sub-salectin voltage and the second sub-halogen voltage have a voltage difference, by adjusting the first sub-plasma voltage and the second sub-halogen voltage, so that the same pixel The liquid crystal on the upper side is different from the angle of the liquid crystal on the lower side to achieve the effect of widening the viewing angle. For the voltage adjustment method in the case of the positive polarity drive and the negative polarity drive, please refer to the description of the second embodiment above. 17 200839704 ruoiuojiEZlTW 23517twf.doc/n Similarly, the pixel driving method corresponding to the scanning line SL2 is also the same, mainly using the transistors SMI, SM2 to switch the enabling time of the sub-scanning line, so that the same element A sub-salm and a second sub-small element can be written to different driving voltages by data lines at different times to 'increase the angle of different liquid crystals, and the viewing angle is enlarged. If the sub-pixels included in the pixel 702 ' are referred to as the third sub-salm 750 and the fourth sub-pixel 760, respectively, the data line DL1 outputs the corresponding third sub-pixel voltage and the fourth sub-pixel respectively. The voltage is applied to the third sub-cell 730 and the fourth sub-halogen 740, and the third sub-decene voltage and the fourth sub-pixel voltage have the same voltage difference. The driving methods of the remaining elements are similarly analogous and will not be described here. Those skilled in the art should be able to easily infer the implementation of the above embodiments in different driving modes (such as dot inversion, column inversion, line inversion, etc.), and will not be described here. Next, the relationship between the data line DL1 and the switching signals SW1, SW2 will be described by a signal waveform. Figure 8 is a waveform diagram of the signal according to Figure 7. 8 is an embodiment of positive polarity driving, wherein when the switching_signal SW1 is enabled, the data line DL1 outputs a first sub-segment voltage SV1 that increases the voltage adjustment value of eight V to the upper sub-element of the pixel 701 (the first A sub-small element 710), the data line DL2 outputs a second sub-segment voltage SV2 that increases the voltage adjustment value to the lower sub-small element of the alizarin 703 (the second sub-element 740). When the switching signal SW2 is enabled, the data line DL1 outputs the second sub-plasma voltage SV2 minus the voltage adjustment value AV to the lower sub-element of the pixel 701 (the second sub-element 720), and the output of the data line DL2 is lowered. The first sub-pixel of the voltage adjustment value AV 18 200839704 jeUblUO^^EZlTW 23517twf.doc/n presses SV1 to the upper sub-pixel of the pixel 703 (the first sub-pixel 730). The voltage difference between the first sub-pixel voltage SV1 and the second sub-pixel voltage SV2 received in the same pixel is twice the voltage adjustment value AV, and the voltage adjustment value AV can be determined according to design requirements. The main difference between FIG. 8 and FIG. 5 is that the switching signals SW1 and SW2 in FIG. 8 are the enabling times for switching the sub-scanning lines, and the switching signals SW1 and SW2 in FIG. 5 are the output paths for switching the data signals (different Sub data line). In practical applications, the source driver can be used to control the pixel boost, first write the lower sub-small element, and then write the upper sub-small element. Fig. 9 is a signal waveform diagram of dot inversion according to a fourth embodiment of the present invention. F ( N) represents the Nth picture, and f ( N+1 ) represents the N+1th picture. In the Nth facet, the data line dli sequentially rotates the corresponding book driving voltage according to the scanning time of the scanning lines SL1 and SL2. Taking the scan line SL1 as an example, in the scan line time T1, by adjusting the enable time of the switching signals SW2 and SW1, the sub-scan lines SSL2 and SSL1 can be sequentially enabled, and the data line DLi can sequentially output the second sub-element. The voltage SV1, the first sub-pixel voltage SV1, and the corresponding sub-mechanics have a voltage difference. Then, when the scan line SL2 is enabled, in the scan line time T2, the sub-scan lines SSL2 and SSL1 can be sequentially enabled via the enable time of the tuning signals SW2 and SW1, and the data lines DL1 are sequentially output. The negatively driven diterpenoid voltage SV2 and the first sub-halogen voltage SV1 correspond to the sub-study of the second sub-segment voltage SV2 and the first sub-pixel strip 19 200839704 ruoiuo^EZlTW 23517twf.doc/ The n svi also has a voltage difference. Fig. 1G is a signal waveform diagram according to Fig. 9. When the sub-scan SSL2 is enabled, the coarse green m green οπο ^ ^ Becco line DL1 will output the second sub-pixel voltage, θ 10 (a): when the sub-scan line ssu is enabled, Π1 increases the driving voltage To output the first-sub-divinity voltage SV, as shown in Figure (b), the basin φ楚^ > ^, with a sub-diet voltage SV1 and the first-pre-pixel voltage SV2 difference between the rain level + two ~ 卞For m), adjust the value Λν. If the data voltage is 2 (the younger brother-subsequence voltage VI is V(X)+AV, the second child is ”V2 is ν(χ)-ΔV, so that the first sub-book has a liquid crystal cross The pressure difference is two 俨# +Chudan Dan, ζ, ——Yang Zuo Tao borrowed the voltage adjustment value AV. When the iron, force example, for the voltage adjustment of the sub-tendin: 4, the drive voltage ' The upper and lower liquid crystals are driven by the local elemental driving condition of the kneading surface, and the voltage adjustment of each sub element is sad under the same driving polarity. FIG. 11 is a schematic diagram of the kneading driving voltage according to the embodiment. Ε 11. The J 堇 堇 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — The negative polarity drive is indicated, and the upper and lower sides of each of the scan lines SL1 and SL2 are each a sub-element (e.g., 1110 1120). The sub-small element 111 and the sub-small element 1 (10) form a unit of a halogen element' data line DL1 to DL4. The sub-pixels are driven by the output. 20 200839704 ruoiuo^SEZlTW 23517twf.doc/n When the positive polarity is driven, the sub-element located above For example, the driving voltage of 1 1 1 0 ) is increased by a voltage adjustment value AV, and the driving voltage of the lower sub-element (such as 1120) is reduced by a voltage adjustment value Δ V. Conversely, when driving at the negative polarity, it is above The driving voltage of the sub-element (such as 1130) is lowered by a voltage adjustment value AV, and the driving voltage of the sub-element (such as 1140) below is increased by a voltage adjustment value AV. Thus, whether it is a positive polarity driving or The negative polarity driving can make the liquid crystal cross-pressure of the sub-small element on the upper side larger than the liquid crystal cross-pressure of the sub-pixel located on the lower side, thereby forming an effect of expanding the viewing angle. With the description of the above embodiments, it is common in the technical field. The knowledge person should be able to easily infer that, regardless of the display mode (such as dot inversion, column inversion, line inversion, etc.), the technical means of the present invention can be utilized to change the upper and lower sides of the element by means of data writing. The liquid crystal crosses the pressure to achieve the purpose of expanding the viewing angle. In summary, the present invention utilizes the method of data writing to make the upper and lower liquid crystals of the alizarin have different liquid crystal cross-pressures to achieve the effect of expanding the viewing angle. In the conventional application, the phenomenon that the display area between adjacent gate drivers is uneven due to excessive glass trace impedance can be avoided in the prior art. Although the present invention has been disclosed above in the preferred embodiment, It is not intended to limit the invention, and any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. [Definition of the drawing] 21 200839704 F06I063SEZ1TW 23517twf.doc/n FIG. 1 is a circuit diagram of a wide viewing angle according to the conventional art, and FIG. 2 is a driving circuit diagram according to the conventional art. 3 is a circuit diagram of a pixel according to a first embodiment of the present invention. FIG. 4 is an equivalent circuit diagram of a display panel according to a second embodiment of the present invention. Figure 5 is a signal waveform diagram according to Figure 4. Figure 6 is a circuit diagram of a pixel device in accordance with a third embodiment of the present invention. Fig. 7 is an equivalent diagram of a display panel according to a fourth embodiment of the present invention. Fig. 8 is a signal waveform diagram according to Fig. 7. Road map. Figure 10 is a signal waveform diagram according to Figure 9. Fig. 11 is a diagram showing a kneading driving voltage according to the present embodiment. [Main component symbol description] VST Bu VST2: Coupling voltage VST: Reference electric VCOM: Common voltage DL1 to DL4: Data line SL1, SL2: Scanning line SDL1: First sub data line SDL2: Second sub data line SSL1 first Sub-scanning line SSL2 second sub-scanning line SV1: first sub-segment voltage SV2: second sub-single voltage CL1, CL2: liquid crystal capacitor 22 200839704 P061063SEZ1TW 23517twf.doc/n CSTH, CST2: compensation capacitor R1, R2, R3 : Resistor Μ 1 , M2 , SMI , SM2 : Transistor ΔV : Voltage adjustment value SW1 , SW2 : Switching signal F (N): Nth face F (N+1): N+1th face T1T2 Scan line time 110, 120, 1110~1140: sub-cells 210, 220: gate driver 300: pixel circuits 310, 410, 610, 710, 730: first sub-cells 320, 420, 620, 720, 740: second sub-pixel 400: display panels 401 to 403, 701 to 703: pixels 430, 750: third sub-salm 10 440, 760: fourth sub-element 600: pixel circuit 700: display panel 23