TW200839522A - Method for dynamically arranging interrupt pins - Google Patents

Abstract

A method for dynamically arranging interrupt pins is provided. The present method is used for arranging a plurality of interrupt pins of a control chip. In the present method, a number of interrupts sent from each of a plurality of device paths in a unit time is detected. These device paths are sorted according to the interrupt numbers thereof. Then, from the one in the head of the sequence, the devices paths are arranged to the interrupt pins. Herein, when arranging a device path, an interrupt checking number required to check the device path sending the interrupt every time an interrupt is produced in each interrupt pin is calculated. Then, when arranging the next device path, the device path is arranged to the interrupt pin with least interrupt checking number.

Description

200839522 IFDUVUUIUTW 23276twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a routing method, and relates to a method for dynamically allocating interrupt pins. [Prior Art] Intermp ReqUest (IRQ) is used to notify and request the processor to suspend work = set to perform the corresponding calculation action when a certain action is performed. The transmission of this interrupt request is through the "two lines, the line", and the number of these lines will be different depending on the motherboard controller. Traditional computers use the Programmable Interrupt Controller (PIC), which includes broken wires. However, these interrupt lines are still too small for the function of the computer, and most of the computer equipment will be occupied, and even multiple hardware devices must be shared. According to this,; _ some new motherboards with advanced programmable towel off control (Yang _ 2 d imaginary morphmable Interrupt Ccmtmllei, APIC) 'This interrupt controller can be managed - like 24 requests (For example, built in café: and ESB2 series l〇APIC, but some of them are used for Message Signal lnterrupt), but can provide a larger number of hardware devices, and there will be less The situation in which the disconnection is shared. If a PIC motherboard is used, usually only four interrupt lines are available for the PCI bus; on the other hand, if the APIC's new host board is used, there are 8 interrupt lines available. This means that even if there are 6 PCI slots on the motherboard, they must barely use 4 or 8 IRQs. In addition, Figure 5 200839522 IFUU/uuiurw 23276twf.doc/Accelerated Graphics Port (AGP), Universal Serial Bus (USB), Redundant Array of Independent Disks (RAID) IRQ is also required for controllers and '~ some Local Area Network (LAN) interfaces, 1394 interfaces, and SATA (Serial) interfaces. In this case, the case where multiple PCI slots share an IRQ is unavoidable. Figure 1 shows the hardware configuration of the conventional PIC/IOAPIC motherboard f). Referring to FIG. 1, a conventional nc motherboard is provided with a central processing unit 110, a north bridge wafer 120, a south bridge wafer 130, and four PCI slots 140, 150, 160, and 170. Among them, PCI slots 140, 150, 160 and 170 respectively transmit 4 interrupt messages (interrUpt message) INTA/INTB/INTC/INTD to the interrupt routing register Rx-A on the north bridge chip 120. Rx B, Rx C and

Rx-D (x=l, 2, 3, 4). Since the nC motherboard only supports 4 irqs, when the north bridge chip 120 actually transmits an interrupt message to the south bridge chip i3, the PCI slots 140, 150, 160, and 170 share four interrupt lines to issue an interrupt. . The south bridge chip 130 receives the interrupt message transmitted by the north bridge chip 120 by four interrupt router registers RA, RB, RC and RD, respectively. These interrupt messages are then sent to a programmable interrupt controller (8259 pic), and the 8259 PIC makes an interrupt request to the central processing unit ho. It is worth mentioning that the conventional IOAPIC motherboard has an advanced programmable interrupt controller (I0Anc) than the pjc motherboard, and the 8259 ioapic requests interrupts to the central processing unit no. 6

FIG. 2 is a diagram showing a wiring configuration table of a conventional interrupt pin. Please see Zhao 2, in which each PCI slot pin A, B, C, 〇 is two 'two; interrupt message iNTA/iNTB/mTC/mTD, and the basic input/output system (Basic Input/Output System) , BIOS) will also correspond to different intercoms when performing Power-On Self Test (POST): INTAANTBANTC/mTD, configure the interrupt request used/shared. For example, the pin of slot #2 A, B, C, and D are mapped to the medium & INTD/INTA/INTB/INTC. Therefore, when configuring the interrupt request, it is also in the order, in the corresponding interrupt wiring registers R2_a, R2_B, R2 C o

Uneven situation 'so the conventional technology is still not the best distribution method [invention content] 200839522 IFDU/UUIUTW 23276twf.doc/n and R2JD store the number 4 small 2, 3 in order to separate the I pin Apic pin 1 , 2, 3 trigger interrupt request. - If each of the four PCI slots is plugged into a ρα interface card, and each PCI interface card needs to trigger four interrupts from the interrupt pins i, 2, 3, and 4 respectively, then each The number of hardware devices shared by the I〇Apic interrupt line is 4, and the hardware drivers for serial connection in these 4 lines are also 4 pieces. It can be seen from this that in this case, each IOAPIC towel is uniformly the same (four), and it is optimized. The above method is to configure the PCI slot based on the fact that the frequency of the pci device configured on each pc]^^ slot is not much different, however, in practical applications, each different ρα device is in the unit. The number of interrupts issued during the time is different, that is, a certain device (4) is busy, and some PCI devices are relatively idle. This hiding still causes emotional pin assignments 7 o

G 200839522 IPD070U10 TW 23276twf. doc/n In view of the above, it is an object of the present invention to provide a method of disconnecting a pin according to the path of the frequency interrupting device on each interrupt pin to reduce the occurrence of each interrupt. , to determine the number of checks required by the program. For the above or other purposes, the present invention provides a motion:::: a plurality of interrupt pins adapted to be allocated-controlled, the method t includes the following steps: First, detecting a plurality of devices in a unit time is static The number of times, then according to the path of each device; the number 'for these device paths to make money, and then the green device path begins, in order to install these, in the month j two 'to each of the interrupt pins on each Generated —: The number of checks required to interrupt the shirt path is the lowest. 4 out of this = in one embodiment of the present invention, the steps of assigning the device paths to the = feet include: according to the path of each device; each time an interrupt is generated on an interrupt pin, the check is performed. The number of times 'when the next device path is assigned, after the path is set, the number of interrupt checks required for each of the interrupt pins is selected. Finally, the device is configured to match the interrupt pin with the least number of interrupt checks. ^Inventive - In the embodiment, the manner in which the interrupted device path is checked is checked by a driver corresponding to the hardware device configured on each device path. 8 200839522 IFDU7UUWTW 23276twf.d〇c/n The number of steps includes the order of the installation path assigned to each interrupt pin, the latest addition of the towel to the lion ^ and then the axis _ set the road := Heavy 'Sub-calculation results are added to the number of cap inspections. In the case of the foot l· month t, after the distribution of the skirting path to the interrupted access, the program includes the (four) program of the hard county set in the order of the above devices. Includes interface card. In an embodiment of the present invention, the manner of detecting the number of interruptions occurring on a plurality of device paths per unit time is detected by a driver corresponding to the hardware device configured on each device path, and the device paths and Among the eight correspondences, the number of people is then recorded in the memory. This memory includes non-volatile_access memory (NGn_VGlatile RandGm Ac(10)

Memory, NVRAM). In an embodiment of the present invention, the interrupt pin includes a connection to a (4) 1 control state (pr〇grammabie shirt tc〇ntr〇ner, pic) and an input and output advanced programmable interrupt controller ( I/〇Advanced

One of the Programmable Interrupt Controllers, 10APIC), and the control chip described above includes one of a Northbridge wafer and a Southbridge wafer. In one embodiment of the invention, the manner in which the device paths are ordered is ordered from large to small, depending on the number of interruptions occurring on each device path. 200839522 IPDUIOOWTW 23276twfdoc/n jin This invention uses each hardware device to calculate the frequency of interruptions on each interrupt pin to move ~', earth foundation, ^_heterogeneous, and according to the material_路^=力1城On the eve of the interruption of the mother, the number of inspections required was issued. The above and other objects and materials of the present invention are as follows. The port of the I port is described in detail. [Embodiment] y allows the allocation of the interrupt pin to be optimized. In the process of performing the self-test in the BI0S, that is, the number of times the device has issued an interrupt, Control =, and make the mother-in-law hang on the ί:= reduction in every time an interruption occurs, the driver is looking for the following 'the following _ real _ for the forest thorn bamboo can _ to implement the ^ month The pedal 3 is a method flow® of dynamically assigning an interrupt = according to an embodiment of the present invention. Please refer to 3, the actual _ is suitable for allocating one: a plurality of interrupt pins of the wafer, the control chip is, for example, a north bridge chip or a south bridge chip, and the interrupt pins are, for example, connected to the programmable interrupt controller ( Programmable Interrupt Controller, pIC) or output and output advanced programmable interrupt controller (I/0 Adva=2

Programmable Interrupt Controller, IOAI>IC). 200839522 irjJU/uuiufW 23276twf.doc/n First, the number of interruptions occurring on a plurality of device paths is measured in one unit time (step S310). The number of interrupts is obtained by the driver of the hardware device configured on each device path, and the driver will count the number of interrupts issued by the driver during the unit time, and the corresponding number is interrupted. PCI device/function address (PFA), device path (generalized device path including PCI device/function address), and number of interrupts are returned to the operating system' and all drivers are collected by the operating system. After the data returned by the program, the summary is recorded as an interrupt occurrence record in the memory of the system. The hardware device is, for example, an interface card, and the memory is, for example, a Non-Volatile Random Access Memory (NVRAM), without limiting its scope. Fig. 4 is a table showing an interrupt occurrence record in accordance with one embodiment of the present invention. Referring to Fig. 4, the first section describes the device path (DP), and the second section describes the number of interrupts generated by the respective device paths. Next, the "device paths" are sorted based on the number of interruptions occurring on the respective device paths (step S320). Among them, the sorting method is, for example, sorting from large to small, so as to facilitate the subsequent arrangement of the interrupt pin. FIG. 5 is a sorted interrupt occurrence record table according to an embodiment of the invention. As shown in Figure 5, in all device paths, an interruption occurs - the highest number of people is 500 times of DP3; and the least is 1〇 of DP〇. Finally, it is possible to start by sorting the preceding device path, and sequentially assign each device path to the interrupt pin so that each interrupt pin generates a each time 11 200839522 ljt^uu/uuiurw 23276twf.doc/n Check the number of interrupt checks required to issue the interrupted split path to a minimum of 1 This step involves first calculating the each interrupt pin on each interrupt pin to check which one is based on the number of interrupts of the previously recorded device path. The number of interrupt checks required for the device path to issue an interrupt (step S330), and based on the number of interrupt checks currently calculated by each interrupt pin, when the device is equipped with a device path, the device path is first inserted into the device path. In each of the pins, and after calculating the path of joining the device, each time an interrupt is generated on each interrupt pin, the interrupt required for the device path for interrupting is checked, the number of times is checked (step S340), and finally the selection is made. The device path is assigned to the interrupt pin with the least number of inspections (step S350). Next, it is determined whether all the device paths have been allocated (step S360). If the allocation is completed, then returning to step S330, continue to calculate the number of interruption checks required in each of the current internal check pins, and assign the next device path. Otherwise, if all the device paths have been allocated, the process ends. The step of dynamically allocating interrupt pins in this embodiment. ^ 士 = It is to be noted that this embodiment calculates the number of interrupt checks described above, and also includes establishing a sequence for the device paths assigned to the respective interrupt pins. This sequence can be via the advanced architecture power interface (Advanced)

Configuration and Power Interface (ACPI) specifies the advanced rack = power "face source language (ACpIS 〇 urceLanguage, asl) code is returned to the system" and is used to cascade the hardware devices configured on each device path to reduce At that time, check the number of interrupt checks that are required when the driver is issued. 12 200839522 iPDOVOUlUfW 23276twf.doc/n The procedure of 'the tree iL order is to put the most device roads in order, and in; Multiply the number of times of adding a device path by multiplying the query 4, that is, adding the products to obtain the final number of interrupt checks. & For example, it is assumed that 'the current system interrupt pin has 4 maps. The interrupt occurrence record table shown in 5 is based on the interrupt pin. At first, the four interrupt pins are not detailed: Γ: These are naturally natural ways to invade the front 4 At the time, 'there are 4 sets of each interrupt pin', so the number of times of each device path is calculated as the interrupt check. The number of interrupt checks is as follows. One in

Checkcount[l]-500

Checkcount[2]=130

Checkcount[3]=l〇〇

Checkcount[4]=70 On the other interrupt pins, the interrupt detection of the 4th interrupt pin is the least. Accordingly, the next step is to prioritize the device path to the 4th interrupt pin and recalculate the number of interrupt checks for the 4th interrupt pin. The calculation step includes first sorting the driver corresponding to the newly added device path DP7 before the device path Dp5, and then calculating the number of interrupt checks of the fourth interrupt pin, and after allocating the device path DP5, each interrupt pin The total number of interrupt checks is as follows: Checkcount[ 1 ]=5 00 13 200839522 jjtjl/u /uwiuTW 23276twf.doc/n

Checkcount[2]=130

Checkcount[3]=l 〇〇

Checkcount[4]=70+60*2=190 Among them, since the device path DP7 is sorted after, if the middle path DP7 sends (4) 'the money is checked in the check, the device first checks the sorted device path DP5 first. If it is found that the interruption is not issued by the device path DP5, it will be checked again whether it is issued by the device path 〇DP7. Therefore, in actual calculation of the number of interruption inspections, it is necessary to add the number of interruption inspections required to inspect the apparatus path DP7 7 times to the number of interruption inspections required to inspect the apparatus path DP5 6〇+6 times, and obtain the total interruption. The number of inspections was 190 times. According to the above principle, when the next device path Dp# is assigned, the third cultivating pin assigned to the least number of uranium interruption inspections (1 〇〇) can be selected, and the third interrupt pin is calculated. The number of interrupt checks, and after the device path DP4 is allocated, the total number of interrupt checks for each interrupt pin is as follows: ' Checkcount [ 1 ]=5 00

Checkcount[2]=l 30

Checkcount[3]=l 00+50*2=200

Checkcount[4]= 70+60*2=190 and so on, the remaining device paths are successively assigned to the interrupt pins with the least number of interrupt checks, and one or more interrupt pins can be connected in series with 2 or more. The device path does not limit its scope. Finally, the total number of interrupt checks for each interrupt pin is as follows. 14 23276twf.doc/n 200839522

XX JLyyj / uw 1 \J TW

Checkcount [ 1 ]=500 Checkcount[2]=l 30+40*2=210 Checkcount[3]=l 00+50*2+10*3=230 Checkcount[4]= 70+60*2+30*3 =280 The final allocation result and the number of interrupt checks for each interrupt pin are shown in Figure 6. Please refer to FIG. 6 'the total number of interruptions originally issued by each device path is 500+130+100+70+60+50+40+30+10=990 times, in the dynamic allocation interrupt pin via the present embodiment. After the method is allocated, only 500+210+230+280=1220 times of interrupt check times can be used to check whether the interrupt is issued by its own hardware device. According to this, the optimization of the interrupt pin assignment can be achieved. According to the above description, the method for dynamically allocating interrupt pins of the present invention has at least the following advantages:

1. According to the number of possible breaks in each county, the devices are all purely pure to the cap pins, which can effectively reduce the number of interrupts that are generated by which driver is generated when it occurs. Check the second time. Sort the device paths assigned to the same ploughing pin and use them for the driver. Therefore, (4) reduce the number of interrupt checks required to find the driver in the single-disconnect pin. x Although the present invention has been disclosed in the preferred embodiments as above, the iron defines the present invention, and any person skilled in the art can make some changes and refinements in the invention and the target area, so: This is subject to the definition of the scope of the patent application. x 呆& 15 200839522 iruKj/\jvLv£W 23276twf.doc/n [Simplified Schematic] Figure ί shows the hardware configuration of the conventional PIC/IOAPIC motherboard. FIG. 2 is a diagram showing a wiring configuration table of a conventional disconnecting leg. Figure ‘Assignment Interruption Figure 3 is a flow chart of a method of a splicing pin in accordance with an embodiment of the present invention. Figure 4 is a diagram showing an interrupt occurrence record in accordance with an embodiment of the present invention. a

o Figure 5 is a list of sorted interrupt occurrence records in accordance with an embodiment of the present invention. Figure 6 is a diagram showing the results of the assignment of interrupt pins in accordance with an embodiment of the present invention. [Main component symbol description] 110: central processing unit 120: north bridge wafer 130: south bridge wafer 140, 150, 160, 170: PCI slots S310 to S360: each of the methods for dynamically allocating interrupt pins in accordance with a preferred embodiment of the present invention Step 16

Claims (1)

200839522TW 23276twf.doc/n X. Patent Application Range: A method for dynamically allocating interrupt pins, suitable for allocating a plurality of interrupt pins of a slice, the method comprising the following steps: [Measurement - on multiple device paths in the early time period Occurred—the medium control crystal number is sorted according to the path of the number of financial occurrences occurring on each of the wires i path; and Γ starting from the device path that is sorted first, sequentially cutting the device paths, and some interrupts are connected The number of times required to check the path of the device that issued the interrupt is minimized on the foot so that each interrupt is generated on each of the interrupt pins. ^ -, 2 · The method of dynamically allocating interrupt pins as described in claim 1 of the patent application, wherein the steps of assigning the device paths to the interrupt pins are included in the package The number of interruptions of the device paths, the number of times the interrupt check is detected for each device path that issues the interrupt when each interrupt is generated on each of the interrupt pins; when the next device path is allocated, the device is first The path is added to each of the interrupt pins, and the number of interrupt checks required to check the path of the device that issued the interrupt is detected each time the interrupt is generated after joining the device path, respectively; The device path is assigned to the interrupt pin with the least number of interrupt checks. 17 200839522 rw 23276twf.doc/n 3. A method for dynamically allocating interrupt pins as described in claim 2, wherein the device that issues the interrupt is checked each time the interrupt is generated on each of the interrupt pins The step of the number of interrupt checks required by the path includes: establishing an order for each of the device paths allocated to each of the interrupt pins, wherein the device path that newly joins the interrupt pins is sorted backward; The sequence multiplies the number of interruptions of each of the device paths by a specific gravity, and adds the calculation results to obtain the number of interruption inspections. 4. The method of dynamically allocating interrupt pins as described in claim 2, wherein the number of interrupt checks required to check the path of the device that issued the interrupt is transmitted through a path corresponding to each of the device paths. A driver for a hardware device to check. 5. The method of dynamically allocating interrupt pins according to claim 4, wherein after the step of assigning the device paths to the interrupt pins, the method further comprises: serially connecting the plurality of the devices according to the sequence. The driver of the hardware device configured on the device path. 6. The method of dynamically allocating interrupt pins as described in claim 4, wherein the hardware devices comprise interface cards. 7. The method of dynamically allocating interrupt pins according to claim 1, wherein detecting the number of interrupts occurring on the plurality of device paths in the unit time is configured by corresponding to each of the device paths A driver of a hardware device detects it. The method for dynamically allocating interrupt pins according to claim 1, wherein after detecting the number of interruptions occurring on the plurality of device paths in the unit time, the step is further The method includes: recording the device paths and the corresponding number of interruptions in a memory. 9. The method of dynamically allocating interrupt pins as described in claim 8 wherein the memory comprises a Non-Volatile Random Access Memory (NVRAM). 10. The method of dynamically allocating interrupt pins as described in claim 1, wherein the interrupt pins comprise a Programmable Interrupt Controller (PIC) and an Input/Output Advanced " One of the T/I Advanced Programmable Interrupt Controller (IOAPIC). u. The method for dynamically allocating interrupt pins according to claim 1 of the patent application, wherein the manner in which the device paths are sorted according to the number of times the devices are interrupted, includes a large to small Sort. 12. The method of dynamically allocating interrupt pins as described in the application patent (4), wherein the control chip comprises a north bridge and a south bridge (9).