TW200838295A - Solid-state imaging apparatus - Google Patents

Abstract

To provide an inexpensive solid-state imaging apparatus the downsizing of which can be attained and the dynamic range of each of a plurality of pixel sections of which can be extended. The solid-state imaging apparatus 1 includes: a light receiving section 11; a first hold section 21; a second hold section 22; an output selection section 31; an AD conversion section 40; a bias section 50; and a control section 61. The first hold section 21 holds a voltage V1m ,n in response to the amount of electric charges generated by photodiodes of pixel sections Pm, n of m-th row of the light receiving section 11 in response to the light incidence over a first period, and a second hold section 22 holds a voltage V2m, n in response to the amount of electric charges generated by photodiodes of pixel sections Pm, n of the m-th row in response to the light incidence over a second period shorter than the first period. An output selection section 31 selectively outputs the V1m, n when the V1 m, n is less than a reference voltage Vsat or selectively outputs the V2m, n when not.

Description

[Technical Field] The present invention relates to a solid-state imaging device including a light-sensing portion (light-receiving portion: imaging region). The light-sensing portion includes charges each having an amount corresponding to the amount of incident light. The photodiode and the pixel portion arranged in two dimensions. [First as technology]

The solid-state imaging device includes a light-sensing portion including a plurality of pixel portions arranged in two dimensions, and each of the pixel portions has a photodiode that generates an electric charge corresponding to the amount of incident light. In the solid-state imaging device described above, it is required to increase the dynamic range, and the invention for realizing this requirement is disclosed, for example, in Patent Document 1. In the solid-state imaging device disclosed in Patent Document 1, the light is incident on the photodiode of all the pixel portions included in the photo-sensing portion, and the voltage corresponding to the amount of the electric charge is obtained. The voltage (analog value) is converted into a digital value, and the digital value is memorized in the frame memory. Then, in response to light incident for a longer period including the above period, a voltage corresponding to the amount of the electric charge is generated by the photodiode of each of the pixel portions included in the photo-sensing portion. Further, regarding the plurality of pixel portions, if the amount of incident light is relatively small and the voltage of the latter is not saturated, the voltage of the latter is selected. On the other hand, if the amount of incident light is relatively large and the voltage of the latter is saturated, the memory is selected to be framed. The value of the former in the memory. Thus, the plurality of pixel portions are respectively expanded in the dynamic range. Patent Document 1: Japanese Patent Publication No. 2,966,977 [Patent Document] 119054.doc 200838295 Problem to be Solved by the Invention However, the solid-state imaging device disclosed in the above document requires a frame memory, which results in an increase in size and cost. The present invention has been developed to solve the above problems, and an object of the invention is to provide a solid-state imaging device which can expand a dynamic range by a plurality of pixel portions, can be downsized, and is inexpensive. Technical means of solving problems

A solid-state imaging device according to the present invention includes: (1) a photosensitive portion including pixel portions P1) 1 to PMN, wherein the pixel portions ,ι, 广 Pm, n each have an amount of electric charge corresponding to an amount of incident light. The photodiode is arranged in a two-dimensional array, and (2) a first holding portion that holds and outputs the pixel portion Pc of any one of the m-th columns of the light-sensing portion. The voltage corresponding to the amount of charge generated by the respective photodiodes is used as a voltage '^' (7): the holding portion' holds and outputs n pixel portions Pm>1 of any of the light-sensing portions. The amount of charge generated by each of the photodiodes of Pm'N corresponds to a voltage of V2ml to V2mN; (4) an output selection unit that inputs N electric M Vlm i to vlm N output from the first holding unit and 2 N voltages V2m l V2m N outputted by the holding portion, and comparing the voltage νι^ with the reference voltage v as the magnitude, outputting a signal indicating the comparison result, and 'selective output voltage I when the voltage Vlmn is smaller than the reference voltage Vsat Otherwise, the voltages V2m, n, and (5) are controlled to control the respective operations of the light sensing unit, the first holding: the second holding unit, and the output selecting unit. Further, it is preferable that The iso-optical sensing unit, the i-th holding unit, the second holding unit, and the output selecting unit are formed monolithically on the common substrate. Among them, M and n are integers of 2 or more, and H9054.doc 200838295 is 1 or more or less. Integer, number. η is 1 or more Ν any of the following, further The solid column of the Ming Dynasty is in the first column of the 邙 〜 〜 置 置 置 置 置 置 置 置 控制 控制 控制 控制 控制 控制 控制 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第The photoelectricity of each pixel portion Pmn of the column: the voltage corresponding to the pole body is generated as the voltage Vlm,n, and after the J-th holding portion, the image of the m-th column, ^p, ...', the temple' is the first Period μ m, n (four), after the initialization, corresponding to the shorter than the above-mentioned first period of the third 傻 傻 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 2 2 2 2 2 2 The voltage of the V9 second outer cliff is the corresponding voltage: Γ ^ 'The maintenance of the second brother is held by the second holding unit, and the part held by the second holding unit is the part that is held by the second holding unit, and From the output selection unit selection "...Input/output selection V2, selection (4) selective output power vlm, "t power generation v zm, n ° In the solid-state imaging device of the present invention, ^ each column sequentially performs the following - λ induction #中之弟1列～第Μ 仃 仃 仃 仃 仃 仃 仃 仃 。 。 似 似 似 似 似 似 似 似 似 似 似 似 似 似 似 似 似 似 似 似 似 似 似 似For each pixel, the voltage corresponding to the Thunder generated by the photodiode of 卩Pm,n is used as the lightning voltage v, and is held by the first holding portion. The first _ ^ is Γ each pixel portion pTM '"Initialization. After the initialization, the light of the second period of the first period is made = _ is the electric IV2mn, and the voltage corresponding to the amount of charge generated by the two bodies is held by the holding portion of the second body. The voltage V1 bp is controlled by the holding unit m, and the voltage V2 ^ X held by the n-part 2 holding unit is selected from the rim, and the 縻V2m, n input wheel V2. In 4, select #selective output voltage vwt electric magic m, n in the round selection part, + _ flat ^ ^ with I 肀, compare voltage ^ ^ and reference voltage 119054.doc 200838295

The size of Vsat, the output indicates the signal of the comparison result, and the voltage

Vlm, when n is less than the reference voltage Vsat, selectively outputs a voltage, otherwise the selective turn-off voltage V2m,n. Further, another solid-state imaging device according to the present invention is characterized in that: (" photosensor" includes pixel portions Ρ1 to N, each of which has a photodiode that generates an amount of electric charge corresponding to the amount of incident light. a body ', and a two-dimensional array of columns; (2) a first holding portion that holds and outputs a photodiode of each of the N pixel portions of the m-th column of the photo-sensing portion The voltage corresponding to the amount of charge generated is a voltage to a wide range. (3) The second holding portion holds and outputs the photoelectricity of each of the N pixel portions Pmi to PmN of any mth column of the light sensing portion. The electric charge corresponding to the amount of charge generated by the diode is (V) is the voltage V2m i~V2m N ; (4) the third holding portion holds and outputs the N pixel portions Pm'^ of any mth column in the photo sensing portion. The voltage corresponding to the amount of charge generated by each of the photodiodes of Pm'N is two s: V3W V3m, N, and (5) output selection portions, and the input is output from the first holding portion or the second holding portion. M vim i~vim N or N voltages V2nU to V2m, N, and N voltages V3m fVL n output from the third holding portion, And comparing the voltage Vlm, n or the voltage V2m i ~ V2m - the reference power 22 size ' and outputting a signal indicating the comparison result, and when the voltage Vlmn or V2m, n is less than the reference voltage, the selective output voltage π (10) or V2m'n' otherwise selectively outputs a voltage π"; and (6) a control unit that controls light sensing. The operation of each of the P f 1 holding portion, the second holding portion, the first holding portion, and the output selecting portion. The optical sensing unit, the second holding unit, the second holding unit, the 篦 μ 立 μ 邛 邛 and the output selection unit are formed monolithically on the common substrate of 119054.doc 200838295. The control unit includes light sensing: the column 4_ and the column sequence: the voltage corresponding to the photodiode of each pixel portion Pm,n of the mth column is made to be the electric house vim. , n or the voltage V2mn is alternately held by the first holding portion or the second holding portion, and after the i-th period,

Pm,n is initialized, and each of the pixel portions after the initialization corresponds to a light amount that is shorter than the second period of the first period, and corresponds to the amount of charge generated by the photodiode of each of the pixel portions. The voltage is the voltage V, and is maintained by the third holding unit, and the electric power, the V3 ... the selective wheel held by the second holding portion held by the second holding portion or the second holding portion. (4), or electric (four) m, n, vjm, n ° In the solid-state imaging device of the present invention, the column is sequentially subjected to the following steps: the first column to the Mth column, and the disk is made to correspond to the light of the first period. The voltage corresponding to the photodiode of each pixel portion pm of the column m is incident as the voltage V1, and the king's electric Heli 2 holding portion alternates 佯# ιΓ1,"' from the first holding portion or the ρ initial After that, "the column of each pixel will be

Cl: shot:: start == by the first; each pixel portion of the column. - Photodiode production and holding |~^ € Μ as voltage V3m, n ' is guaranteed by the third holding unit = 2, and is held by the first holding unit or the second holding unit. Keep the voltage v3 out, select the selective output voltage vim,n or voltage V2m 119054.doc 200838295 or voltage V3m,n. In the output selection unit, ':2- and the reference voltage (10), and the rotation indicates the comparison = voltage number, and the signal selective output voltage K voltage V2 'n / quasi-voltage at the voltage Vlmn or the voltage V2m ^ Vsat 'v, m'n secondary [V2m, n, otherwise selective output voltage

Further, in the operation of the solid-state imaging device of the present invention, the __ portion can be repeated between the $column period and the other (fourth) of the other column. Further, the first period of a certain column and the second period of another column may be overlapped with each other. Furthermore, the second period of a certain column may also be part of the i-th period of another column. L is a speed at which the speed of the implementation is increased. It is preferable that some or all of these are repeated with each other. Moreover, the present invention can also be applied in the case of an APS (ACtive Pixel Sensor) method and a (Passive Pixei Sensor) method. Advantageous Effects of Invention The solid-state imaging device of the present invention can be miniaturized and inexpensive. [Embodiment] Hereinafter, the best mode for carrying out the invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same components are denoted by the same reference numerals, and the description thereof will not be repeated. (First Embodiment) First, a first embodiment of a solid-state imaging device according to the present invention will be described. Fig. 1 is a schematic configuration diagram of a solid-state imaging device 1 according to the first embodiment. The solid-state imaging device 1 shown in the figure is an APS system, and includes a light sensing unit 119054.doc -10- 200838295 11 , a first holding unit 21 , a second holding unit 22 , an output selecting unit 31 , an octagonal conversion unit 40 , and The biasing unit 5 and the control unit 61. Preferably, the monoliths are formed on the common substrate SB. In this case, one of the arrangements on the substrate, for example, as shown in the figure, includes a pixel portion of the APS method in which two rows are arranged in a row of N rows. Ρι, ι 〜 Pm, n ° Each pixel portion Pm n has a photodiode that generates an amount of electric charge corresponding to the amount of incident light. Here, Μ, N is an integer of 2 or more, and m is 1

Any of the following integers, η is an integer of 1 or more and N or less. The first holding portion 21 receives a voltage corresponding to the amount of electric charge generated by each of the photodiodes of each of the pixel portions to PmN in any mth column of the photo sensing portion 11, and uses the voltage as the voltage vlmi~ Vlm, N keeps and outputs. Similarly, the second holding unit 22 is input to the light sensing unit! The voltage corresponding to the amount of charge generated by the photodiode of each of the N pixel portions Pmi to PmN in any mth column of j is held and output as the voltage V2m, V2m, N. The output selection unit 31 inputs N voltages output from the first holding unit 21, and also inputs ν voltages V2W to V2m, N output from the second holding unit 22. Further, the output selection unit 31 compares the magnitudes of the voltage νι_ and the reference voltage Vsat, and outputs a mode-out signal indicating that the comparison result thereof, and the field voltage Vlm,n does not reach the reference voltage Vsat, and the selective output voltage Vlm,n When the voltage Vlm,n reaches the reference voltage v, the voltage V2m,n is selectively rotated. The AD conversion .p 40 inputs the voltage output from the output selection unit 31, converts the talk voltage (analog value) into a digital value, and outputs the digital value video 119054.doc 200838295 The biasing portion 50 is output to the light sensing portion 11, The selection unit 3 and the ad conversion unit 4 are supplied with reference voltages. The control unit 61 generates and outputs a control unit 61 for controlling the light sensing unit jj, the first holding unit 21, the second holding unit 22, and the output selecting unit 31 & AD converting unit 4 based on the external input (^[foot signal and ST signal]. The control signals of the respective actions include logic circuits such as shift registers.

Fig. 2 is a view showing the configuration of the light sensing unit 11, the first holding unit 21, and the second holding unit 22 included in the solid-state imaging device according to the first embodiment. In the light sensing portion u, two pixel portions pi" to n having a common structure are arranged in two dimensions, and the pixel portions Pm, n are located in the Nth row of the third row. The first holding unit 21 includes N holding circuits Hi, ! Hu. Further, the second holding unit 22 includes a holding circuit. N holding circuits Ηι ι~仏, and the N holding circuits have a common structure. ''the output end of each of the pixel portions of the nth row included in the light sensing portion 11, the holding circuit included in the i-th holding portion 21, the input terminal, and the holding circuit included in the second holding portion 22 The terminals are connected by the common wiring (4). The output terminals of the holding circuits 1 to I included in the first holding portion 21 are connected by a common wiring. Further, the N holding circuits included in the holding portion 22 are provided. The common wiring is connected to each other by a pixel portion included in the solid-state imaging device μ of the wide-area embodiment: a pixel ΓΗι, η, and a circuit diagram of the holding circuit Η2, η.卩Pm,n contains the photodiode PD and four electric=Τ4Ή's as shown in the figure 'Cell crystal 1, transistor T2 and photo-electrode-PD are connected in series, and the self-bias t reference voltage Vbl is input to 119054.doc - 12- 200838295 The anode terminal of the crystal T1 is grounded to the anode terminal of the photodiode PD. The transistor T3 and the transistor T4 are connected in series, and the reference voltage Vb2 supplied from the bias unit 50 is input to the terminal of the transistor T3, and the source terminal of the transistor T4 is connected to the wiring Vline(n). The junction of the transistor T1 and the transistor T2 is connected to the gate terminal of the transistor T3. Also, a constant current source is connected to the wiring Vline(n).

The gate terminal of the Vreset (m) signal input transistor T1 supplied from the control unit 61, the gate terminal of the Vtrans (m) signal input transistor T2 supplied from the control unit 61, and the Vaddress (m) supplied from the control unit 61. The signal is input to the gate terminal of the transistor T4. The Vreset (m) signal, the Vtrans (m) signal, and the Vaddress (m) signal are commonly input to the N pixel portions Pm, i to Pm, N 0 Vreset (m) signal and Vtrans (m) signal of the mth column. When the high level is on time, the junction capacitance portion of the photodiode PD is discharged. When the Vaddress(m) signal is at a high level in the discharged state, the noise component is output from the pixel portion Pm,n to the wiring Vline(n). When the Vreset (m) signal is at a low level, and the Vtrans (m) signal and the Vaddress (m) signal are at a high level, the voltage corresponding to the amount of charge stored in the junction capacitance portion of the photodiode PD is used as a signal component to be wired. Vline(n) output. Each of the first holding portions 21 includes a holding circuit H!, n including two capacitor elements Cl, C2, and four switches SW11, SW12, SW21, and SW22. In the holding circuit Η!, η, the switch SW11 and the switch SW12 are connected in series, and are disposed between the wiring Vline(n) and the wiring Hline_sl, and one end of the capacitive element C1 is connected to a connection point between the switch SW11 and the switch SW12, and the capacitive element C1 The other end is grounded. Further, the switch SW21 and the switch SW22 are connected in series and are provided in the wiring 119054.doc •13·200838295

Between Vline(n) and wiring Hline-nl, one end of the capacitive element C2 is connected to the connection point between the switch SW21 and the switch SW22, and the other end of the capacitive element C2 is grounded. In the holding circuit, the switch SW11 is switched in accordance with the level of the set-si signal supplied from the control unit 61. The switch SW21 is switched in accordance with the level of the set-n1 signal supplied from the control unit 61. The set_s1 signal and the set "" signal are commonly input to the N holding circuits included in the first holding unit 21. The switches SW12 and SW22 are switched in accordance with the level of the hshiht (4) signal supplied from the control unit 61. The holding circuit Hu When the set-nl signal is shifted from the high level to the low level, the noise component output from the pixel portion Pm, n to the wiring Vline(n) is thereafter held as the voltage out_nl(n) by the capacitive element C2. set_sl When the signal is shifted from the high level to the low level, the signal component output from the pixel portion pm n to the wiring vline(n) is thereafter held as the voltage out_sl(n) by the capacitive element C1. And, if the hshiht(n) signal becomes At a high level, the voltage out_sl(n) held by the capacitive element C1 is output to the wiring Hline-si, and the voltage 〇ut-nl(n) held by the capacitive element €2 is output to the wiring Hline-nl. The difference between the voltage 〇ut_sl(4) and the voltage out-nl(n) represents a voltage Vlm,n corresponding to the amount of charge generated by the photodiode pD of the pixel portion pmn. The second holding portion 22 includes respective holds. Circuits 112, 11 include two capacitive electrical components Cl, C2, and four switches swu, SW12 SW21, SW22. The holding circuit H2, nt, the switch swil and the switch SW12 are connected in series, and are disposed between the wiring Vline(n) and the wiring Hline_s2, and one end of the capacitive element 〇1 is connected to the connection between the switch swii and the switch SW12. Point, capacitor 119054.doc -14- 200838295 The other end of c 1 is grounded. In addition, the switch sW2 i and the switch sW22 are connected in series, and are disposed between the wiring Vline(n) and the wiring Hline-n2, and one end of the capacitive element C2 is connected. At the connection point between the switch SW21 and the switch SW22, the other end of the capacitive element C2 is grounded. In the holding circuit Hu, the switch SW1 is switched according to the level of the set_s2 signal supplied from the control unit 61. The switch sW2! The set-s2 signal and the set one are input to the N holding circuits included in the second holding unit 22 in common by the signal. The switches SW12 and SW22 are based on the self-control unit. 61 supply hshihtO) signal level and switch. In the holding circuit H2, n, set a n2 signal from the high level to the low level shift %, the noise component output from the pixel portion Pm, n to the wiring Vline (n) , after that as the voltage out a n2 (n) by electricity The capacitive element C2 is held. When the set-s2 signal is shifted from the high level to the low level, the signal component output from the pixel portion Pm n to the wiring VHne(n) is thereafter held by the capacitive element ci as the voltage out_s2(n). Further, if the hshiht(n) signal becomes a high level, the voltage 〇ut_s2(8) held by the capacitive element C1 is output to the wiring Hline-S2, and the voltage cmt"i2(n) held by the capacitive element C2 is wired. Hline-n2 output. The difference between the voltage out_S2(n) and the voltage out_n2(n) represents a voltage v2m n corresponding to the amount of charge generated by the photodiode PD of the pixel portion Pm n . Fig. 4 is a view showing the configuration of the output selecting unit 31 included in the solid-state imaging device J of the embodiment of the first embodiment. The output selection unit 31 includes a difference operation circuit, a differential operation circuit 312, a comparison circuit 313, a latch circuit 314, a logic inversion circuit 315, switches SW30 to SW32, and switches SW40 to SW42. 119054.doc -15- 200838295 The first input terminal of the difference calculation circuit 311 is connected to the wiring Hhne-S1 via a buffer amplifier, and is input to the self-holding circuit Η!, η is turned to the wiring Hline-si by the voltage out-sl(n ). The second input terminal of the difference arithmetic circuit 3 11 is connected to the wiring Hline-n1 via a buffer amplifier, and is input to the voltage out_ni(n) output from the holding circuit ^ι^ to the wiring Hline-n1. Further, the difference operation circuit 311 outputs a voltage Vim,n indicating the difference between the voltage 〇m_sl(n) and the voltage 〇utjQl(8). The first input terminal of the differential circuit 312 is connected to the wiring Hline_s2 via a buffer amplifier, and the voltage out_S2(n) output from the holding circuit Hu to the wiring Hline_S2 is input. The second input terminal of the difference arithmetic circuit 312 is connected to the wiring Hline-n2 via a buffer amplifier, and is input to the voltage 〇ut-n2(n) output from the holding circuit H2n to the wiring Hline-n2. Further, the difference operation circuit 312 outputs a voltage V2m,n indicating the difference between the voltages 0 plus 82 (11) and the voltages 〇 111: - 112 (11). The wiring Hline-si is grounded via the switch SW3 1, and the input voltage input to the first input terminal of the difference operation circuit 31 is initialized by turning off the switch SW31. The wiring Hline_n1 is grounded via the switch SW32, and the input voltage input to the second input terminal of the difference arithmetic circuit 311 is initialized by turning off the switch SW32. The wiring Hline_s2 is grounded via the switch SW41, and the input voltage input to the first input terminal of the difference arithmetic circuit 312 is initialized by closing the switch SW41. The wiring Hline_n2 is grounded via the switch SW42, and the input voltage input to the second input terminal of the difference arithmetic circuit 312 is initialized by turning off the switch SW42. The respective switching operations of the switches SW31, SW32, SW41, and SW42 are controlled by the hreset signal supplied from the control unit 119054.doc -16-200838295. The comparison circuit 313 compares the voltages Vlm,n output from the self-difference operation circuit 311 with the magnitude of the reference voltage Vsat, and outputs a mode_out signal indicating the comparison result. The latch circuit 314 inputs the mode_out signal that is rotated from the comparison circuit 3U, and turns the mode-out signal for a fixed time. The logic inverting circuit 315 inputs the output from the latch circuit 314, such as a signal, performs a logic inversion, and outputs the inverted signal. One end of the switch SW30 is connected to the output terminal of the difference operation circuit 311, and the switching operation is performed based on the mode-out signal output from the latch circuit 314. One end of the switch SW40 is connected to the output terminal of the difference operation circuit 312, and the switching operation is performed based on the signal (the inverted signal of the m〇de-0llt signal) output from the logic inverting circuit 3 15 . When one of the switch SW30 and the switch SW40 is in an open state, the other is in a closed state, and the other end of the switch SW3 is connected to the other end of the switch SW40, and the vide〇-a signal output from the connection point becomes a voltage Vlm. n and any of the voltages V2m, n. Therefore, the vide〇_a signal output from the output selecting unit 31 is the voltage Vlm n when the voltage vim,n does not reach the reference voltage Vsat, and is the voltage V2mn when the voltage νι_ reaches the reference voltage Vsat. Here, the reference voltage (10) is set to an appropriate value which is comparable to the comparison circuit 313 " The AD conversion unit 40 receives the vide〇-a signal output from the output selection unit 31, converts the voltage (analog value) of the signal into a digital value, and outputs the digital value video_data. Fig. 5 is a circuit diagram of the difference operation circuit included in the output selection unit 31, and 3i2. The difference operation circuits 311, 312 have a common structure including differential amplification 119054.doc • 17- 200838295 A and resistors R1 to R4. The inverting input terminal of the differential amplifier a is input to the voltage VI via the resistor R1, and is connected to the output terminal of the differential amplifier 8 via the resistor R2. The non-inverting input terminal of the differential amplifier A is input to the voltage V2 via the resistor R3, and is grounded via the resistor R4. When the resistance values of the resistors -R1 to R4 are equal, the voltage Vd output from the output terminal of the differential amplifier A becomes the difference between the input two voltages VI and the voltage V2. Next, the operation of the solid-state imaging device 第 according to the first embodiment will be described. Fig. 6 is a timing chart for explaining the level change of the signal of the solid-state imaging device 1 of the first embodiment. The signals shown in the timing chart are explained in order from the top to the bottom as shown below. The CLK signal is a signal from the external input control unit 61, which is a main clock signal for operating the solid-state imaging device 1 as a whole. The ST signal is a signal from the external input control unit 61, which is a main start signal for instructing to start reading. The signal generated by the Vst signal control unit 61 is a start signal for instructing the operation of the first column to the third column of the light sensing unit to be sequentially selected. The signal generated by the Velk signal control unit 61 indicates that the clock signals of the respective columns of the light sensing unit i are sequentially selected, and the Vshift signal changes based on the signal.

The signal generated by the Vreset signal control unit 61 is a signal indicating the reset of the pixel portion selected by the vshift signal. The signal generated by the Vtrans signal control unit 61 is a signal for indicating the pixel data of the pixel portion selected by the Vshift signal. The signal generated by the Vaddress signal control unit 61 is a signal for instructing reading of the pixel data of the pixel portion of the column selected by the Vshift signal. The Vshift signal is a signal generated by the control unit 61 based on the Vclk signal and the Vst signal, and is a signal indicating the selection of the light sensing unit 119054.doc 18 200838295. The signal produced by the signal system control unit 61 is a signal for holding the long-term stored data (noise component) output from the pixel portion in the second hold circuit 21. The signal generated by the set_S1 signal control unit 61 is a signal indicating that the long-term stored data (signal component) output from the pixel portion is held in the upper holding circuit 2!. The set_n2 signal controls the signal produced by the rider, and refers to the signal that does not store the material (the noise component) output from the pixel portion in the second hold circuit 22. The signal generated by the signal system control unit 61 instructs the short-time storage of the data (the signal is held in the second holding circuit 22) from the pixel portion.

The signal generated by the Hsm number control unit 61 is a start signal for instructing the first reading circuit (21) of the second holding circuit 21 and the second holding circuit 22. The signal generated by the Hclk signal control unit 61 is a clock signal for sequentially reading data from the work holding circuit 21 and the second holding circuit 22, respectively. The Hshift signal is a signal generated by the control unit 6^ based on the Hclk signal and the signal, and indicates that the signal of the nurturing is not read from the !! hold circuit 21 and the second hold circuit (10). Vide. The signal output from the output selecting unit 31 is a value corresponding to the amount of incident light incident on the photodiode included in the pixel portion. ~ Fig. 7 is a timing chart showing the operation of the solid-state imaging device of the second embodiment. The figure shows the timing of the charge storage in the photodiode of each pixel portion of the photo-sensing portion 11, the timing at which the voltage output from the photo-sensing portion u is held by the first holding portion and the second holding portion 22, and The voltage of the Guardian Temple of the ith holding portion (four) and the second holding portion 22 is output to the output selection unit _ 119054.doc • 19· 200838295. Further, this operation is performed based on the respective control signals output from the control unit 61 shown in Fig. 6. Here, for convenience of illustration, the m value is set to 4 and the N value is set to 4. In the timing chart, 'in the top-down order, the charge storage operation in the photodiode of each of the pixel portions Ρι, ι to Ρι, 4 of the column, and the pixel portion P2 > 1 to P2 in the second column are shown. 4, the charge storage operation in each of the photodiodes, the charge storage operation in the photodiode of each of the pixel portions P31 to P34 in the third column, and the photodiode in each of the pixel portions p4i to P4, 4 in the fourth column In the charge storage operation, the voltage holding operation by the holding circuits H1 and H included in the second holding unit 21 is performed by the holding circuits included in the second holding unit μ, respectively. The voltage holding operation and the operation of outputting the video_a signal from the output selecting unit 31. In the light-sensing portion 11, each of the pixel units in the respective rows operates at the same timing, and operates at a timing different from each other in the order of the solid-state. Further, the first column to the _ column of the light sensing unit 11 sequentially perform the following operations. Each pixel portion Pm of the mth column. The photodiode repeatedly repeats the light input operation of the first stage: the corresponding charge storage operation, the initializing operation of the first period Tm, the charge storage operation corresponding to the light incidence of the second period T2, and the second period T2 After the initialization action. However, the second period T2 is shorter than the first period Τ1. Τι and τ2 shown at the top of Fig. 7 indicate periods of respective pixel portions Ρι, η (η = 1 to 4) of the i-th column. Each of the pixel portions of the mth column is incident on the light corresponding to the first period T1. The electric charge generated by the photodiode is charged with the voltage corresponding to the amount of the electric charge via the wiring V11ne(n), and is turned into the second holding portion 21 as a voltage vim" by the 119054.doc 200838295 first holding portion 2 1 Keep the circuit Η!, η remains. At this time, the signal component out_sl(n) and the noise component out-nι(η) are held in the holding circuit η 1, u, and the difference between the signal components out_sl(n) and the noise component out_ni(n) is expressed. Voltage vim η. After the first period τ1, each pixel portion pmn of the mth column is initialized. After the initialization, the light is generated by the photodiode of each pixel portion pm n of the m-th column corresponding to the incidence of light shorter than the second period T2 of the first period T1, and the voltage corresponding to the amount of the electric charge is via the wiring. 111^(11) is input to the second holding portion 22' and held by the holding circuits H2, n of the second holding portion 22 as voltages V2m, n. At this time, the hold circuit Hut holds the signal component out_s2(n) and the noise into a tool ut_n2(n), and the signal components 〇ut_s2(n) and the noise component 〇ut-n2(n) The difference between them represents the voltage V2m n . After the second period, the pixel portions Pm, n of the first melon column are initialized. The voltage Vlm n held by the first holding unit 21 is input to the output selection unit 31 via the wirings mine_sl and Hline-n1. The voltage V2m,n held by the second holding portion 22 is input to the output selecting portion 31 via the wirings Hline_s2 and mine-n2. The output selection unit 31 first inputs the voltage Vlm i and the voltage V2W, and then inputs the voltage Vlm, 2 and the voltage V2m, 2, and then inputs the voltage VIm and the voltage V2m, 3... from the first row to the Nth row. The order input voltage is V Vlm,n, voltage V2m n voltage. Further, the output selection unit ^ selects the output voltage vim,n or the voltage V2mn. The value of the video a signal outputted from the output selection unit 31 is a voltage m when the voltage does not reach the reference voltage Vsat (that is, when the voltage Vlmn is not saturated), and the voltage Vm, n reaches the reference voltage Vsat, which is the voltage. V2m n. As described above, the voltage u and the amount of electric charge generated by the photodiode of the pixel portion 1Vn corresponding to the relatively long first period Tk 119054.doc • 21 - 200838295 light incidence: voltage voltage V2m, n system And corresponding to the relatively short second period T2

The amount of charge corresponding to the amount of charge generated by the photodiode of the pixel portion p of the pixel portion. When the V-ray intensity is small, even if the charge storage time is relatively long, the voltage Vlm,n is not saturated, so the voltage Vlmn is selected. When the light incident intensity is relatively large, the electric Mvimn is saturated, so the voltage V2m,n is selected. Therefore, the solid-state imaging device i expands the dynamic range for a plurality of pixel portions. Further, this solid-state imaging device does not require a frame memory, and only a small-scale circuit is added, so that it can be reduced in size and inexpensive. In the solid-state imaging device 1, the first holding portion 21 and the second holding portion are caused by performing charge storage in the relatively short second period T2 after the charge storage is performed for a relatively long second period τι. 22 respective voltages maintain a small timing difference. Then, the processing until the output selection unit 31 is completed, and the time for holding the voltages of the first holding unit 21 and the second holding unit 22 is short. Therefore, in this respect, the size of the additional circuit can be small. (Second Embodiment) Next, a second embodiment of the solid-state imaging device according to the present invention will be described. FIG. 8 is a schematic configuration diagram of the solid-state imaging device 2 according to the second embodiment. The solid-state imaging device 2 shown in the figure is an APS side, and includes a light sensing unit 11, a second holding unit 21, a second holding unit 22, a third holding unit 23, an output selecting unit 32, and an AD conversion unit. 40. The biasing unit 5〇 and the control unit 62. Preferably, the monoliths are formed on the common substrate SB, and the arrangement on the substrate in this case is as shown, for example. 119054.doc -22- 200838295 Compared with the configuration of the solid-state imaging device 1 of the first embodiment, the solid-state imaging device 2 of the embodiment differs in the following aspects: the replacement portion 23, the replacement rim, The output unit selection unit 31 is provided with the output unit 32, and the control unit 61 is provided instead of the control unit 61. The third holding portion 23 has a structure similar to that of the first holding portion 21 and the second holding portion, respectively, and the charge is generated from the photodiode of the pixel portion of any of the light sensing portions " Input and the charge

The voltage of the quantity 'and the electric (4) is held and output as electricity (four) mi~V3mN. The output selection unit 32 inputs the n electric dusts Vlm, i to vim'N output from the first holding unit 21, and inputs the N voltages V2m, i to V2m, N output from the second holding unit 22, and is also input from The nth voltage is outputted by the third holding unit 23. Further, the output selection unit 32 performs the magnitude of the % voltage ¥1^ or ¥2_ and the reference voltage Vsat, and outputs the m〇de_out signal ' of the comparison result of the table* and when the voltage Vlmn or V2mn does not reach the reference voltage Vsat. 'Selective output voltage Vlmn4v2mn, when vim, ^v2mn reaches the reference voltage Vsat, selectively outputs a voltage V3m n. The AD conversion unit 40 receives the voltage output from the output selection unit 32, converts the voltage (analog value) into a digital value, and outputs the digital value. The bias unit 50 supplies a reference voltage to each of the light sensing unit 11, the output selecting unit 32, and the ad conversion unit 40. The control unit 62 generates and outputs the YS signal and the ST signal input from the outside to control the light sensing unit U, the first holding unit 21, the second holding unit 22, the third holding unit 23, the output selecting unit 32, and the gossip. The control signals of the respective operations of the conversion unit 40 include logic circuits such as shift registers. 119054.doc -23·200838295 FIG. 9 is a structure of the light sensing unit 11, the first holding unit 21, the second holding unit 22, and the third holding unit 23 included in the solid-state imaging device 2 in the state of the second embodiment. Figure. In the light sensing portion 11, two pixels ρ ι , ι Ρ μ, ν having a common structure are arranged in two dimensions, and the pixel portion pm n is located in the mth column. The i-th holding unit 21 includes N holding circuits Hii to Hin. The second holding portion 22 includes n holding circuits Hz' 丨 H2'N. Further, the third holding portion 23 includes N holding circuits Η3, ι ̄ Hu. The N holding circuits ΗιΝ, N holding circuits, and N holding circuits k n have a common structure. The output end of each of the pixel portions P1 > n to PMn in the nth row included in the photo-sensing portion 11, the input terminal of the holding circuit 1 included in the i-th holding portion 21, and the holding circuit h2 included in the second holding 22 The input terminal and the input terminal of the holding circuit 1 included in the third holding unit 23 are connected by a shared line (4) plus (4). The U holding circuits I## included in the i-th holding unit 21 are connected from the output terminals by a common wiring. The output terminals of the N holding circuits I to H2 and N included in the second holding portion 22 are connected by a common wiring. Further, the output terminals of the u holding circuits φ to the third holding portion 23 are connected by a common wiring. Fig. 1 is a view showing a pixel portion 保持, a holding circuit H1, n, and a holding circuit 包含 included in the solid-state imaging device 2 of the second embodiment. And keep the map. Each of the pixel portions, the holding circuit 1 included in the second holding portion 21, and the holding circuit included in the holding portion 22 are respectively connected to the holding circuits I included in the third material portion 23 shown in FIG. Contains 2 electric U2, and 4 switches _, _, _, _. In the circuit H3,n, the switch SW11 and the switch SW12 are connected in series, and are disposed between the wiring Vline(n) and the wiring Hline_s3, and one end of the capacitive element C1 is connected between the switch SW11 and the switch SW12. At the connection point, the other end of the capacitive element C1 is grounded. Further, the switch SW21 and the switch SW22 are connected in series between the wiring Vline(n) and the wiring Hline_n3, one end of the capacitive element C2 is connected to the connection point between the switch SW21 and the switch SW22, and the other end of the capacitive element C2 is grounded. In the holding circuits H3, n, the switch SW11 is switched in accordance with the level of the set-S3 signal supplied from the control 62. The switch SW21 is switched in accordance with the level of the set-n3 signal supplied from the control unit 62. The set_s3 signal and the set-n3 signal are input in common to the N holding circuits included in the third holding unit 23. The switches SW12 and SW22 are switched in accordance with the level of the hshiht(n) signal supplied from the control unit 62. This hold circuit is defective. When the set-n3 signal is shifted from the high level to the low level, the noise component output from the pixel portion Pm,n to the wiring Vline(n) is thereafter held by the electric valley element C2 as the writing pressure out_n3(n). The set-s3 signal is shifted from the high level to the low level 4, and the signal component output from the pixel portion n to the wiring vHne(n) is thereafter held by the capacitance element ci as the voltage out_s3(n). Also, if the hshiht(n) signal becomes a high level, it is a capacitive element. The held voltage out s3(n) is output to the wiring Hlme_s3, and the voltage out_n3(n) held by the capacitive element C2 is turned to the wiring Hline-n3. The difference between the voltages 〇m_s3(n) and the voltage 〇m-n3(n) represents the photodiode of the pixel portion Pmn? 1> The amount of charge generated corresponds to the voltage V3m>n. Fig. 11 is a view showing the configuration of an output selection 119054.doc - 25 - 200838295 portion 32 included in the solid-state imaging device 2 of the second embodiment. The output selection unit 32 includes a difference operation circuit 31, a difference operation circuit 312, a comparison circuit 313, a latch circuit 314, a logic inverter circuit 315, switches SW30 to SW34, switches SW41 to SW44, and switches SW50 to SW52. The first input terminal of the arithmetic circuit 311 is connected to the wiring Hline-si via the switch SW33 and the buffer amplifier, and is connected to the wiring Hline-s2 via the switch SW43 and the buffer amplifier. When the switch SW33 is turned off, the first input terminal is connected. The voltage output out_si (n) is input from the holding circuit Ηι, η to the wiring HUne_sl. On the other hand, when the switch SW43 is turned off, the voltage out_s2(n) output from the holding circuit Η2, η to the wiring Hline_s2 is input. The second input terminal of the difference arithmetic circuit 311 is connected to the wiring Hline-n1 via the switch SW34 and the buffer amplifier, and is connected to the wiring Hline-n2 via the switch SW44 and the buffer amplifier. The second input terminal inputs the voltage out_n1(n) outputted from the holding circuit H1n to the wiring Hline_n1 when the switch SW34 is turned off, and the input self-holding circuit H2 and the n-directional wiring Hline__n2 when the switch SW44 is turned off. The output voltage out_n2(n). The switch SW33 and the switch SW34 perform switching operations at the same timing. Further, the switch SW43 and the switch SW44 also perform switching operations at the same timing. Further, when the group of the switch SW33 and the switch SW34 and the group of the switch SW43 and the switch SW44 are turned on, the other is turned off. Therefore, when the switch SW33 and the switch SW34 are turned off, the difference operation circuit 311 outputs a voltage vlm,n' indicating the difference between the voltage out_si(n) and the voltage 〇ut_nl(n), on the other hand, when the switch SW43 and the switch When SW44 is turned off, the differential circuit 311 outputs a voltage V2m,n representing the difference between the voltage cmt_s2(n) and the voltage 〇ut_n2(n) 119054.doc -26-200838295. The first input terminal of the difference arithmetic circuit 3 12 is connected to the wiring Hline-s3 via the buffer amplifier, and is input to the self-holding circuit H3, and the voltage out of the wiring Hline-s3 is out s3(n). The second input terminal of the difference arithmetic circuit 312 is connected to the wiring mine-n3 via a buffer amplifier, and the voltage out_n3(n) output from the holding circuit Hu to the wiring Hline-n3 is input. Further, the difference operation circuit 312 outputs a voltage V3m indicating the difference between the voltage out_s3(n) and the voltage 〇1^113(11), and the line Hline-si is grounded via the switch SW3 1 by being turned off. The switch SW31 initializes an input voltage input to the first input terminal of the differential shift circuit 311. The wiring Hline_n1 is grounded via the switch SW32, and the input voltage input to the second input terminal of the difference arithmetic circuit 311 is initialized by turning off the switch SW32. The wiring Hline-s2 is grounded via the switch SW41, and the input voltage input to the first input terminal of the difference arithmetic circuit 312 is initialized by turning off the switch SW41. The wiring Hline-n2 is grounded via the switch SW42, and the input voltage input to the second input terminal of the difference arithmetic circuit 312 is initialized by turning off the switch SW42. The wiring Hline_s3 is grounded via the switch SW5 1, and the input voltage input to the first input terminal of the difference arithmetic circuit 312 is initialized by turning off the switch SW5 1 . The wiring Hline_η3 is grounded via the switch SW52, and the input voltage input to the second input terminal of the differential operation circuit 312 is initialized by turning off the switch SW52. The switching operations of the switches SW31, SW32, SW41, SW42, SW51, and SW52 are controlled by the hreset signal supplied from the control unit 62. The comparison circuit 313 compares the voltages Vlm, n4 119054.doc 27-200838295 V2m,n output from the self-difference operation circuit 311 with the magnitude of the reference voltage Vsat, and outputs a mode-out signal indicating the comparison result. The latch circuit 314 inputs the mode_out signal output from the comparison circuit 3 13 and outputs the m〇de_out signal for a fixed time. The logic inverting circuit 315 inputs the mode_〇ut signal output from the latch circuit 314, performs logic inversion, and outputs the inverted signal. One end of the switch SW30 is connected to the output terminal of the difference operation circuit 311, and the switching operation is performed based on the m〇de-out signal output from the latch circuit 314. One end of the switch SW50 is connected to the output end of the difference operation circuit 3 12, and performs a switching operation according to a signal (m〇 (inverted signal of the je_out signal) output from the logic inverting circuit 3 15 . The switch SW30 and the switch SW50 are implemented. When one is open state k' the other is closed, the other end of switch SW 3 0 is connected to the other end of switch SW50, and the vide〇-a signal output from its connection point becomes voltage Vlm, n or voltage V2m , n or voltage V3m, n. Therefore, when the switch SW33 and the switch SW34 are turned off and the voltage vim,n does not reach the reference voltage Vsat, the vide〇-a signal output from the output selection unit 32 becomes the voltage Vlm,n, when the switch SW43 When the switch SW44 is turned off and the voltage V2mn does not reach the reference voltage Vsat, the voltage V2mn is obtained, and when it is not any of the voltages V3m, n, the voltage V3m, n is set. Here, the reference voltage Vsat is set to be k/f with the comparison circuit 313. The voltage Vlmn or the voltage V2m,n is an appropriate value for saturation. The ad conversion unit 40 inputs the video a signal output from the output selection unit 32, converts the voltage (analog value) of the signal into a digital value, and outputs the digital value video. -data Next, the operation of the solid-state imaging device 2 of the second embodiment will be described. Fig. 12 is a view showing the operation of the solid-state imaging device 2 of the second embodiment at the time of 119054.doc -28-200838295. The timing of the vertical charge storage in the photodiode of each pixel portion of the photo-sensing portion u is the timing at which the voltage output from the photo-sensing portion u is held by the holding portion Ί2 holding portion 22 and the third holding portion 23, respectively. And the timing at which the first holding unit 21, the second holding unit 22, and the third holding unit are outputted to the output selection unit 32. The operation is based on the respective control signals output from the control unit 62. In addition, here, in order to facilitate the graph, the value of the threshold is set to 4, and the value of N is set to 4. In the timing diagram, the top-down order is indicated: the pixel of the pixel column ePirPw The charge storage in the diode is #, the second column is: the pixel portion ~~1>2, the charge storage operation in the photodiode of each of the two, and the pixel portion P3 of the third column> The charge storage in the polar body, the pixel part of the 4th column, the pixel part ρ4ι~p44 The voltage storage operation in the body, the voltage holding material by the holding circuits ～ HM included in the ith holding unit 21, and the voltage holding operation by the holding circuits included in the second holding unit "The voltages of the holding circuit included in the holding unit, H3, and 4, respectively, are outputted from the output selecting unit 32." The operation of the signal. In the light sensing unit 11, N of each column w / 歹J The pixel portion operates at the same timing, and the column = operates at a timing that is the same as the fixed time μ. Further, in the light sensing unit u, the following operations are performed in order from the first column to the third column. The photodiode of each pixel portion Pmn of the m-th column repeatedly performs charge storage operation corresponding to the first period: light incidence, initialization after the first _τι, and charge storage operation corresponding to the light incidence of the second period Τ2 And the initialization action after the second period. However, the second period η is shorter than the i-th period 119054.doc -29-200838295 T. The ΤΙ and Τ2 shown at the top of FIG. 12 indicate the period of each pixel portion & ❹ (η = 1 to 4) of the first column. . The electric charge is generated by the photodiode of each pixel portion η of the m-th column corresponding to the incidence of light in the first period Τ1, and the voltage corresponding to the amount of the electric charge is input through the wiring V11ne(n) when the history is an odd number. The first holding portion 21 is held by the holding circuit H1 n as the voltage m, n, and when the value is an even value, the second holding voltage is input as the voltage V2m, and n is held by the holding circuits H2, n. At this time, the signal component 〇ut_sl(n) and the noise component nl(n) are held in the holding circuit H!, n, the signal components om_sl(n) and the noise component out-nl(n) The difference indicates that the voltage m'n holds the signal component 〇ut_s2(n) and the noise into the 〇ut_n2(n) in the holding circuit H2, n, and the signal components 〇ut_s2(n) and the noise component The difference between 〇ut_n2(n) represents the voltage V2m,n. After the first period T1, each pixel portion Pm,n of the mth column is initialized. After the initialization, the light is generated by the photodiode of each pixel portion Pm n of the m-th column corresponding to the incidence of light shorter than the second period T2 of the first period T1, and the voltage corresponding to the inside of the concentrated charge is via the wiring Vline. (n) is input to the third holding portion 23, and is held by the third holding portion 23 as the voltage V3mn. Keep it. At this time, the signal component 〇ut-S3 (^ and the noise-forming knife out-n3(n) are held in the holding circuit, and the signal components 〇llt-s3(n) and the noise component out-n3(n) The difference indicates the voltage V3m n. After the second period D2, the pixel portions Pm n of the (5)th column are initialized. In the output selection unit 32, when the m value is an odd number, the voltage is maintained by the second holding portion vim n is input via a wiring outlet, and is input as "Hline-nl. When the melon value is an even number, the voltage V2m η held by the second holding portion 22 is via wiring 119054.doc • 30-200838295

Hline-S2, Hline-n2 are input, and the voltage V3m,n held by the third holding portion 23 is not limited to the m value and is input to the line via the wiring Hline-s3,mine w

When the m value is an odd number, the output selection unit 32 first inputs the voltage Vlmj and the voltage V3W, and then the input voltage Vlm, 2 and the voltage V3m2, and further inputs the electric MVlm, 3 and the voltage V3m, 3" Since the first! The voltage is input to the Nth row in order of the voltages Vlm, n and the voltage V3mn. When the m value is an even number, the output selection unit 32 first inputs the voltage V2mi and the voltage ν'", and then the input voltage V2m, 2 and the voltage V3m, 2, and further the input voltage ν'" and the voltage V3m, 3... In this manner, the voltages V2m, n and the voltage V3mn are input in the order from the third row to the Nth row. Further, when the m value is an odd number, the voltage selection unit 32 selectively outputs the voltage Vlmn or the voltage V3mn, and when the (f) value is an even number, the voltage selection unit 32 selectively outputs the voltage V2m, n or the voltage V3mn. The value of the Vide0-& signal outputted from the output selection unit 32, when the m value is an odd number, and the voltage Vlmn does not reach the reference voltage Vsa, and when the saturation is Am, the tm value is an even number, and the quasi-voltage Vsat (ie, the voltage V2mn and When it is not saturated, it is a voltage of V2m, n, and is not a voltage of V3m,n. As described above, the voltages Vlm, n and the voltages V2m, n are respectively incident on the light corresponding to the relatively long first period T1. The voltage generated by the photodiode of 卩Pm n corresponds to a voltage voltage V3m, which is generated by the photodiode of the pixel portion Pm n corresponding to the light incident corresponding to the relatively short second period The amount of charge corresponds to the voltage. When the light intensity is relatively small, even if the charge storage time is longer than 119054.doc -31 - 200838295, the voltage Vlm,n or the voltage V2m,n#il is not saturated, so the voltage Vlm,n and the voltage V2m,n are selected. . When the light incident intensity is large, the voltage vimn or the voltage V2 is saturated, so the voltage is selected. Therefore, the solid: the image unit 2 expands the dynamic range for a plurality of pixel portions. Further, the solid-state imaging device 2 does not require a memory, and only a small-scale circuit is added, so that it can be reduced in size and inexpensive.

Further, in the solid-state imaging device 2, the charge storage is performed in the relatively long i-th period τ1, and the second storage period is performed in the relatively short second period, so that the first holding 21 and the second holding portion are caused. 22 respective voltages maintain a small difference in timing. Then, the processing until the output selection unit 32 is completed, and the time during which the first holding unit 21 and the second holding unit 22 hold the voltages is kept short. Therefore, in this respect, the size of the additional circuit can be small. Further, the solid-state imaging device 2 alternately uses the first! Since the holding circuit is in contact with the second holding circuit 22, for example, the voltage can be held in the next column by the second holding circuit 22 during the period in which the holding circuit 21 reads the voltage for a certain column. In the processing period of the selection unit 32, the charge storage in the second period can be performed in the next column. Therefore, in the picture capturing device 2 of the second embodiment, the degree of freedom in setting the first period T1 and the second period T2 is high. Compared with the solid-state imaging device i of the first embodiment, the rate of the building rate can be further increased. (Third Embodiment) Next, a third embodiment of the solid-state imaging device according to the present invention will be described. Fig. 13 is a third embodiment. The solid-state imaging device 3 shown in the figure is a PPS system, and includes a light sensing unit H9054.doc-32-200838295 13, an integrating unit 20, a first holding unit 24, and a second The holding unit 25, the output selecting unit 33, the AD converting unit 40, the biasing unit 50, and the control unit 63. Preferably, the ones are monolithically formed on the common substrate SB, and in this case, one of the configurations on the substrate is, for example, As shown in the figure, the light sensing unit 13 includes The pixel portion PucPwn of the PPS method of two rows and N rows is arranged in two dimensions. Each of the pixel portions Pm n has a photodiode that generates an electric charge corresponding to the amount of incident light. Here, M, Ν^2 or more, (5) For any integer below i, ^ is any integer below N.

The integrating unit 20 receives the electric charge generated by the photodiode of each of the pixel portions Pm of the first column in the photo-sensing portion 13, and outputs a voltage corresponding to the amount of the electric charge. The first holding unit 24 receives the voltage output from the integrating unit 2', and holds and outputs the electric power as the electric house V1mi to VlmN. Similarly, the second holding unit 25 inputs the voltage output from the integrating unit 2G, and holds and outputs the voltage as the electric relay V2m, N. The output selection unit 33 inputs N voltages vim, i to vim, N' output from the first holding unit 24, and also inputs n voltages V2m, N output from the second holding unit 25. And 'the output selection unit % compares the electrical waste reference voltage size, and outputs a mode-out signal indicating the comparison result thereof, and when X ^ does not reach the reference voltage vsat, the selective output voltage Vi, ^ V1 ^ m, n standby Vlm, when n reaches the reference voltage Vsat, the selective output voltage V2mn. The AD conversion unit 4 converts the input self-supply voltage (analog value) into a number! Γ 33 output voltage, and outputs the digit, and outputs the digit - data. The biasing unit 5〇 supplies the reference voltage to the integrating unit 2〇, the partial output selecting unit 33, and the AD converting unit 4, respectively, to 119054.doc •33·200838295. The control unit 63 generates and outputs the control unit 63 for controlling the light sensing unit 13, the integrating unit 20, the first holding unit 24, the second holding unit 25, the output selecting unit 33, and the gossip conversion based on the CLK signal and the ST signal input from the outside. The control signals of the respective operations of the unit 40 include logic circuits such as a shift register.

Fig. 14 is a configuration diagram of the optical sensing unit U, the integrating unit 20, the first holding unit 24, and the second holding unit 25 included in the solid-state imaging device 3 of the third embodiment. In the light sensing portion 13, MxN pixel portions Ρι, ι to Pm, n having a common structure are arranged in two dimensions, and the pixel portion Pm, n is located in the eleventh row of the mth column. The integrating unit 2 includes N integrating circuits having a common structure. The i-th holding unit 24 includes N holding circuits Hhl~. Further, the second holding unit 25 includes N holding circuits Hu to H2, n. The N holding circuits Hu to Hi, n & N holding circuits h2 i to H2, n have a common structure. The output terminals of the "one pixel portion", η to ρΜη of the nth row included in the light sensing portion 13 and the input terminal of the integrating circuit k included in the integrating portion 20 are connected by the common wiring VHne (4). The output end of the integral electric gift included, the holding circuit H terminal included in the first holding portion 24, and the input end of the holding circuit 1 included in the second holding portion 25 are connected by a common wiring. The output of each of the "hold circuits" included in the portion 24 is connected by a common wiring. Further, the output terminals of the respective holding circuits &~^ of the second holding unit 25 are connected by a common wiring. Fig. 15 is a diagram showing a pixel portion included in the solid-state imaging device 3 of the third embodiment: a path I holding circuit Ηΐ, a circuit 保持 of the holding circuit H2, n, and a pixel portion Pm, n including a photodiode _ and a switch . The anode terminal of the photodiode PD is grounded, and the cathode of the photodiode pD is H9054.dc, -34- 200838295. The terminal is connected to the wiring Vline(n) via the switch sw. The switch is switched according to the level of the Vaddress(m) signal supplied from the controller control unit 63. When the switch is turned off, the charge stored in the junction capacitance portion of the photodiode PD is output to the wiring Vline(n). Each of the integrating circuits In included in the mountain integrating unit 20 is provided with an amplifier A, a capacitor element c, and a switch in parallel between the input terminal and the output terminal. The input terminal of each integrating circuit ιη is connected to the wiring vline(n), and is input from the charge of the pixel portion Pm,n of any one of the columns. Please use this switch according to the price of the control unit. The level of the Resetl signal is switched. The integrating circuit 1 discharges the capacitive element C when the switch is turned off, and initializes the voltage output from the output terminal. On the other hand, the integrating circuit In stores the electric charge input to the wheel-in terminal to the capacitor element when the switch 81 is turned on. The output terminal outputs a voltage corresponding to the amount of stored charge. Each of the holding circuits Hi n included in the first holding unit 24 includes a capacitor element c and two switches SW1 and SW2. The holding circuit u, the switch _ and the switch SW2 are connected in series, and the one end of the electric valley element C is connected between the output terminal of the integrating circuit In and the wiring, and the connection point between the switch s W1 and the switch s W2 is connected. One end is grounded. The switch SW1 is switched in accordance with the level of the set_s1 signal supplied from the control unit 63. "[Η signal pair] The N holding circuits Hu to Hin included in the holding unit 24 are commonly input. The switch S W2 is switched according to the level of the hshiht(n) signal supplied from the control unit 63. The set_sl signal is from the high level. The voltage output from the integrating circuit 1 is quasi-transfer to the low level on time, and thereafter held as the voltage out_sl(n) by the capacitive element c. n and, when the hshiht(n) signal is in the directional level, the 119054.doc is held by the capacitive element doc. -35- 200838295 The voltage out_Sl(n) is output to the wiring Hline_sl. The voltage (10)t-si(n) represents the voltage Vlm corresponding to the amount of charge generated by the photodiode PD of the pixel portion Pm,n. n. Each of the holding circuits 包含 included in the second holding unit 25 includes a capacitive element c and two switches SW1 and SW2. In the holding circuit, the switch _ and the switch SW2 are connected in series, and are provided at an output terminal of the integrating circuit In and One end of the electric grid element C between the wiring mine_s2 is connected to the connection point between the switch SW1 and the switch S W2, and the other end of the capacitive element c is grounded. The switch SW1 is based on the level of the set-S2 signal supplied from the control unit 63. The switch set § 2 signal is included in the second holding portion 25 The N holding circuits 112, 1 to 112 are commonly input. The switch S W2 is switched according to the level of the hshiht(n) signal supplied from the control unit 63. The set_s2 signal is shifted from the high level to the low level, since The voltage output from the integrating circuit 1 is thereafter held by the capacitive element c as a voltage out_s2(n). And when the hshiht(n) signal is at a high level, the voltage out_s2(n) held by the capacitive element c is wired. Hline-S2 output. The voltage 〇ut_s2(n) represents a voltage V2m,n corresponding to the amount of charge generated by the photodiode PD of the pixel portion Pm,n. Figure 16 is a solid of the third embodiment. A configuration diagram of the output selection unit 33 included in the imaging device 3. The output selection unit 33 includes an integration circuit, an integration circuit 332, a comparison circuit 333, a latch circuit 334, a logic inversion circuit 335, a switch SW30, and a switch SW40. The circuit 331 and the integrating circuit 332 respectively have the same circuit structure as the integrating circuit i of Fig. 15. The input terminal of the integrating circuit 331 is connected to the wiring Hlme-si, and the input self-holding circuit ,ι, η is output to the wiring HHne-si 119054. Doc -36 - 200838295 Pressing out a si (η), the output voltage Vlm, n. The input terminal of the integrating circuit 332 is connected to the wiring Hline-s2, and the voltage 〇ut__s2(n) output from the holding circuit H2n to the wiring Hline s2 is input, and the voltage V2m is output. n. The comparison circuit 333 compares the voltage Vlmn output from the self-interference operation circuit 331 with the magnitude of the reference voltage Vsat, and outputs a mode_out signal indicating the comparison result. The latch circuit 334 inputs the mode-out signal output from the comparison circuit 333, and outputs the m〇de-out signal for a fixed time. The logic inverting circuit 335 inputs the mode_out signal output from the latch circuit 334, performs logic inversion, and outputs the inverted signal. One end of the switch S W3 0 is connected to the output terminal of the difference operation circuit 313, and the switching operation is performed based on the m〇de-out signal output from the latch circuit 334. One end of the switch SW40 is connected to the output terminal of the difference operation circuit 332, and the switching operation is performed based on the signal (the inverted signal of the m〇de 〇ut signal) output from the logic inverting circuit 335. One of the switch SW30 and the switch SW40 is in an open state, and the other is in a closed state. The other end of the switch SW 30 is connected to the other end of the switch SW40, and the vide〇_a signal output from the connection point becomes the voltage Vlm. n and any of the voltages V2m, n. Therefore, the video-a signal output from the output selection unit 33, when the voltage

Vlm, n is the voltage Vlm,n when the reference voltage Vsat is not reached, and is the voltage V2m,n when the voltage Vlm,n reaches the reference voltage Vsat. Here, the reference voltage Vsat is set to an appropriate value which can be judged in the comparison circuit 333 as to whether or not the voltage Vlmn is saturated. The AD conversion unit 40 inputs the vide〇_a signal output from the output selection unit 31, converts the voltage (analog value) of the signal into a digital value, and outputs the digital value video_data 〇 119054.doc -37· 200838295. The operation of the solid-state image pickup device 3 of the third embodiment will be described. The timing chart of the operation of the solid-state imaging device of the third embodiment will be described in the same manner as the timing chart shown in Fig. 7. In the light sensing and the middle, the N pixel portions of each column operate at the same timing, and the columns operate at timings different from each other. Further, the first column to the μth column of the light sensing unit 13 sequentially perform the operations shown below to the photodiode of each pixel portion 第 of the mth column, and the first period T1 is performed.

The charge storage operation corresponding to the light incident, the initializing operation after the i-th period T1, the charge storage operation corresponding to the light incidence of the second period T2, and the initializing operation after the second period T2. Among them, the second love day τ τι a- , , T T 2 during the second period T1. The electric charge generated by the photodiode of each pixel portion n of the mth column corresponding to the incidence of light in the first period τ1 is input to the integrating circuit In via the wiring VHne(n), and the output from the integrating circuit In corresponds to the electric charge amount. The voltage. The voltage output from the integrating circuit In is input to the ith holding portion 24, and is held by the holding circuit Ηΐβ of the first holding portion 24 as a voltage 匕^ (out_sl(n)). After the first period τ1, each pixel portion Pmn of the mth column is initialized. After the initialization, the electric charge generated by the photodiode of each pixel portion Pmn of the mth column corresponding to the light incident in the second period T2 shorter than the first period T1 is input to the integrating circuit In via the wiring Vline(n). The self-integration circuit ^ outputs a voltage corresponding to the charge 1. The voltage output from the integrating circuit L is input to the second holding portion 25, and is held by the holding circuit H2, n of the second holding portion as the voltage V2mn (〇ut - s2(n)). After the second period 12, the pixel portions Pm,n of the mth column are initialized to 0 119054.doc •38·200838295 The voltage Vlm n held by the first holding unit 24 is outputted via the wiring 匕❻§1. Part 33. The voltage V2m,n held by the second holding portion 25 is input to the input/output selection unit % via the wiring H1iM_s2. In the output selection unit %, "first input voltage Vlm i and voltage V2H, then input voltage Μ and voltage V2m, 2, and then input voltage Vlm, 3 and voltage ν2^··,

The voltage is input from the first row to the Nth row in the order of the voltage Vlm,n and the voltage U. Further, the output selection unit 33 selectively outputs the voltage VUn or the voltage V2m,n. The value of the video-a signal outputted from the output selection unit 33 is a voltage when the voltage V1_ is less than the base voltage Vsat (that is, when the voltage Vlmn is not saturated)

Vlm,n, when Vlm,n reaches the reference voltage Vsat, is the voltage V2m n. As described above, the voltage V 1 m,n is a voltage corresponding to the amount of charge generated by the photodiode of the pixel portion Pm n corresponding to the incident light of the relatively long j-th period τ ,, the voltage V2m,n A voltage corresponding to the amount of electric charge generated by the photodiode of the pixel portion Pm n corresponding to the incidence of the light of the relatively short second period D2. ~ When the incident intensity of light is relatively small, even if the charge storage time is long, the voltage Vlm,n is not saturated, so the voltage νι^η is selected. When the light incident intensity is large, the voltage Vlm n is saturated, so the voltage V2m,n is selected. Therefore, the solid-state imaging device 3 expands the target range for the plurality of pixel portions. Further, the solid-state imaging device 3 does not require a frame memory, and only a small-scale circuit is added, so that it can be reduced in size and inexpensive. Further, in the solid-state imaging device 3, after the charge storage is performed in the relatively long i-th period τι, the charge storage 119054.doc -39-200838295 is stored in the relatively short second period T2 to make the first holding portion The difference between the voltage holding timings of each of the 24 and the second holding portions 25 is small. Then, the processing until the output selection unit 33 is completed, and the time during which the first holding unit 24 and the second holding unit 25 hold the voltages is short. Therefore, in this respect, the size of the additional circuit can be small. (Modification) The solid-state imaging device 1 of the first embodiment is provided with an APS method of two holding units, and the solid-state imaging device 2 of the second embodiment includes an APS method of three holding units, and the third embodiment The garden image capturing device 3 is a PPS system having two holding portions. The solid-state imaging device of the present invention may be a PPS system having three holding portions. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration diagram of a solid-state imaging device according to a first embodiment. Fig. 2 is a configuration diagram of the light sensing unit 11, the first holding unit 21, and the second holding unit 22 included in the solid-state imaging device 1 according to the first embodiment. Fig. 3 is a circuit diagram of a pixel portion Pm, n, a holding circuit Hi, n, and a holding circuit H2, n included in the solid-state imaging device 1 of the first embodiment. Fig. 4 is a configuration diagram of an output selection unit 31 included in the solid-state imaging device 1 of the first embodiment. Fig. 5 is a circuit diagram of the difference arithmetic circuits 3U, 312 included in the output selecting unit 31. Fig. 6 is a timing chart for explaining the change of each signal level in the solid-state imaging device 1 of the first embodiment. Fig. 7 is a timing chart for explaining the operation of the solid-state imaging device 1 of the first embodiment. FIG. 8 is a schematic configuration diagram of the solid-state imaging device 2 according to the second embodiment. FIG. 9 is a junction diagram of the light sensing unit 11, the first holding unit 21, the second holding unit 22, and the third holding unit 23 included in the solid-state imaging device 2 of the second embodiment. FIG. 1 is a pixel portion included in the solid-state imaging device 2 of the second embodiment.

Pm, n, hold circuit H!, n, hold circuit Η. And the circuit diagram of the holding circuit H3 n . Fig. 11 is a configuration diagram of an output selection unit 32 included in the solid-state imaging device 2 of the second embodiment.

Fig. 12 is a timing chart for explaining the operation of the solid-state imaging device 2 of the second embodiment. Fig. 13 is a schematic configuration diagram of a solid-state imaging device 3 according to a third embodiment. Fig. U is a configuration diagram of the optical sensing unit (1) including the integrating unit 20, the ρ holding unit 24, and the second holding unit 25 included in the solid-state imaging device 3 of the third embodiment. Fig. 15 is a diagram showing the output of the pixel portion ρ: η, the integrating circuit Ιn, the holding circuit H1, n, and the holding circuit & circuit diagram 0 included in the solid-state imaging device 3 according to the third embodiment. A configuration diagram of the solid-state imaging unit 3 of the embodiment. [Description of main component symbols] 1 to 3 Solid-state imaging device 11 χ 13 Photosensitive unit 2 〇 integration unit 21 First holding unit 22 Second holding unit 119054.doc -41 - 200838295 23 Third holding unit 24 First holding unit 25 Second holding portions 31 to 33 Output selecting portion 40 AD converting portion 50 biasing portions 61 to 63 Control portion 119054.doc - 42

Claims (1)

200838295 X. Patent application scope: 1. A solid-state imaging device characterized in that M and N are integers of 2 or more, m is an arbitrary integer of 1 or more and Μ, and 11 is an arbitrary integer of 丨 or more, and includes: The sensing portion ′ includes a pixel portion Ρ^-Ρμ, ν, and the pixel portion 〜Pm,n each has a photodiode that generates an amount of electric charge corresponding to the amount of incident light, and the two-dimensional array is arranged in μ columns and N rows; The first holding portion 'holds and outputs a voltage corresponding to the amount of charge generated by each of the photodiodes of the paste pixel portions Pmi to PmN of any one of the m-th column of the photo sensing portion as the voltage vlm i to vlm N a second holding portion that holds and outputs a voltage corresponding to a charge amount generated by each of the N pixel portions pmi to PmN of the mth column of the photo sensing portion as a voltage V2m1 to V2m N; an output selection unit that inputs N voltages vim, !~vim, N output from the first holding unit, and n voltages V2m, N output from the second holding unit, and a comparison voltage Vlmn and a reference voltage The size of the output, and the output table does not compare the result of the signal 'and at the voltage u, at the reference voltage Vsat, the selective output voltage is ¥1 heart, $ is the selective voltage V2m,n; and., the first holding portion The operation of the first row to the second row is controlled by the control unit, and the second control unit and the output selection unit of the light sensing unit are controlled to be in the middle of the light sensing unit: The light incident in the first period and the pixel portion in the mth column 119054.doc 200838295 The amount of charge generated by the photodiode of Pm'n corresponds to the electric charge VIm, n ' is held by the first holding portion; after the first period, each pixel portion Pmn of the claw row is Initialization; "After initialization, the electric (four) corresponding to the amount of charge generated by the photodiode of each pixel portion pm,n of the 111th column corresponding to the light incident in the second period shorter than the first period is electrically Grinding with the heart, kept by the second above; The voltage VIm,n held by the first holding portion and the second hold are maintained. The voltage V2mn held by P is input to the output selection unit, and the voltage vim,n or the voltage V2m n is selectively outputted from the output selection unit. 2. If requested! In the solid-state imaging device, the light sensing unit, the first holding unit, the second holding unit, and the output selection unit are integrally formed on the common substrate. 3. A solid-state imaging device characterized in that: n is an integer of 2 or more, m is an integer of 1 or more and M or less, and n is an arbitrary integer of 丨 or more, and includes: a portion including pixel portions Pi i to Pm n each having a photo-electrode generating an amount of electric charge corresponding to the amount of incident light, and the two-dimensional arrangement is [^ column] The first holding portion 'holds and outputs a voltage corresponding to the amount of charge generated by each of the N pixel portions Pmi to PmN of any one of the m-th columns of the photo sensing portion as the voltage VUj to Vlm , N ; $ 2 > ί 持 持 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The voltage corresponding to the amount of electric charge is the voltage v2m i to V2m N ; and the third holding portion holds and outputs the pixel portions Pm i to Pm, N of the m-th column of any one of the photo-sensing portions. The voltage corresponding to the amount of charge generated by the photodiode is used as the voltage V3m i~V3m N ; An output selection unit that inputs N voltages V, VU, N, or N voltages V2m output from the first holding unit or the second holding unit, and wide V2m NA N voltages V3W output from the third holding unit 〜V3m,N, and compare the voltage vim,n or the voltage V2mn with the magnitude of the reference voltage Vsat, the output indicates the comparison result (4), and when the voltage Vlmn or the voltage u is at the reference voltage Vsat, the selective output voltage Vlm,n or a voltage V2m, or a selective output voltage V3m, n; and a control unit that controls the light sensing unit, the second holding unit, the second holding unit, the third holding unit, and the output selecting unit; control. P is sequentially arranged for each of the i-th column to the second column of the photo-sensing portion: corresponding to the amount of charge generated by the photodiode of each pixel name pm'n of the m-th column corresponding to the incidence of light in the first period The voltage is the electric shoulder VW voltage V2m,n, which is alternately held by the first "holding portion or the above-mentioned first portion; after the first period, each pixel portion of the mth column is V-ized; after the initializing, the corresponding is short The voltage corresponding to the amount of charge generated by the photodiode of each pixel portion bn in the first period is incident as the electric substance m, n, and is maintained by the above-mentioned 119054.doc 200838295; The electric relay Vlm,n or the voltage V2m,n held by the holding portion or the second holding portion and the electric power held by the third holding portion are input to the output selecting portion, and the voltage Vlm is selectively outputted from the output selecting portion. And a voltage V2m, n or a voltage V3m n. The solid-state imaging device of claim 3, wherein the light sensing unit, the first holding unit, the second holding unit, the third holding unit, and the output are The selection portion is formed monolithically on the common substrate. 119054.doc