200837767 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種儲存裝置，尤指一種藉由偵測主機 或緩衝記憶體之資料存取狀態，以即時調整控制器之時脈 頻率，使控制器處理資料之速度加快或減慢，以節省電力 之儲存裝置及可降低該儲存裝置之耗電之方法。 【先前技術】 目前市面上的資料處理裝置A之結構主要包括一控制 * 器B及一儲存媒體C，而該控制器B主要包括一主機控制 界面B1、一儲存媒體存取控制單元B2、一缓衝記憶體管理 單元B3及一微處理單元B4。該主機控制界面B1連接一主 機D，以存取轉換主機D所傳送之資料，而藉由儲存媒體 存取控制單元B2、緩衝記憶體管理單元B3的資料缓衝及 存取控制，以管理主機D之資料存取，而上述各控制單元 分別與微處理單元B4連接，並以微處理單元B4控制整個 • 控制器B之所有運作。 在上述資料處理的過程中，主機D與資料處理裝置A 的時脈是固定的，當主機D傳輸小量的資料給資料處理裝 置A時，資料處理裝置A並不會因此而改變資料處理的速 度，仍是以高速在運轉，而以高速處理小量之資料，將造 成電力的浪費。 為解決過度耗電的問題，目前主要是基於主機D之電 源管理模式所設定之模式，如睡眠、待機模式等，以切換 5 200837767 ' ί變資料處理裝置A的時脈，從而控制資料處理裝置A的 貝料處理速度，惟’上述方法在實際使用時，並無法即時 控制資料處理裝置A的運轉速度，因此，在省電效率上並 不明顯。 有鐘於此，為了％ i μ、+、 善述之缺點，使儲存裝置可依主 、十衝圮憶體之資料存取狀態，即時改變資料處理裝置 的4脈’以降低耗電，發明 h 月人年貝夕年的經驗及不斷的研菸200837767 IX. Description of the Invention: [Technical Field] The present invention relates to a storage device, and more particularly to detecting a clock access frequency of a controller by detecting a data access state of a host or a buffer memory. The speed at which the controller processes data is accelerated or slowed down to save power and to reduce the power consumption of the storage device. [Previously] The structure of the data processing device A currently on the market mainly includes a control device B and a storage medium C, and the controller B mainly includes a host control interface B1, a storage medium access control unit B2, and a storage medium access control unit B2. The buffer memory management unit B3 and a micro processing unit B4. The host control interface B1 is connected to a host D to access the data transmitted by the conversion host D, and the host is managed by the storage medium access control unit B2 and the buffer buffer and access control of the buffer memory management unit B3. The data access of D is performed, and each of the above control units is respectively connected to the micro processing unit B4, and all operations of the entire controller B are controlled by the micro processing unit B4. During the above data processing, the clock of the host D and the data processing device A is fixed. When the host D transmits a small amount of data to the data processing device A, the data processing device A does not change the data processing. Speed, still running at high speed, and processing small amounts of data at high speed will result in waste of electricity. In order to solve the problem of excessive power consumption, the current mode is mainly based on the mode set by the power management mode of the host D, such as sleep, standby mode, etc., to switch the clock of the data processing device A, thereby controlling the data processing device. The processing speed of the bedding material of A is only that the above method cannot control the running speed of the data processing device A in real time, and therefore, the power saving efficiency is not obvious. There is a clock here, in order to % i μ, +, the shortcomings of the description, so that the storage device can access the state according to the data of the main and the ten-in-one memory, and instantly change the 4-pulse of the data processing device to reduce power consumption, inventing h month people's years of experience and continuous research
改進，遂有本發明之產生。 X 【發明内容】 本發明之主要目的力&讲 _ _ “ 的在&供一種可降低儲存裝置之耗電 '^万法’猎由偵測主機或 即時1敕批p * 衝5己體之貢料存取狀態，以 β正控制态之蚪脈頻率，使控制器處理資料之速户 快或減慢，俾能即時改變/又σ 力。 艾柯仔衣置之運轉速率，以節省電 本發=之次要目的在提供—種儲存裝置藉由以― 偵測主機或緩衝記憶體之資料之存取狀態，並: 糸、、先岭脈調整單元即時 控制器處理眘枓夕、Φ ώ 役制。。之％脈頻率，以增減 運轉 二^又之結構’俾能即時改變儲存褒置之 !轉逮率，以節省電力。 又 為達上述發明之目的’本發明所設之可降 之耗電之方法，包括 -子衣置 主樯I地如 ^驟.a.k供一控制器，以控制— 機與—儲存媒體間之資料存取；b.提供一 谓挪資料之存取狀態；以祕|視早兀’以 及美供一系統時脈調整單元， 6 200837767 ' 以依據監視單元所偵測之資料存取狀態，調整控制器之時 脈頻率，而增減控制器處理資料之速度。 本發明所設之儲存裝置，包括一控制器及一儲存媒 體，該控制器包括一主機控制界面、一儲存媒體存取控制 單元、一緩衝記憶體管理單元、一微處理單元、一監視單 元以及一系統時脈調整單元。該主機控制界面係連接一主 機，供存取轉換主機所傳送之資料；該儲存媒體存取控制 單元係分別連接主機控制界面及儲存媒體，供控制主機資 • 料之存取；該緩衝記憶體管理單元係與主機控制界面及儲 存媒體存取控制單元連接，供管理一緩衝記憶體之資料存 取；該微處理單元係分別與主機控制界面、儲存媒體存取 控制單元、緩衝記憶體管理單元及至少一隨機存取記憶體/ 唯讀記憶體（RAM/ROM)連接，供控制控制器之運作；該 監視單元係供監視上述資料之存取狀態；而該系統時脈調 整單元係與監視單元連接，以依據監視單元偵測之資料存 0 取狀態，調整控制器之時脈頻率，以增減控制器之資料處 理速度。 為便於對本發明能有更深入的瞭解，茲詳述於後： 【實施方式】 請參閱第1圖所示，其為本發明可降低儲存裝置之耗 電之方法之較佳實施例，包括下列步驟： a. 提供一控制器，以控制一主機與一儲存媒體間之 200837767 資料存取 b. 提供一監視單元，以偵測資料之存取狀態 C· 提供一系統時脈調整單元，以依據監視單元所偵 測之資料存取狀態，以調整控制器之時脈頻率， 而增減控制器處理資料之速度。 V驟b中’该監視單元係監視控制器内之緩衝記 體之資料存取時之填滿㈣，以於步驟 ^ 脈調整單元調整控制器之時脈頻率。 手㈣ 以於視;元由亦可直接監視主機存取資料之速率， 頻率，# 時脈調整單元調整控制器之時脈 電之效果。I、控制器的資料處理速度相匹配，以達到省 快閃錄體，所、^ 媒體3，該儲存媒體3係為 件；而該控制二：存媒體3亦可為硬碟或其他儲存元 取控制單元2;:: 機控制界面21、-儲存媒體存 24、一監視單-二緩衝記憶體管理單元23、-微處理單元 70以及-系統時脈調整單元^。 4所傳送界Γ1係連接—主機4,供存取轉換主機 主機控制界面體存取控制單7122係分別連接 該緩衝記憶體管理單子3、=，供控制主機4資料之存取； 疋23係與一緩衝記憶體27、主機控制 8 200837767 ' 界面21及儲存媒體存取控制單元22連接，供管理緩衝記 憶體27之資料存取；該微處理單元24係分別與主機控制 界面21、儲存媒體存取控制單元22、缓衝記憶體管理單元 23及至少一隨機存取記憶體/唯讀記憶體（RAM/ROM) 28 連接，供控制整個控制器2之運作；而該監視單元25係連 接緩衝記憶體27，供監視上述資料之存取狀態，在本實施 例中，該監視單元25係偵測缓衝記憶體27之資料填滿狀 態；而該系統時脈調整單元26係與該監視單元25連接， ⑩ 以依據該監視單元25偵測之資料存取狀態，調整控制器2 之一時脈產生器（圖中未示）所產生之時脈頻率，以增減 控制器2之資料處理速度。 使用時，上述偵測緩衝記憶體27之資料填滿狀態，因 主機4進行資料之寫入動作及讀取動作之不同而有所區別。 當主機4進行資料之寫入動作時，該緩衝記憶體27的 儲存空間若始終未能超過一低臨界值，例如：儲存空間的 φ 1/4，表示主機4的寫入速度比控制器2之處理速度慢，系 統時脈調整單元26即降低控制器2之時脈頻率，減缓控制 器2的運轉速度，使主機4與控制器2的資料處理速度相 匹配。而當該緩衝記憶體27的儲存空間若始終未能低於一 高臨界值，例如：儲存空間的3/4，表示主機4的寫入速度 通常比控制器2之處理速度快，系統時脈調整單元26則調 升控制器2之時脈頻率，以增加控制器2的運轉速度。 而當主機4進行資料之讀取動作時，若該緩衝記憶體 9 200837767 ' 27的儲存空間始終未能低於一高臨界值，例如：儲存空間 的3/4，表示主機4的讀取速度較慢，系統時脈調整單元 26將降低控制器2之時脈頻率，減缓控制器2的運轉速度； 而若該缓衝記憶體27的儲存空間始終未能高於一低臨界 值，例如：儲存空間的1/4，表示主機4的讀取速度較快， 系統時脈調整單元27將調升控制器2之時脈頻率，增加控 制器2的運轉速度，直至到達控制器2的最高運轉速度為 止。 • 請參閱第3圖所示，其為本發明儲存裝置1之第二實 施例，其中，該監視單元25係連接主機控制界面21，以藉 由偵測主機控制界面21—段時間内之資料轉換狀態或固定 時間内之資料存取狀態，以偵測得知主機4存取資料之速 率；而該系統時脈調整單元26則依據該監視單元25偵測 之主機4資料存取速率，即時調整控制器2之時脈頻率。 於本發明中，上述系統時脈調整單元26係為一除頻器 φ 電路，當該主機4資料存取速率減缓時，可將控制器2之 時脈頻率除以2,而當該主機4資料存取速率增快時，將控 制器2之時脈頻率乘以2,以即時改變控制器2之時脈頻率。 實施時，所述的系統時脈調整單元26亦可為一相位鎖 定迴路（PPL, Phase Locked Loop)，該相位鎖定迴路較佳 係為一相位鎖定頻率合成器電路，以準確調整整個控制器 之系統時脈，從而使主機4與控制器2的資料處理速度相 匹配，以達到省電之效果。 200837767 因此，本發明具有以下之優點： 1 本發明可依主機或緩衝記憶體之資料存取狀 恶，即時調整控制器處理資料之速度，因此不 會讓控制器過度運轉，以有效節省電力。 2、 本發明可即時調整控制器處理資料之速度，以 達到省電之效果，比較習用技術需藉由不同模 式的切換以省電的方式，在使用上更為方便， 且更有效率。 • “上所述’依上文所揭示之内容，本發明確可達到發 明之預期目的’提供一種可依主機或緩衝記憶體之資料存 ==即時改變資料處理裝置的時脈，以降低耗電 存裝置及可降低該儲存裝置之耗電之方法，極具產業上利 用之價值，爰依法提出發明專利申請。 〃 r，述乃是本發明之具體實施例及所運用之技術手 本文的揭露或教導可衍生推導出 本發明之構想所作之等效改變，其所產以 太名 兄明書及圖式所涵蓋之實質精神時，均庫視為名 本創作之技術範噚之内，合先陳明。 丨應視為在 【圖式簡單說明】 驟流=圖係為本發明可降低儲存裝置之耗電之方法之步 實施例之電路方 一第2圖係為本發明之儲存裝置之第一 塊示意圖。 200837767 ' 第3圖係為本發明之儲存裝置之第二實施例之電路方 塊不意圖。 第4圖係為習用資料處理裝置之電路方塊示意圖。 【主要元件符號說明】 資料處理裝置 A 控制器 B 主機控制界面 B1 儲存媒體存取控制單元B2 緩衝記憶體管理單元 B3 微處理單元 B4 儲存媒體 C 主機 D 儲存裝置 1 控制器 2 主機控制界面 21 儲存媒體存取控制單元22 緩衝記憶體管理單元 23 微處理單元 24 監視單元 25 系統時脈調整單元 26 緩衝記憶體 27 隨機存取記憶體/唯讀記憶體28 儲存媒體 3 主機 4Improvements have not occurred in the present invention. X [Summary of the Invention] The main purpose of the present invention is to provide a power-saving device that can reduce the power consumption of the storage device by the detection host or the instant 1 batch p * 冲5 The tributary access state of the body, with the pulse frequency of the β positive control state, enables the controller to process the data faster or slower, and can instantly change / σ force. The speed of the Ai Kezi clothing is set to The purpose of saving electricity is to provide a storage device by means of "detecting the access status of the host or buffer memory data, and: 糸,, first ridge pulse adjustment unit, the instant controller handles the cautious eve Φ ώ 役 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The method of reducing the power consumption includes: - the sub-clothing main 樯 I. ^ .. ak for a controller to control the data access between the machine and the storage medium; b. providing a data transfer The access state; the secret | see early and 'the United States for a system clock adjustment unit, 6 200837767 ' Adjusting the clock frequency of the controller according to the data access status detected by the monitoring unit, and increasing or decreasing the speed of processing the data by the controller. The storage device provided by the invention comprises a controller and a storage medium, and the control The device comprises a host control interface, a storage medium access control unit, a buffer memory management unit, a micro processing unit, a monitoring unit and a system clock adjustment unit. The host control interface is connected to a host for access Converting the data transmitted by the host; the storage medium access control unit is respectively connected to the host control interface and the storage medium for accessing the control host resource; the buffer memory management unit is connected to the host control interface and the storage medium The control unit is connected to manage data access of a buffer memory; the micro processing unit is respectively connected to the host control interface, the storage medium access control unit, the buffer memory management unit, and at least one random access memory/read only memory Body (RAM/ROM) connection for operation of the control controller; the monitoring unit is for monitoring the storage of the above data The system clock adjustment unit is connected to the monitoring unit to adjust the clock frequency of the controller according to the data stored in the monitoring unit to adjust the data processing speed of the controller to increase or decrease the data processing speed of the controller. For a more in-depth understanding, please refer to the following: [Embodiment] Please refer to FIG. 1 , which is a preferred embodiment of the method for reducing power consumption of a storage device according to the present invention, including the following steps: a. Providing a controller for controlling 200837767 data access between a host and a storage medium b. providing a monitoring unit to detect the access status of the data C. providing a system clock adjustment unit to detect according to the monitoring unit The data access status is measured to adjust the clock frequency of the controller, and increase or decrease the speed at which the controller processes the data. In step V, the monitoring unit fills up the data access of the buffered data in the controller (4), so that the clock adjustment unit adjusts the clock frequency of the controller. Hand (4) for viewing; Yuan can also directly monitor the rate at which the host accesses data, frequency, and #clock adjustment unit adjusts the clock power of the controller. I, the controller's data processing speed is matched to achieve the provincial flash recording, the media 3, the storage medium 3 is a piece; and the control 2: the storage medium 3 can also be a hard disk or other storage element The control unit 2;:: machine control interface 21, - storage medium storage 24, a monitoring single-two buffer memory management unit 23, - micro processing unit 70, and - system clock adjustment unit ^. 4 transmission interface 1 system connection - host 4, for access to the conversion host host control interface body access control list 7122 is connected to the buffer memory management list 3, = for access to the control host 4 data; 疋 23 series Connected to a buffer memory 27, a host control 8 200837767 'interface 21 and a storage medium access control unit 22 for managing data access of the buffer memory 27; the micro processing unit 24 is respectively associated with the host control interface 21 and the storage medium The access control unit 22, the buffer memory management unit 23, and at least one random access memory/read only memory (RAM/ROM) 28 are connected to control the operation of the entire controller 2; and the monitoring unit 25 is connected. The buffer memory 27 is configured to monitor the access status of the data. In the embodiment, the monitoring unit 25 detects the data filling status of the buffer memory 27; and the system clock adjusting unit 26 is connected to the monitoring. The unit 25 is connected, 10 to adjust the clock frequency generated by a clock generator (not shown) of the controller 2 according to the data access status detected by the monitoring unit 25, to increase or decrease the data processing of the controller 2. Degree. In use, the data of the detection buffer memory 27 is filled up, and the host 4 differs in the data writing operation and the reading operation. When the host 4 performs the data writing operation, the storage space of the buffer memory 27 fails to exceed a low threshold value, for example, φ 1/4 of the storage space, indicating that the writing speed of the host 4 is greater than the controller 2 The processing speed is slow, and the system clock adjusting unit 26 lowers the clock frequency of the controller 2, slows down the operating speed of the controller 2, and matches the data processing speed of the host 4 and the controller 2. When the storage space of the buffer memory 27 is not lower than a high threshold value, for example, 3/4 of the storage space, it means that the writing speed of the host 4 is usually faster than the processing speed of the controller 2, and the system clock. The adjusting unit 26 then raises the clock frequency of the controller 2 to increase the operating speed of the controller 2. When the host 4 performs the data reading operation, if the storage space of the buffer memory 9 200837767 ' 27 is not lower than a high threshold value, for example, 3/4 of the storage space, the reading speed of the host 4 is indicated. Slower, the system clock adjustment unit 26 will reduce the clock frequency of the controller 2, slowing down the operating speed of the controller 2; and if the storage space of the buffer memory 27 is not always higher than a low threshold, for example : 1/4 of the storage space, indicating that the reading speed of the host 4 is faster, the system clock adjusting unit 27 will increase the clock frequency of the controller 2, and increase the operating speed of the controller 2 until reaching the highest level of the controller 2. The speed of operation is up. Please refer to FIG. 3, which is a second embodiment of the storage device 1 of the present invention, wherein the monitoring unit 25 is connected to the host control interface 21 for detecting the data of the host control interface 21 The data access status of the conversion state or the fixed time is detected to detect the rate at which the host 4 accesses the data; and the system clock adjustment unit 26 is based on the data access rate of the host 4 detected by the monitoring unit 25, Adjust the clock frequency of controller 2. In the present invention, the system clock adjustment unit 26 is a frequency divider φ circuit, when the data access rate of the host 4 is slowed down, the clock frequency of the controller 2 can be divided by 2, and when the host 4 When the data access rate is increased, the clock frequency of the controller 2 is multiplied by 2 to instantly change the clock frequency of the controller 2. In implementation, the system clock adjustment unit 26 can also be a phase locked loop (PPL), which is preferably a phase locked frequency synthesizer circuit to accurately adjust the entire controller. The system clock is used to match the data processing speed of the host 4 and the controller 2 to achieve the power saving effect. 200837767 Therefore, the present invention has the following advantages: 1. The present invention can adjust the speed of processing data by the controller according to the data access of the host or the buffer memory, so that the controller is not over-operated to save power. 2. The invention can adjust the speed of the controller to process data in real time, so as to achieve the effect of power saving, and the conventional technology needs to be switched by different modes to save power, which is more convenient and more efficient in use. • “Before the above, the present invention can achieve the intended purpose of the invention.” Providing a data that can be stored in the host or buffer memory == instantly change the clock of the data processing device to reduce the consumption. The electrical storage device and the method for reducing the power consumption of the storage device are of great industrial value, and the invention patent application is filed according to law. 〃 r, the description is the specific embodiment of the invention and the technical application used herein. The disclosure or teaching can be derived to derive the equivalent changes made by the concept of the present invention, which are considered to be within the technical scope of the author's creation.陈 明 。 丨 丨 丨 丨 简单 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = The first block diagram. 200837767 'The third figure is a circuit block diagram of the second embodiment of the storage device of the present invention. FIG. 4 is a block diagram of a circuit of the conventional data processing device. DESCRIPTION OF REFERENCE NUMERALS Data processing device A Controller B Host control interface B1 Storage medium access control unit B2 Buffer memory management unit B3 Micro processing unit B4 Storage medium C Host D Storage device 1 Controller 2 Host control interface 21 Storage media access Control unit 22 buffer memory management unit 23 micro processing unit 24 monitoring unit 25 system clock adjustment unit 26 buffer memory 27 random access memory/read only memory 28 storage medium 3 host 4
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