200837556 九、發明說明： 【發明所屬之技術領域】 本揭示案係關於串行介面之領域。詳言之，揭示一種用 於在無外部载ϋ所供應之操作模式㈣信號之情況下配 置串行匯流排物理層介面成迴反模式的方法及裝置。 【先前技術】 諸如拇指碟之記憶體設備並行地處理用於儲存之資料且 串行地處理用於輸入及/或輸出至主機或其他外部設備的 貧料。記憶體設備通常具有特殊應用積體電路（ASIC)，其 具有通用串行匯流排物理層介面（USB PHY)以在串行與並 行格式之間轉換資料且提取並解譯高速信號。 ASIC測試器通常用以在生產包括USB ?11¥之Asic時對 ASIC進行測試。ASIC測試器具有多個特徵，包括配置 USB PHY之控制輸入成迴反模式之能力，使得並行資料經 串行化且接著由USB PHY轉換回並行。輸入並行資料接著 與輸出並行資料相比較且產生測試結果。 在可靠性測試中，測試USB ΡΗΥ歷時經延長之時間段 (多達1000小時），同時環境參數經改變且USB ρΗγ操作經 觀測。對於執行可靠性測試而言，低成本測試比全Asie測 減更佳。可藉由具有較少之所需外部測試功能而實現低成 本測試。 【發明内容】 當前已認定在不需要外部測試器之情況下於USB PHY中 起始迴反模式之需要。 127869.doc 200837556 JU nf-| X 係由請求項界定且此部分之内容不應被當作對彼 等請求項之限制。200837556 IX. Description of the invention: [Technical field to which the invention pertains] The present disclosure relates to the field of serial interfaces. In particular, a method and apparatus for configuring a serial bus physical layer interface to be in an inverted mode without an external mode of operation (4) signal supplied by an external carrier is disclosed. [Prior Art] A memory device such as a thumb disc processes data for storage in parallel and serially processes lean materials for input and/or output to a host or other external device. Memory devices typically have a special application integrated circuit (ASIC) with a universal serial bus physical layer interface (USB PHY) to convert data between serial and parallel formats and to extract and interpret high speed signals. ASIC testers are commonly used to test ASICs when producing Asic including USB?11. The ASIC tester has several features, including the ability to configure the USB PHY's control inputs to be in an inverted mode, allowing parallel data to be serialized and then converted back to parallel by the USB PHY. The input parallel data is then compared to the output parallel data and the test results are generated. In the reliability test, the USB 测试 is tested over an extended period of time (up to 1000 hours) while the environmental parameters are changed and the USB ρΗγ operation is observed. For performance reliability testing, low-cost testing is better than full Asie measurement. Low cost testing can be achieved with fewer external test functions required. SUMMARY OF THE INVENTION It has now been determined that a need to initiate a bounce mode in a USB PHY without the need for an external tester. 127869.doc 200837556 JU nf-| X is defined by the request and the content of this section should not be construed as limiting the claims.
根據本揭示案之一態樣，向特殊應用積體電路（ASIC)中 之儲存凡件寫入控制位元序列，以用於在ASIC中於通用串 行匯流排物理層介面（USB ΡΗγ)中起始迴反模式。控制位 凡序列經傳達至USB PHY之控制輸入。可程式化及/或可 選擇之測試資料亦可傳達至USB PHY。可結算由USB PHY 執行之迴反操作的數目。又，可結算在測試資料與傳回資 料之間的匹配之數目。 根據本揭示案另一態樣，ASIC具有USB PHY、與USB PHY之控制輸入通信之迴反控制引擎，及處理器，以設定 在迴反控制引擎中之可程式化儲存元件的狀態。該處理器 藉由向迴反控制引擎發送適當控制信號序列而起始USB PHY之迴反模式。迴反控制引擎較佳具有具用於接收控制 信號序列之儲存元件的可程式化暫存器。 較佳地，處理器經配置以致能硬體產生資料或可程式化 測試資料之產生，且ASIC具有經配置以向USB PHY傳達 測試資料之多工器。第一記憶體可整合於ASIC中以接收亦 傳達至USB PHY之測試資料。第二記憶體可整合於asic 中以接收由USB PHY傳回之串行化/解串行化測試資料。 ASIC可包括結真由USB PHY執行之迴反操作的數目之第 一计數器。第一什數裔可結异在每一迴反操作完成時之第 一記憶體中的資料與第二記憶體中的資料之間的匹配之數 目0 127869.doc 200837556 現將參看所附加圖式描述較佳實施例。 【實施方式】 圖1展示具有處理器102、迴反控制引擎104及USB PHY 106之ASIC 100。迴反控制引擎104具有例如108之與USB PHY 106的控制輸入（未圖示）通信之儲存元件。控制輸入 (未圖示）之狀態判定USB PHY 106是否經配置以操作於迴 反模式中。迴反控制引擎104允許處理器102配置USB PHY 106以操作於迴反模式中。在一方案中，迴反控制引擎104 具有可藉由處理器102程式化之一組暫存器。來自 Chipidea(葡萄牙）或其他PHY IP供應商之USB PHY可實施 於ASIC中。 處理器102可下載且執行用於配置USB PHY 106在迴反 模式中操作之一組指令。舉例而言，指令可包括對迴反控 制引擎104之寫入序列以提供由USB PHY 106所需之用於 迴反模式操作的控制信號序列。處理器102亦可下載用於 執行可靠性（或其他）測試之指令，且可在測試完成後即抹 除指令。 圖2為實施圖1之組件且可包含諸如快閃記憶體拇指碟之 USB周邊設備之一部分之ASIC 200的方塊圖。USB周邊設 備可經配置以經由USB通信線208與主機設備（未圖示）連 接。主機設備可為任何設備之USB埠，該任何設備具有諸 如基於個人電腦或其他微處理器之設備（諸如行動電話或 MP3播放機）之USB能力。USB通信線208可為USB周邊設 備經由標準USB連接器與主機設備的直接USB連接，或可 127869.doc 200837556 包括介入USB功能。ASIC 200宜包括用於連接至諸如快閃 記憶體之非揮發性記憶體的介面模組212。 ASIC 200包括具有展示於圖3中之迴反控制引擎300之引 擎辅助塊204。迴反控制引擎300控制可程式化暫存器 324，暫存器324具有經由連接器322而連接至USB PHY 206之控制輸入的儲存位置。在一較佳方案中，可程式化 暫存器324為韌體USB PHY迴反致能暫存器302及韌體USB PHY迴反控制暫存器304。 韌體USB PHY迴反致能暫存器302具有致能（en)儲存位 置306以保持判定USB PHY 206之控制輸入是否可由韌體 USB PHY迴反控制暫存器304儲存位置控制的設定。致能 (en)儲存位置306設定致能或者去能USB PHY迴反模式之韌 體控制。 韌體USB PHY迴反致能暫存器302具有輸出致能（〇e)儲 存位置308以保持控制USB PHY 206是否向ASIC輸出插腳 輸出迴反測試傳回資料的設定。 韌體USB PHY迴反控制暫存器304具有起始（in)儲存位置 3 10以保持起始迴反模式之設定。在一較佳方案中，起始 (in)儲存位置310為僅在其他USB PHY迴反控制暫存器304 儲存位置已為所要操作模式（諸如迴反模式）設定之後設定 的位元。 操作模式（mode)儲存位置314保持設定USB PHY 206之 操作模式（諸如迴反模式）的程式碼。鎖存器（lat)儲存位置 3 12經設定以鎖存在操作模式（mode)儲存位置314中的測試 127869.doc 200837556 模式值。重設（re)儲存位置3 16經設定以立即使USB PHY 206退出迴反模式。時脈控制（cl)儲存位置32〇控制由USB PHY 206產生之時脈。 請參看圖4，引擎辅助塊204亦可包括用於測試迴反模式 中之USB PHY 206的測試組件400。測試組件400可包括與 處理^§ 2 0 2通化之測試邏輯電路414。在一方案中，測試邏 輯電路在自處理器202接收到致能信號後即輸出測試資 料。測試資料可自硬體資料電路（硬體測試資料）獲得，或 者自可藉由處理器202(經程式化測試資料）程式化之測試資 料暫存器獲得。測試邏輯電路414可包括硬體資料電路（未 圖示）及測試資料暫存器（未圖示）。 用於每一迴反測試之測試資料可由USB ΡΗΥ 206藉助於 與測试資料暫存器通信的多工器2 14(圖2)接收。多工器214 係由引擎輔助塊204控制，該引擎辅助塊204在來自uSB媒 體存取控制電路（USB MAC)210之正常功能資料與測試資According to one aspect of the present disclosure, a sequence of control bits is written to a storage element in a special application integrated circuit (ASIC) for use in an ASIC in a universal serial bus physical layer interface (USB ΡΗ γ) Start the inverse mode. Control bit The sequence is communicated to the control input of the USB PHY. Programmable and/or selectable test data can also be communicated to the USB PHY. The number of round-trip operations performed by the USB PHY can be settled. In addition, the number of matches between the test data and the returned data can be settled. In accordance with another aspect of the present disclosure, an ASIC has a USB PHY, a flyback control engine that communicates with the control input of the USB PHY, and a processor to set the state of the programmable storage element in the flyback control engine. The processor initiates the bounce mode of the USB PHY by sending a sequence of appropriate control signals to the back-control engine. The flyback control engine preferably has a programmable register with storage elements for receiving a sequence of control signals. Preferably, the processor is configured to enable the generation of data or programmable test data, and the ASIC has a multiplexer configured to communicate test data to the USB PHY. The first memory can be integrated into the ASIC to receive test data that is also communicated to the USB PHY. The second memory can be integrated into the asic to receive the serialized/deserialized test data returned by the USB PHY. The ASIC can include a first counter that counts the number of backhaul operations performed by the USB PHY. The first number of people can be distinguished by the number of matches between the data in the first memory and the data in the second memory at the completion of each counter operation. 0 127869.doc 200837556 Reference will now be made to the attached figure. The preferred embodiment is described. [Embodiment] FIG. 1 shows an ASIC 100 having a processor 102, a back-control engine 104, and a USB PHY 106. The flyback control engine 104 has a storage element, such as 108, in communication with a control input (not shown) of the USB PHY 106. The state of the control input (not shown) determines if the USB PHY 106 is configured to operate in the flip mode. The flyback control engine 104 allows the processor 102 to configure the USB PHY 106 to operate in an anti-reverse mode. In one aspect, the bounce control engine 104 has a set of registers that can be programmed by the processor 102. A USB PHY from Chipidea (Portugal) or other PHY IP provider can be implemented in an ASIC. The processor 102 can download and execute a set of instructions for configuring the USB PHY 106 to operate in a reverse mode. For example, the instructions may include a write sequence to the back-control engine 104 to provide a sequence of control signals required by the USB PHY 106 for the return mode operation. The processor 102 can also download instructions for performing a reliability (or other) test and can erase the instructions upon completion of the test. 2 is a block diagram of an ASIC 200 that implements the components of FIG. 1 and may include a portion of a USB peripheral device such as a flash memory thumb. The USB peripheral device can be configured to interface with a host device (not shown) via a USB communication line 208. The host device can be a USB port of any device having USB capabilities such as a personal computer or other microprocessor based device such as a mobile phone or MP3 player. The USB communication line 208 can be a direct USB connection of the USB peripheral device to the host device via a standard USB connector, or 127869.doc 200837556 includes an intervening USB function. ASIC 200 preferably includes an interface module 212 for connection to non-volatile memory such as flash memory. ASIC 200 includes an engine auxiliary block 204 having a bounce control engine 300 shown in FIG. The flyback control engine 300 controls the programmable register 324, which has a storage location connected to the control input of the USB PHY 206 via the connector 322. In a preferred embodiment, the programmable register 324 is a firmware USB PHY back-acting register 302 and a firmware USB PHY back-control register 304. The firmware USB PHY back-reversal register 302 has an enable storage location 306 to maintain a determination as to whether the control input of the USB PHY 206 can be returned by the firmware USB PHY control register 304 to store the position control settings. Enable (en) storage location 306 to enable or disable the firmware control of the USB PHY inversion mode. The firmware USB PHY back-reversal register 302 has an output enable (〇e) storage location 308 to maintain control of whether the USB PHY 206 outputs a back-to-back test return data to the ASIC output pin. The firmware USB PHY back control register 304 has a start (in) storage location 3 10 to maintain the initial flip mode setting. In a preferred embodiment, the in (in) storage location 310 is a bit that is set only after the other USB PHY flyback control register 304 storage location has been set for the desired mode of operation (such as a flip mode). The mode storage location 314 maintains a code that sets the operating mode of the USB PHY 206, such as the inverted mode. The latch (lat) storage location 3 12 is set to latch the test 127869.doc 200837556 mode value in the mode storage location 314. Reset (re) storage location 3 16 is set to immediately bring the USB PHY 206 out of the reverse mode. The clock control (cl) storage location 32 controls the clock generated by the USB PHY 206. Referring to Figure 4, the engine auxiliary block 204 can also include a test component 400 for testing the USB PHY 206 in the bounce mode. Test component 400 can include test logic 414 that is integrated with processing. In one arrangement, the test logic circuit outputs the test data upon receipt of the enable signal from the processor 202. The test data can be obtained from a hardware data circuit (hardware test data) or from a test data register that can be programmed by the processor 202 (programmed test data). Test logic circuit 414 can include a hardware data circuit (not shown) and a test data register (not shown). The test data for each back-test can be received by the USB port 206 by means of a multiplexer 2 14 (Fig. 2) in communication with the test data register. The multiplexer 214 is controlled by an engine auxiliary block 204 that is in the normal functional data and test resources from the uSB media access control circuit (USB MAC) 210.
料之間進行選擇，以在迴反測試經致能時以一序列向USB PHY 206提供測試資料。測試資料序列可藉由處理器2〇2而 転式化或可經硬體控制。引擎辅助塊204監視並控制測試 序列。 藉由測試邏輯電路414傳達至USB PHY 206之測試資料 亦保持於在引擎輔助塊204中之測試資料儲存元件4〇2中。 在迴反模式中，USB ρΗγ 2〇6串行化並解串行化測試資料 且向引擎輔助塊2〇4中之傳回資料儲存元件4〇4輸出傳回資 料 較電路41 〇比較在測试資料儲存元件4〇2中之測試資 127869.doc 200837556 料與傳回資料儲存元件404中之傳回資料且向測試傳回插 腳238提供輸出信號。每當在迴反操作完成時測試資料2 存元件402中之資料與傳回資料儲存元件4〇4中之資料匹酉 時，比較電路410可輸出「高」信號。 — 輔助塊204亦可具有兩個計數器以對迴反經起始之次數 (計數器1 408)及測試資料與傳回資料之間的匹配次數（，數 器2 4丨2)進行結算。處理器202可自計數器！ 4〇8及計數器 412接收資料並產生用於評估118]8]?11¥2〇6之測試結果。2 圖5展示將USB PHY配置成迴反模式並執行測試之動作 500。在動作502處，用於致能並起始迴反操作之處理器可 執行指令被載入ASIC之處理器中。該等指令宜包括用於向 可程式化暫存器或與USB PHY通信之其他儲存元件寫入資 料的寫入命令。舉例而言’該等指令可藉助於測試或除二 輸入236而載入，或可已預先載入並儲存於處理器之記= 體中。該等指令可包括用於測試迴反模式中之usb 指令。 、 在動作504處，USB PHY之控制位元經設定以致能處理 器來控制USB PHY之操作模式。在動作5〇6處，處理器向 與USB PHY之操作模式控制輸入通信的可程式化暫存器輪 出控制信號序列。在動作5G8處，將測 Γ測試資料可傳達自處理器、暫存器、記憶體或其他 來源。 二土方案中’猎由USB PHY完成之迴反操作之數目 I、，。异（動作51〇)，且成功迴反操作之數目經結算（動作 127869.doc 200837556 5 1 2)。成功迴反操作對應於使測試資料匹配傳回測試資 料。測試資料可輸出至處理器或其他設備。 以下同時建檔（2006年12月31日）之共同擁有的美國專利 申請案（由美國專利申請案序號「USSN」參考）以引用的方 式併入本文中：「Method for Configuring a USB PHY to Loopback Mode」（USSN 11/6 18，849且代理人參考號為 SDA-1095x(10519/203)) ;「Apparatus for Configuring a USB PHY to Loopback Mode」（USSN 1 1/618,852且代理人 參考號為 SDA-1095y( 10519/204)) ;「Method for Performing Full Transfer Automation in a USB Controller」(USSN 1 1/618,865 且代理人參考號為 SDA-1094x(10519/201)); 「USB Controller with Full Transfer Automation」（USSN 11/618,867 且代理人參考號為 SDA-1094y(10519/202)); 「Selectively Powering Data Interfaces」（USSN 11/649,325 且代理人參考號為 SDA-1076x) ;「Selectively Powered Data Interfaces」（USSN 11/649,326 且代理人參考號為 SDA-1076y) ;「Integrated Circuit with Protected Internal Isolation」（USSN 1 1/61 8,875且代理人參考號為80八-1090y) ;「Internally Protecting Lines at Power Island Boundaries」（USSN 11/618,874且代理人參考號為80八-1090x) ;「Module with Delay Trim Value Updates on Power-Up」（USSN 1 1/61 8,898且代理人參考號為80八-1091y) ;「Updating Delay Trim Values」（USSN 11/618,897 且代理人參考號為 SDA-1091x) ;「Systems and Integrated 127869.doc 11 200837556A choice is made between the materials to provide test data to the USB PHY 206 in a sequence as the backtest is enabled. The test data sequence can be modified by the processor 2〇2 or can be controlled by hardware. The engine auxiliary block 204 monitors and controls the test sequence. The test data communicated to the USB PHY 206 by the test logic circuit 414 is also maintained in the test data storage component 4〇2 in the engine auxiliary block 204. In the anti-reverse mode, USB ρΗγ 2〇6 serializes and deserializes the test data and returns the data storage component 4〇4 to the data storage component 4〇4 in the engine auxiliary block 2〇4. The test material 127869.doc 200837556 in the test data storage component 4 〇 2 feeds back the data in the data storage component 404 and provides an output signal to the test pass pin 238. The comparison circuit 410 can output a "high" signal whenever the data in the test data storage element 402 matches the data in the data storage element 4〇4 at the completion of the return operation. - Auxiliary block 204 may also have two counters to settle the number of times the backhaul is initiated (counter 1 408) and the number of matches between the test data and the returned data (number 2 4 丨 2). The processor 202 can be self-counting! 4〇8 and counter 412 receive the data and generate test results for evaluating 118]8]?11¥2〇6. 2 Figure 5 shows the action 500 of configuring the USB PHY to be in the reverse mode and performing the test. At act 502, the processor executable instructions for enabling and initiating the return operation are loaded into the processor of the ASIC. These instructions should include write commands for writing data to the programmable registers or other storage elements that communicate with the USB PHY. For example, the instructions may be loaded by means of a test or divide-by-two input 236, or may have been pre-loaded and stored in the body of the processor. These instructions may include a usb instruction for testing the bounce mode. At act 504, the control bits of the USB PHY are set to enable the processor to control the mode of operation of the USB PHY. At action 5〇6, the processor rotates the control signal sequence to a programmable register that communicates with the operational mode control input of the USB PHY. At action 5G8, test data can be communicated from the processor, scratchpad, memory, or other source. The number of backhaul operations performed by the USB PHY in the two soil schemes I,,. Different (action 51〇), and the number of successful reverse operations is settled (action 127869.doc 200837556 5 1 2). Successfully reversing the operation corresponds to passing the test data back to the test data. Test data can be output to a processor or other device. The co-owned U.S. Patent Application Serial No. (USSN), which is incorporated herein by reference in its entirety in its entirety in its entirety in the the the the the the the the the the the the Mode" (USSN 11/6 18,849 with agent reference number SDA-1095x (10519/203)); "Apparatus for Configuring a USB PHY to Loopback Mode" (USSN 1 1/618,852 and agent reference number SDA -1095y( 10519/204)) ; "Method for Performing Full Transfer Automation in a USB Controller" (USSN 1 1/618,865 and agent reference number SDA-1094x (10519/201)); "USB Controller with Full Transfer Automation" (USSN 11/618,867 with agent reference number SDA-1094y (10519/202)); "Selectively Powering Data Interfaces" (USSN 11/649,325 with agent reference number SDA-1076x); "Selectively Powered Data Interfaces" (USSN 11/649,326 with agent reference number SDA-1076y); "Integrated Circuit with Protected Internal Isolation" (USSN 1 1/61 8,875 and agent reference number 80-8-1090); "Internally Protecting Lines at Power Island Boundaries" (USSN 11/618,874 with agent reference number 80-8-1090x); "Module with Delay Trim Value Updates on Power-Up" (USSN 1 1/61 8,898 with agent reference number 80 Eight-1091y); "Updating Delay Trim Values" (USSN 11/618,897 with agent reference number SDA-1091x); "Systems and Integrated 127869.doc 11 200837556
Circuits with Inrush-Umited p〇wer Islands」（USSN 11/618,854且代理人參考號為SDA_1〇92y);及「[七出吨 Power Island Inrush CUrrent」（USSN 1 1/618,855且代理人 參考號為SDA-1092x)。 上文所有討論（不管所描述之特定實施）在性質上為例示 性的而非限制性的。舉例而言，儘管已描述ASIC之特定組 件，但符合ASIC之製造方法、系統及製品可包括額外或不 同組件。舉例而言，處理器可由以下一或多者實施··控制 邏輯、硬體、微處理器、微控制器、特殊應用積體電路 (ASIC)、離散邏輯，或電路及/或邏輯之組合。任何動作 或動作組合可在電腦可讀儲存媒體上儲存為指令。記憶體 可為DRAM、SRAM、快閃記憶體或任何其他類型之記憶 體。程式可為單-程式、獨立程式或越過若干記憶體及處 理器分布之部分。 儘官已描述了本發明之各種實施例，但對於熟習此項技 術者而言將顯而易見，在本發明之範疇内，許多其他實施 例及實施係可能的。因此，除依據附加請求項及其等效物 之外，本發明並不受限制。 【圖式簡單說明】 圖1為具有處理器及可由處理器配置成迴反模式之usb PHY的ASIC之方塊圖。 圖2為具有圖〗之組件及用於測試USB ρΗγ的組件與用於 支援記憶體儲存元件與USB ΡΗΥ之間的資料流之額外組件 的ASIC之方塊圖。 127869.doc -12- 200837556 圖3展示具有在可程式化暫存器中與圖2之USB PHY及處 理器通信的較佳之儲存位置集合的引擎輔助塊。 圖4為展示圖2之ASIC中用於測試USB PHY的較佳組件 之圖式。 圖5展示將USB PHY配置成迴反模式之動作方案。 【主要元件符號說明】 100 ASIC 102 處理器 104 迴反控制引擎 106 USB PHY 108 儲存元件 200 ASIC 202 處理器 204 引擎輔助塊 206 USB PHY 208 USB通信線 210 USB媒體存取控制電路（USB MAC) 212 介面模組 214 多工器 236 測試或除錯輸入 238 測試傳回插腳 300 迴反控制引擎 302 韌體USB PHY迴反致能暫存器 304 韌體USB PHY迴反控制暫存器 127869.doc -13- 200837556 306 308 310 312 314 316 320 322 324 400 402 404 408 410 412 414 致能（en)儲存位置 輸出致能（〇e)儲存位置 起始（in)儲存位置 鎖存器（lat)儲存位置 操作模式（mode)儲存位置 重設（re)儲存位置 時脈控制（cl)儲存位置 連接器 可程式化暫存器 測試組件 測試資料儲存元件 傳回資料儲存元件 計數器i 比較電路 計數器2 測試邏輯電路 127869.doc -14-Circuits with Inrush-Umited p〇wer Islands" (USSN 11/618,854 with agent reference number SDA_1〇92y); and "[7 out of Power Island Inrush CUrrent" (USSN 1 1/618,855 with agent reference number SDA) -1092x). All of the above discussion, regardless of the particular implementation described, is illustrative in nature and not limiting. For example, while specific components of an ASIC have been described, the ASIC-compliant manufacturing methods, systems, and articles of manufacture can include additional or different components. For example, a processor can be implemented by one or more of the following: control logic, hardware, microprocessor, microcontroller, special application integrated circuit (ASIC), discrete logic, or a combination of circuits and/or logic. Any action or combination of actions can be stored as instructions on a computer readable storage medium. The memory can be DRAM, SRAM, flash memory or any other type of memory. Programs can be single-program, stand-alone, or distributed across several memory and processor sections. Various embodiments of the invention have been described, but it will be apparent to those skilled in the art that many other embodiments and embodiments are possible within the scope of the invention. Therefore, the present invention is not limited except in addition to the appended claims and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of an ASIC having a processor and a usb PHY that can be configured in an anti-back mode by the processor. Figure 2 is a block diagram of an ASIC having components of the diagram and components for testing USB ρ γ and additional components for supporting data flow between the memory storage element and the USB port. 127869.doc -12- 200837556 FIG. 3 shows an engine auxiliary block having a preferred set of storage locations in communication with the USB PHY and processor of FIG. 2 in a programmable scratchpad. 4 is a diagram showing preferred components for testing a USB PHY in the ASIC of FIG. 2. Figure 5 shows the action scheme for configuring the USB PHY in an inverted mode. [Main Component Symbol Description] 100 ASIC 102 Processor 104 Back Control Engine 106 USB PHY 108 Storage Element 200 ASIC 202 Processor 204 Engine Auxiliary Block 206 USB PHY 208 USB Communication Line 210 USB Media Access Control Circuit (USB MAC) 212 Interface Module 214 Multiplexer 236 Test or Debug Input 238 Test Return Pin 300 Back Control Engine 302 Firmware USB PHY Back-Reversal Scratchpad 304 Firmware USB PHY Back-Reaction Control Register 127869.doc - 13-200837556 306 308 310 312 314 316 320 322 324 400 402 404 408 410 412 414 Enable (en) Storage position Output enable (〇e) Storage position Start (in) Storage position latch (lat) Storage position Operation mode (mode) storage location reset (re) storage location clock control (cl) storage location connector programmable program test component test data storage component return data storage component counter i comparison circuit counter 2 test logic circuit 127869.doc -14-