200835136 • 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種高頻率多相位之環振盪器，尤指以 新的裝置與方法藉由非全擺動信號的内插，來產生高頻 ^ 率多相位振盪器。 - 【先前技術】 多相位振盪器(multi-phase oscillator，MPO)在許多資 _ 料傳輸應用上扮演重要的腳色，目前已有提出許多方法 來實現多相位振盪器電路。例如，環振盪器(ring 〇scillato|^ 即疋一種備有奇數(odd)個反向器(inverter)串接的振蘯 為’因為奇數個層級串接，因此反向器輸出的信號則會 在尚(high)/低(low)間振盪。然而，傳統的環振盪器架構 只能產生奇數個多相位信號(multi-phase signal);而環振 盪益另外一個問題是，在環振盪器内串聯的反向器數目 φ 太多，將導致無法獲得高頻振盪。 美國專利5,592,126號揭露一種多相位輸出振靈器， 其包含一些振盪器電路以串連耦接方式形成環狀結構， 其中，每一個振盪器内更包括多個互連的反向器，此多 相位輸出振盤态結構可產生偶數個(even_number)多相位 訊號。 美國專利6,870,431號揭露一種具有多相位互補輪出 6 200835136 的振靈其包含_第—多個單端放大器串連以形成一 輸入端與—輸出端、—第二多個單端放大器串連以形成 輪入端與-輸出端。而此第一多個單端放大器與第二 多個單端放大器更透過回饋路徑(feedback path)與鎖定 電路(lockingCircuit)進一步互連，以產生多相位互補之信 號0 其它常見的方法是利用内插法（也稱作相位混合 (phase-blending))，在多個輸入信號中利用内插產生多相 位日守脈k號。苐一圖說明傳統單階(single_stage)相位混合 電路的一個示意圖。參考第一圖，此四個相位混合電路 (aHd)具有輸入信號φΑ、Φβ以及輸出信號φΑ、Φβ、 ΦΑΒ，其中^號φΑΒ是由信號(j)A、之間經過内插 而產生的。例如，IEEE Journal 〇f Solid-State Circuits, vol. 34, No. 5(May 1999)，揭露一種高速CM〇s介面電路的 可攜式(portable)數位延遲鎖定迴路(delay 1〇cked 1〇〇p， DLL) 〇 然而’内插法(interpolationapproach)有一個問題是， 通常在相位内插信號上，無法内插出精準的信號，這是 因為輸入信號為全擺動(foil swing)信號，要從兩個全擺動 相鄰輸入信號之間内插出精準位於兩相鄰相位訊號中間 的信號是很困難的。 7 200835136 -種常用轉決上述之她不精準_題，則是在 輸入L说上ί曰加負載(l〇ading)，如增加電容器。增加負載 可讓輸入仏歧成非全擺動(n〇n_full sw㈣信號，此可改 進信號内插時_位科度。例如麵】賴^ Solid-State Circuits, v〇l. 35, No. 11( November 2〇〇〇 } , ^ 露一種L3週期鎖定時間、非鎖相回路/延遲鎖定迴路時 脈乘法器’其根據α時脈週期内插產生即取時脈(d〇ek on de_d) ’但是此方法則會因外加的電容器其在製 I數的欠異所麵的獨賴電位偏移崎信號的 精準度降低。 、、丁上所述提供_種準確與穩定相位内插來產生多 相位信號以提供各種不同資料傳輸應用，並且可方便、 簡單製造的多相位振盪器是有其必要性。 【發明内容】 本毛月克服月ij述傳統多相位振盈器的缺點。本發明提 供一種以環振盈器產生多相位時脈信號(muiti_phase200835136 • IX. INSTRUCTIONS: [Technical Field] The present invention relates to a high-frequency multi-phase ring oscillator, and more particularly to a new device and method for generating high frequency by interpolation of a non-full swing signal ^ Rate multi-phase oscillator. - [Prior Art] Multi-phase oscillators (MPOs) play an important role in many resource transmission applications. Many methods have been proposed to implement multi-phase oscillator circuits. For example, the ring oscillator (ring 〇scillato|^ is a kind of oscillator with an odd number of inverters connected in series. 'Because the odd-numbered cascades are connected, the signal from the inverter will be Oscillation between high/low. However, the traditional ring oscillator architecture can only produce an odd number of multi-phase signals; another problem with ring oscillation is that it is in the ring oscillator. The number of inverters in series is too large, which will result in the inability to obtain high-frequency oscillations. U.S. Patent No. 5,592,126 discloses a multi-phase output oscillator comprising a plurality of oscillator circuits in a series coupling manner to form a ring structure, wherein Each of the oscillators further includes a plurality of interconnected inverters, and the multi-phase output oscillatory disc structure can produce an even number of (even_number) multi-phase signals. U.S. Patent No. 6,870,431 discloses a multi-phase complementary turn-out 6 200835136 The vibration includes a plurality of single-ended amplifiers connected in series to form an input terminal and an output terminal, and a second plurality of single-ended amplifiers are connected in series to form a wheel-in terminal and an output terminal. Single-ended amplifier Further interconnecting with the second plurality of single-ended amplifiers through a feedback path and a locking circuit to generate a multi-phase complementary signal 0. Another common method is to use interpolation (also known as phase mixing). Phase-blending)), using multiplication in multiple input signals to generate a multi-phase day-going k-number. One figure illustrates a schematic diagram of a conventional single-stage phase hybrid circuit. Referring to the first figure, the four phases The hybrid circuit (aHd) has input signals φ Α, Φβ and output signals φ Α, Φβ, Φ ΑΒ, where ^ φ ΑΒ is generated by interpolating between signals (j) A. For example, IEEE Journal 〇f Solid-State Circuits, vol. 34, No. 5 (May 1999), reveals a portable digital delay-locked loop (delay 1〇cked 1〇〇p, DLL) for a high-speed CM〇s interface circuit. One problem with the interpolation method is that it is usually impossible to interpolate the precise signal on the phase interpolation signal. This is because the input signal is a full swing signal, and the two input signals from the full swing are adjacent. It is very difficult to interpolate the signal accurately located in the middle of the two adjacent phase signals. 7 200835136 - The commonly used ones that turn to the above are not accurate _ questions, it is in the input L said 曰 曰 load (l〇ading ), such as adding a capacitor. Increasing the load allows the input to be non-fully swung (n〇n_full sw (four) signal, which can improve the signal interpolation time _ bit degree. For example, Lai ^ Solid-State Circuits, v〇l. 35, No. 11 ( November 2〇〇〇} , ^ reveals an L3 period lock time, non-phase-locked loop / delay-locked loop clock multiplier' The α clock cycle interpolation produces the instantaneous clock (d〇ek on de_d) 'But this method will reduce the precision of the offset signal by the external capacitor due to the applied capacitor. According to the above, it is necessary to provide a multi-phase oscillator which is accurate and stable phase interpolation to generate multi-phase signals to provide various data transmission applications, and which can be conveniently and simply manufactured. The present invention overcomes the shortcomings of the conventional multi-phase oscillator. The present invention provides a multi-phase clock signal generated by a ring oscillator (muiti_phase).
Msign蝴裝置與方法，其產生之信號的相位精準且 容易被控制。 本^月之以％振盪器產生多相位時脈信號的裝置與 ^法’不需外加電容器作為外加的負載來產生非全擺動 信號。由於不需外加電容器作為貞載，本發明可避免環 8 200835136 振盪為的製程中所造成的電路不穩定性。 本發明之以環振盪器產生多相位時脈信號的裝置包 S 弟 P白相位混合模組（first stage phase-blenderThe Msign device and method produce a precise and easily phased signal. The device and the method for generating a multi-phase clock signal by the % oscillator in this month do not require an external capacitor as an applied load to generate a non-full swing signal. Since no external capacitor is required as the load, the present invention can avoid the circuit instability caused by the oscillation of the ring 8 200835136. The apparatus for generating a multi-phase clock signal by a ring oscillator of the present invention is a first phase phase-blender module (first stage phase-blender)
module)與一第二階相位混合模組㈣⑺nd s吨e Phase_blendermodule)。而第一階相位混合模組更包括了 - 多個差動運算放大器相位混合電路(differential OP phaSe_blendCT drcuit) ’每一個差動運算放大器相位混合 電路備有2個輸入信號，以及一輸出信號，此輸出信號 的相位係内插介於兩個輸入信號之間。 第-P皆相位混合模組包括了多個反向器相位混合電 ^nvertef phase_bleiider drcuit)。每個反向器相位混合電 路触第H相贿麵組輸㈣兩個信號作為輸入信 號，並輸出-時脈信號，此時脈信號相位係内插於第一 φ 階相位混合模組輸出的兩個信號之間。 本發明也提伽環振靈n產好相位時脈信號的方 法’其包含下列步驟：⑴·使用-環振盡器以提供至 v兩個非全擺動信號；⑵·使用差動運算放大器相位 此口电路來此合由環振盘器產生的兩個非全擺動信號 的相位，以及，（3)•使用反向器相位混合電路來產生 具有内插相位的多相位時脈信號。 9 200835136 兹配合下列圖示、實施例之詳細說明及申請專利範 圍’將上述及本發明之其他目的與優點詳述於後。 【實施方式】 第二圖係本發明的第一個實施例，說明一環振盪器 產生3個相位時脈信號的一個示意圖。參考第二圖，此 可產生3個相位時脈信號的環振盪器包含3個延遲元件 (延遲元件1-延遲元件3)，其彼此串聯並產生信號phiji、 Phi一lb、Phi—2、Phi—2b、Phi—3、與 Phi一3b，其中信號 Phi—lb、Phi—2b、及 Phi」b 分別與信號 Phi_j、phi^、 及卩111—3具有相反的相位。而信號1>111_1、1^」1)、视2、 Phi一2b、Phi—3、與Phi一3b皆為非全擺動信號。 第三圖為本發明之另一實施例，說明一 2-階相位混 合益，其針對2個不同相位之輸入信號進行混相。此2_ • 階相位混合器利用2對非全擺動信號(PhiJ、Phi—2與其 互補的Phi—lb、Phi—2b信號)以產生3相位時脈信號。 P皆相位混合器包括了 _第—階相位混合模組與_第二階 相位混合模組。而第—階相位混合模組更包括了多個差 動運算放大ϋ相域合魏，每—個差純算放大器相 位混合電路接收2個輪入信號。 筝考第三圖，差動運算放大器相位混合電路301Α接 收㈣心」、PhiJb輸入，差動運算放大器相位混合電 200835136 路301B也接收信號Phi_l、Phi_lb輸入。同樣地，差動 運算放大器相位混合電路301E接收信號Phi_2、Phi_2b 輸入，差動運算放大器相位混合電路301F也接收信號 Phi一2、Phi-2b輸入。然而，差動運算放大器相位混合電 路301C其接收信號PhiJ、Phi_2b輸入，而差動運算放 大态相位混合電路301D接收信號phi_2、Phi__lb輸入。 差動運算放大器相位混合電路301A - 301F則分別輸出 信號 Phi—A、Phi—A、Phi ^B、Phi BA、Phi B、PM B。 進一步說明的是，信號Phi_A是信號Phi_l經過放大 後的信號，也就是說，信號Phi_A的相位與信號ph^ 的相位相同，而彳吕號Phi—A的振幅(ampiitude)則大於信 號Phi-1的振幅；同樣地，信號Phi_B是信號Phi_2經過 放大後的信號。差動運算放大器相位混合電路3〇1a、 301B、301E和301F最主要的目的是產生延遲，以補償 差動運算放大器相位混合電路3〇lc、3〇1D所造成的延 遲。 差動運算放大器相位混合電路3〇lc的輸出信號 朽11-^ ’其相位是由信號Phi一 1與Phi一2b經過内插而得 到；差動運算放大器相位混合電路301D的輸出信號Module) with a second-order phase mixing module (four) (7) nd s tons e Phase_blendermodule). The first-order phase mixing module further includes a plurality of differential operational amplifier phase mixing circuits (differential OP phaSe_blendCT drcuit). Each of the differential operational amplifier phase mixing circuits is provided with two input signals and an output signal. The phase of the output signal is interpolated between the two input signals. The first-P phase-mixing module includes a plurality of inverter phase hybrids (nnvertef phase_bleiider drcuit). Each inverter phase mixing circuit touches the (H) two signals of the H-phase bribe surface group as an input signal, and outputs a clock signal, and the pulse signal phase is interpolated in the output of the first φ-order phase mixing module. Between two signals. The present invention also provides a method for generating a phase clock signal by a gamma ring vibration, which comprises the following steps: (1) using a ring oscillating device to provide two non-full oscillating signals to v; (2) using a differential operational amplifier phase This port circuit is used to combine the phases of the two non-full swing signals generated by the ring oscillator, and (3) the inverter phase mixing circuit is used to generate a multi-phase clock signal having an interpolated phase. 9 200835136 The above and other objects and advantages of the present invention will be described in detail in the following description of the accompanying drawings. [Embodiment] The second figure is a first embodiment of the present invention, and illustrates a schematic diagram of a three-phase clock signal generated by a ring oscillator. Referring to the second figure, the ring oscillator which can generate three phase clock signals includes three delay elements (delay element 1 - delay element 3) which are connected in series and generate signals phiji, Phi-lb, Phi-2, Phi - 2b, Phi-3, and Phi-3b, wherein the signals Phi-lb, Phi-2b, and Phi"b have opposite phases to the signals Phi_j, phi^, and 卩111-3, respectively. The signals 1 > 111_1, 1^"1), 2, Phi-2b, Phi-3, and Phi-3b are all non-wobble signals. The third diagram is another embodiment of the invention illustrating a 2-stage phase mixing benefit for mixing phases of input signals of two different phases. The 2_ • phase mixer uses 2 pairs of non-full swing signals (PhiJ, Phi-2 and its complementary Phi-lb, Phi-2b signals) to generate a 3-phase clock signal. The P-phase mixer includes a _th-order phase hybrid module and a _ second-order phase hybrid module. The first-order phase hybrid module further includes a plurality of differential operation amplification ϋ phase domain convergence, and each of the difference pure amplifier amplifier phase mixing circuits receives two round-in signals. The third picture of the kite test, the differential operational amplifier phase mixing circuit 301 is connected to the (four) heart, the PhiJb input, and the differential operational amplifier phase hybrid 200835136, the road 301B also receives the signals Phi_l, Phi_lb input. Similarly, the differential operational amplifier phase mixing circuit 301E receives the signals Phi_2, Phi_2b inputs, and the differential operational amplifier phase mixing circuit 301F also receives the signals Phi-2, Phi-2b inputs. However, the differential operational amplifier phase mixing circuit 301C receives the signals PhiJ, Phi_2b, and the differential operation amplifier phase mixing circuit 301D receives the signals phi_2, Phi__lb. The differential operational amplifier phase mixing circuits 301A - 301F output signals Phi - A, Phi - A, Phi ^ B, Phi BA, Phi B, PM B, respectively. It is further explained that the signal Phi_A is the amplified signal of the signal Phi_l, that is, the phase of the signal Phi_A is the same as the phase of the signal ph^, and the amplitude of the Phi-A is larger than the signal Phi-1. Similarly, the signal Phi_B is the amplified signal of the signal Phi_2. The main purpose of the differential operational amplifier phase mixing circuits 3〇1a, 301B, 301E and 301F is to generate a delay to compensate for the delay caused by the differential operational amplifier phase mixing circuits 3〇lc, 3〇1D. The output signal of the differential operational amplifier phase mixing circuit 3〇lc is 11-^' whose phase is obtained by interpolating the signals Phi-1 and Phi-2b; the output signal of the differential operational amplifier phase mixing circuit 301D
Phl-BA，其相位是由信號Phi—2與Phi一lb經過内插而得 到。 11 200835136 第三圖内之第二階相位混合模組包括了多個反向器 相位混合電路，在此實施例中，每個反向器相位混合電 路更包括3個反向器。例如，反向器302A、302B、303A 形成一反向器相位混合電路，以混合信號Phi__A、 Phi—A，並產生一時脈信號Phij’ ，值得一提的是，而 信號Phi一 Γ的相位與信號phij、phi j的相位是相同 的。同樣的，時脈信號Phi_2，的相位與信號Phi_B、Phi_2 的相位是相同的。 另一方面，反向器3〇2C、302D、及303C形成一反 向為相位混合電路，以混合信號、phi_BA，並產 生一時脈信號PhiJ2，信號Phi_12的相位是由信號 PhU、Phi_2内插得來。因此，此2.相位混合器混合 了輪入信號Phi—1與ρμ_2並產生3個相位的時脈信號 PhU’、Phi—12、與 Phi—2，。 同樣地，此2-階相位混合器也可以用來混合兩個輸 入b虎Phi—2與Phi_3並產生3個相位的時脈信號 Phi—2, 、Phi—23、與Phi_3，；以及混合兩個輸入信號 Phi〜3與phi—1並產生3個相位的時脈信號、 Phi」i、與 Phij，。 第四圖為差動運算放大器相位混合電路之詳細電路 一個示意圖。參考第四圖，此差動運算電路備有輸入信 12 200835136 號v+與v-，並輸出一 v〇猶信號。以第三圖之差動運算 放大器相位混合電路301C為例子，因為信號Phi_2b(V-) 具有相位延遲以補償信號Phij(v+)，電晶體MN2延遲 著其電流之降低。因此，輸出信號Phi一AB(V〇ut)具有相 . -對於信號Phi_A之相位延遲，其中信號Phi—A是由差動 運算放大器相位混合電路301A與301B所輸出的信號。 Φ 相同的’如第三圖的差動運算放大器相位混合電路 301D，因為信號Phi_2(V+)具有相對於信號Phi_ib〇) 之相位延遲，電晶體_2在電晶體MN1之前將電流拉 低。因此，輸出信號Phi—AB(V〇ut)具有相對於信號Phi_B 之相位延遲，其中信號Phi—B是由差動運算放大器相位 混合電路301E與301F所輸出的信號。 信號Phi一AB與信號Phi__BA則透過反向器302C、 ® 302D、303C再次混合，以產生時脈信號Phi—12。值得 一提的是，由反向器302A、302B、303A組成的反向器 相位混合電路，與反向器302E、302F、303E組成的反 向器相位混合電路，都是用來補償延遲。 第五圖為說明使用以環振盪器來產生多相位時脈信 號的流程圖。參考第五圖，使用一環振盪器以提供至少 兩個非全擺動信號，如步驟501所示。使用多個差動運 异放大态相位混合電路來混合由環振盪器產生的兩個非 13 200835136 全擺動信號的相位，以產生不同組合，如步驟502所示。 最後，使用多個反向器相位混合電路來混合步驟5〇2所 輸出的信號，並產生具有内插相位的多相位時脈信號， 如步驟503所示。 惟，以上所述者，僅為發明之最佳實施例而已，當不 能依此限定本發明實施之範圍。即大凡一本發明申請專Phl-BA, whose phase is obtained by interpolating signals Phi-2 and Phi-lb. 11 200835136 The second-order phase mixing module in the third figure includes a plurality of inverter phase mixing circuits. In this embodiment, each inverter phase mixing circuit further includes three inverters. For example, the inverters 302A, 302B, and 303A form an inverter phase mixing circuit to mix the signals Phi__A, Phi-A, and generate a clock signal Phij'. It is worth mentioning that the phase of the signal Phi is The phases of the signals phij, phi j are the same. Similarly, the phase of the clock signal Phi_2 is the same as the phase of the signals Phi_B, Phi_2. On the other hand, the inverters 3〇2C, 302D, and 303C form a reverse phase mixing circuit to mix the signals, phi_BA, and generate a clock signal PhiJ2, and the phase of the signal Phi_12 is interpolated by the signals PhU and Phi_2. Come. Therefore, the phase mixer mixes the wheel signals Phi-1 and ρμ_2 and generates three phase clock signals PhU', Phi-12, and Phi-2. Similarly, the 2-stage phase mixer can also be used to mix two input b tigers Phi-2 and Phi_3 and generate three phase clock signals Phi-2, Phi-23, and Phi_3, and two The input signals Phi~3 and phi-1 generate three phase clock signals, Phi"i, and Phij. The fourth picture is a schematic diagram of the detailed circuit of the differential operational amplifier phase mixing circuit. Referring to the fourth figure, the differential operation circuit is provided with an input signal 12 200835136 v+ and v-, and outputs a v 〇 信号 signal. Taking the differential operation of the third diagram, the amplifier phase mixing circuit 301C is taken as an example, since the signal Phi_2b(V-) has a phase delay to compensate for the signal Phij(v+), and the transistor MN2 delays the decrease of its current. Therefore, the output signal Phi_AB(V〇ut) has a phase - a phase delay for the signal Phi_A, which is a signal output by the differential operational amplifier phase mixing circuits 301A and 301B. Φ The same as the differential operational amplifier phase mixing circuit 301D of the third figure, since the signal Phi_2(V+) has a phase delay with respect to the signal Phi_ib〇), the transistor 2 pulls the current low before the transistor MN1. Therefore, the output signal Phi_AB(V〇ut) has a phase delay with respect to the signal Phi_B, which is a signal output by the differential operational amplifier phase mixing circuits 301E and 301F. The signal Phi-AB and the signal Phi__BA are again mixed through the inverters 302C, ® 302D, 303C to generate the clock signal Phi-12. It is worth mentioning that the inverter phase mixing circuit composed of the inverters 302A, 302B, and 303A and the inverter phase mixing circuit composed of the inverters 302E, 302F, and 303E are used to compensate for the delay. The fifth diagram is a flow chart illustrating the use of a ring oscillator to generate a multi-phase clock signal. Referring to the fifth diagram, a ring oscillator is used to provide at least two non-full swing signals, as shown in step 501. A plurality of differential-optical-amplified phase mixing circuits are used to mix the phases of the two non-2008 35136 full wobble signals generated by the ring oscillator to produce different combinations, as shown in step 502. Finally, a plurality of inverter phase mixing circuits are used to mix the signals output in step 5〇2 and generate a multi-phase clock signal having an interpolated phase, as shown in step 503. However, the above description is only the preferred embodiment of the invention, and the scope of the invention is not limited thereto. That is, a special application for invention
利範圍所作之均等變化與修飾，皆應仍屬本發明專利涵 蓋之範圍内。 14 200835136 m * 【圖式簡單說明】 第一圖說明一個傳統單階相位混合電路的一個示意圖。 第二圖為本發明之實施例，說明應用本發明之環振盪器 產生3個相位信號的一個示意圖。 ， 弟二圖為本發明之另一實施例，說明一 2-階相位混合器， 其針對2個不同相位之輸入信號進行混相。 第四圖說明一差動運算放大器相位混合電路的一個示意Equivalent changes and modifications to the scope of the invention are still within the scope of the invention. 14 200835136 m * [Simple description of the diagram] The first diagram illustrates a schematic diagram of a conventional single-stage phase hybrid circuit. The second diagram is a schematic diagram showing the generation of three phase signals by applying the ring oscillator of the present invention to an embodiment of the present invention. FIG. 2 is another embodiment of the present invention, illustrating a 2-stage phase mixer that performs phase mixing for input signals of two different phases. The fourth figure illustrates a schematic of a differential operational amplifier phase hybrid circuit
第五圖是本發明以環振盪器產生多相位時脈信號的運作 流程圖。 【主要元件符號說明】 ΦΑ、ΦΒ、ΦΑΒ 信號____ Phi—1、Phi—lb、Phi—2、Phi—2b、Phi—3、Phi—3b、Phi—A、Phi_AB、 Phi—B、Phi 1，、Phi—12、Phi—2，信號 301A、301B、301C、301D、301E、301F 差動運算放大器相位 混合電路__ 302A - 302F、303A-303E 反向器_______ MN1、MN2、MP1、MP2 電晶體 Vdd、Vout、V+、V-信號_ 501使用一環振盪器以提供至少兩個非全擺動信號_ 502使用多個差動運算放大器相位混合雷路來混合由環振盪器 15 200835136The fifth figure is a flow chart showing the operation of the multi-phase clock signal generated by the ring oscillator of the present invention. [Description of main component symbols] ΦΑ, ΦΒ, ΦΑΒ Signals ____ Phi-1, Phi-lb, Phi-2, Phi-2b, Phi-3, Phi-3b, Phi-A, Phi_AB, Phi-B, Phi 1 , Phi-12, Phi-2, Signals 301A, 301B, 301C, 301D, 301E, 301F Differential Operational Amplifier Phase Mixing Circuit__ 302A - 302F, 303A-303E Inverter _______ MN1, MN2, MP1, MP2 The transistors Vdd, Vout, V+, V-signal_501 use a ring oscillator to provide at least two non-full swing signals _ 502 using a plurality of differential operational amplifier phase mixing ramps to be mixed by the ring oscillator 15 200835136
產生的兩個非全擺動信號的相位，以產生不同組合 503使用多個反向器相位混合電路來混合步驟502所輸出的信 號，並產生具有内插相位的多相位時脈信號 16The resulting two non-wobbled signals are phased to produce different combinations 503 using a plurality of inverter phase mixing circuits to mix the signals output in step 502 and to generate a multi-phase clock signal having an interpolated phase.