TW200834427A - Storage medium with stackable component structure - Google Patents

Abstract

A storage medium with a stackable component structure is disclosed, which comprises: a carrier having a first surface and a second surface opposite to the first surface; a control integrated circuit installed on the first surface of the carrier, wherein the control integrated circuit is arranged such that the conductive contact thereof is electronically connected to a corresponding circuit track on the first surface; a first memory installed on the first surface of the carrier, wherein the first memory is arranged such that its conductive contact is electronically connected to a corresponding circuit track on the first surface; a second memory partially superimposed on the first memory so as to keep the conductive contact thereof from being covered by the first memory, wherein the conductive contact of the second memory is electronically connected to a corresponding circuit track on the first surface; and a case covering the carrier, the control integrated circuit and the memories, wherein the case has a plurality of through holes used for being exposed to a corresponding circuit track of the second surface.

Description

200834427 IX. Description of the Invention: Field of the Invention The present invention relates to a storage medium body having a stacked element structure. BACKGROUND OF THE INVENTION In recent years, the demand for memory cards such as MMC, SD, MINI-MMC, MINI-SD, etc. has continued to increase with the popularity of consumer products such as digital cameras, digital cameras, mobile phones, and MP3 10 . These memory cards have a similar structure, as shown in the twentieth and twenty-first figures, a conventional SD memory card is exemplified. Referring to the twentieth and twenty-first figures, the SD memory card has a printed circuit board 11 as a lower cover, a memory 12, a control integrated circuit 13, and a plurality of circuits for external use ( The external connection electrode 14 and the upper cover 1 are electrically connected. The printed circuit board 11 has a component mounting surface 11A, a back surface 111 opposite the component mounting surface 110, and a predetermined circuit trace pattern (not shown) disposed on the component mounting surface 110. The memory 12 is mounted on the component mounting surface 11A of the printed circuit board 11 by, for example, flip chip so that its conductive contacts (not shown) are the components on the printed circuit board 11. The corresponding circuit trace pattern on the mounting surface 11 is electrically connected. The control integrated circuit 13 is mounted on the component mounting surface 110 of the printed circuit board 11 of, for example, flip chip so that its conductive contacts (not shown) are on the printed circuit board 13 [The corresponding circuit trace pattern on the component mounting surface 11 is electrically connected. - the external connection electrodes 14 commonly referred to as gold fingers are disposed on the back surface 111 of the printed circuit, the 5-way board 11 and are disposed on the component mounting surface 11 of the printed circuit board 11 in a suitable manner. Corresponding circuit trace patterns are electrically connected. The upper cover 10 has a shape matching the printed circuit board 11 and is combined with the printed circuit board in an appropriate manner. 10 However, the memory card described above has the disadvantage that the area of the printed circuit board 11 is usually designed to accommodate two memory 12s in the size allowed by the memory card, see printing in the twenty-first figure. The dashed area of the board 11 is such that the memory card manufacturer can view the desired valley and install one or two memories on the board 11. However, as the size of the memory card becomes smaller and smaller, the area of the circuit board 11 cannot be accommodated. • Two counts 12 are arranged side by side, so the capacity cannot be expanded as needed. In view of this, the inventor of this case has been actively researching and improving with the spirit of excellence in the industry for many years of experience in the industry, and has produced the invention and a storage medium with a stacked component structure. 20 SUMMARY OF THE INVENTION An object of the present invention is to provide a storage medium having stacked memories. According to a feature of the invention, a storage medium 200834427 having a stacked component structure is provided, the storage medium comprising: a carrier having a first surface and a second surface opposite the first surface Forming, on the first surface and the second surface, predetermined circuit traces respectively, the circuit traces on the first surface and the corresponding circuit traces on the second surface being electrically 5 connected to each other; a control integrated circuit mounted on the first surface of the carrier, the control integrated circuit being configured such that its conductive contacts are electrically connected to corresponding circuit traces on the first surface; a first memory on a first surface of the carrier, the first memory being configured such that a conductive contact thereof is electrically connected to a corresponding circuit trace on the first surface; a portion 10 a second memory stacked on the first memory such that the conductive contacts thereof are not covered by the first memory, and the conductive contacts of the second memory are corresponding to the first surface Circuitry electrical connection; and a housing encasing the carrier, the control integrated circuit and the memory, the housing being formed with a plurality of through holes for corresponding circuit traces exposed on the second surface of the carrier . According to another feature of the invention, a storage medium having a stacked component structure is provided, the storage medium comprising: a carrier having a first surface, a second surface opposite the first surface, And a through hole penetrating the carrier, wherein the first surface and the second surface are respectively formed with predetermined circuit traces, and the track of the circuit track 20 on the first surface corresponds to the second surface The circuit traces are electrically connected to each other; a surface formed on the first surface of the carrier such that the surface on which the conductive contact is formed is a memory accessible through the through hole, and the conductive contact of the memory is Corresponding circuit traces on the first surface of the carrier are electrically connected. On the surface of the memory formed with the conductive contacts, a circuit trace of a predetermined 200834427 is formed, which is a shaped conductive contact mounted on the memory. a surface of the control integrated circuit located within the through hole, the control integrated circuit being a circuit trace on a surface of the memory formed with a conductive contact Air connections, and - a coating of the carrier, the control housing and the integrated circuit memory 5, the through hole formed in the housing of the circuit traces for several exposed on the second surface of the carrier corresponding to the sum of. Low material (four) and force....does (four) (four) component knot:

The storage medium is provided with a 'brittle media containing: a carrier having a first surface, a second one facing the first surface, and a through hole extending through the carrier. The first surface and the second surface are divided into predetermined circuit traces, and the path traces on the first surface and the corresponding (four) rails on the second surface are electrically mounted on the carrier - The conductive contact on the surface of the control integrated circuit is electrically connected to a circuit trace on the first surface of the carrier; a via body disposed in the via of the carrier, the first memory having a surface body formed with a conductive surface: a second memory on the surface of the first memory formed with the conductive contact and the first surface of the body, the second memory being the second memory The conductive contact of the body is * this configuration. 20 conductive contacts and the corresponding 1 connection in the memory of the carrier.

Connecting, and - wrapping the carrier, the control integrated circuit and the I =: the outer casing is formed with a plurality of through holes for exposing the corresponding circuit traces on the carrier: the =. </ RTI> </ RTI> According to the present invention, there is a stacked component connection; 200834427 * * 储存 The storage medium is handled, and the deposit medium includes: a carrier having a first surface, a second surface opposite the first surface, and a through hole penetrating the carrier, the first surface and the second surface of the second surface are on the surface of the first surface The upper electric, & (4) and the corresponding circuit lion on the second surface of the 4 are electrically connected to each other; a memory placed in the through hole of the carrier, the memory having a conductive contact formed and Corresponding to the surface of the predetermined contact path of the conductive contact, the circuit trace on the surface of the record is electrically connected to the corresponding circuit trace on the first surface of the carrier via the conductor a control integrated circuit mounted on a surface of the memory formed with a conductive contact, the control integrated circuit being configured such that the conductive contact of the control integrated circuit is on the surface of the memory Corresponding circuit trace electrical Bonding; and - a cover that depends on the control housing of the integrated circuit and memorized body 'of the housing is formed a through hole for several circuit traces 15 exposed on the second surface of the carrier corresponding to the sum of the. • A further feature of the invention is that a storage medium having a stacked component structure is provided, the storage medium comprising: a first carrier having a first surface and a first - a surface opposite the surface of the first surface and the second surface of the first carrier are respectively formed with a pre-twisted circuit trace, a circuit trace on the first surface and a corresponding circuit on the first surface The tracks are electrically connected to each other; a second carrier partially overlapping the first carrier, the second carrier having a first I face and a second surface opposite the first surface, the second carrier The first surface and the second surface are respectively formed with predetermined circuit traces, and the circuit traces on the first surface and the corresponding circuit traces on the second surface are electrically connected to each other, in the second carrier The circuit trace on the second surface is a circuit trace corresponding to the first surface of the first carrier • 5 k connection; a control product mounted on the first surface of the first carrier, _ Road 'the (four) integrated circuit is Arranged such that the control integrated circuit _ electrical contact is electrically connected to a corresponding circuit trace on the _th surface of the gamma; a _ mounted on the first surface of the second carrier a memory, the first memory being configured such that the conductive contacts of the first memory are electrically connected to circuitry corresponding to the first surface of the second carrier; a second money on the second surface of the second carrier, the body of the second domain is § &amp; such that the conductive contact 疋 of the second memory is on the second surface of the second carrier Corresponding circuit traces are electrically connected, and a casing encasing the carrier, the control integrated circuit and the memory, the casing is formed with a plurality of corresponding surfaces for exposure on the second surface of the carrier The through hole of the circuit trace. According to a re-characteristic of the present invention, a memory medium having a stacked component structure is provided, the storage medium comprising: a carrier, the carrier having a plurality of conductive pins, and a mounting on the carrier a first memory, such as a first memory having a surface formed with a conductive contact and a circuit trace electrically connected to the corresponding conductive contact, the first register being configured such that the first memory The conductive contact is electrically connected to the corresponding conductive connection of the carrier, a second memory mounted on the first memory, the second memory has a conductive contact formed and corresponding The surface of the circuit trace of the conductive contact is electrically connected, the second memory is configured to 200834427, the conductive contact of the second memory is connected with (4), v ', the conductive contact Wei; - a 4-body a control integrated circuit on the surface of the corresponding trace, the control integrated body 2 = west so that the conductive contact of the control integrated circuit is electrically connected to the second corresponding circuit trace; and - a package Overlay (four) body circuit and the outside of the memory Control product &amp; form several through hole for exposing the corresponding surface of the support of two of Ti circuitry traces. - According to still another feature of the present invention, a storage medium read and provided with a stack of component structures ίο 15 20, the storage medium comprising: a carrier having a first surface and a a second surface opposite the first surface is formed with a predetermined circuit trace on a first surface of the carrier, and a second surface of the carrier is formed with a scale interface circuit and a predetermined circuit trace a circuit trace on the first surface and a corresponding circuit trace and a special purpose interface circuit on the second surface are electrically connected to each other; a control integrated circuit mounted on the first surface of the carrier, The control integrated circuit is configured such that the conductive contacts of the control integrated circuit are electrically connected to corresponding circuit traces on the first surface of the carrier, a memory mounted on the first surface of the carrier The memory cartridge is configured such that the conductive contacts of the § memory are electrically connected to corresponding circuit traces on the first surface of the carrier; and a cladding carrier, the control integrated circuit and Memory of the housing, the housing is formed with several through hole for a corresponding exposure of the upper surface of the support of the second circuit traces is performed. According to still another feature of the present invention, a method of fabricating a storage medium is provided, the method comprising the steps of: conducting a memory in a memory 11 200834427 ^ - * . ^ « * , · mounting a contact mounting surface Controlling the integrated circuit, on the conductive contact mounting surface of the memory, a predetermined circuit trace is mounted with a plurality of conductive contacts and electrically connected to the corresponding conductive contacts, the control integrated circuit is configured to be The conductive contact is electrically connected to the corresponding '5 t road lion on the surface of the navigation (4); (4) the sewing body is on the lead frame so that (4) the conductive contact of the memory corresponds to the lead frame The conductive pin is electrically connected, and the outer casing is covered with the memory, the control integrated circuit and the conductive pin of the wire guide, and the outer casing is formed with a plurality of corresponding portions for exposing the lead frame A through hole in one of the conductive pins. 10 is a brief description of the technical means and the efficacy of the present invention for achieving the above objects and features, and a preferred embodiment is described below with reference to the following drawings: Figure 1 is a first preferred embodiment of the present invention A schematic partial cross-sectional view of a #t storage with a stacked component structure; 15 胄2 is a stacked-type element of the present invention

A schematic bottom plan view of a storage medium of a structure; the figure is a schematic view of a bribe of a stacked structure having a stacking structure according to a second preferred embodiment of the present invention; The preferred embodiment has a stack of 20 pieces of structure read memory frequency private parts; the fifth figure is a schematic partial cross-sectional view of a storage medium having a stack structure according to a fourth preferred embodiment of the present invention; Figure 5 is a schematic partial cross-sectional view of a storage medium having a stack structure in accordance with a fifth preferred embodiment of the present invention;

12 200834427 » FIG. 7 is a schematic partial cross-sectional view of a storage medium having a stacked component structure according to a sixth preferred embodiment of the present invention; and FIG. 8 is a stacked view showing a seventh preferred embodiment of the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 9 is a schematic partial cross-sectional view of a storage medium having a stacked component structure according to an eighth preferred embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 11 is a schematic partial cross-sectional view of a storage medium having a stacked element structure according to a ninth preferred embodiment of the present invention; FIG. 11 is a storage of a stacked 1-inch element structure according to a tenth preferred embodiment of the present invention; A schematic partial cross-sectional view of a medium; a twelfth drawing is a schematic bottom plan view of a storage medium having a stacked component structure according to a tenth preferred embodiment of the present invention; and a thirteenth drawing showing a tenth embodiment of the present invention A schematic perspective view of the storage medium of the preferred embodiment placed in a mounting seat; and FIG. 14 and FIG. 15 are diagrams showing the φ storage medium of the tenth preferred embodiment of the present invention used in 1C crystal A schematic plan view on the card; Fig. 16 is a schematic plan view showing the tenth preferred embodiment of the present invention, the storage medium is used on the IC chip card; • The material seven to nineteen is (four) A schematic diagram showing the method of manufacturing the storage medium of the present invention; FIG. 10 is a schematic exploded view of a conventional storage medium; and _th-10th is a storage showing the seventeenth figure. A schematic plan view of the back of the media. 13 200834427 [Detailed Description of the Preferred Embodiments] _ In the following, the detailed description of the present invention is the same as that of the similar elements.

10 will be omitted. The details of the present invention are disclosed in detail in the accompanying drawings. The storage medium having the stacked 7G structure of the first preferred embodiment of the present invention comprises a first carrier, a second carrier 2, and a control integrated circuit (shown in FIG. 2 and FIG. Control IC) 3. First and second memory bodies 4 and 5, and a housing 6. The first carrier 1 can be a printed circuit board or a lead frame. In this embodiment, the first carrier 1 is a printed circuit board and has a first surface 10 provided with a pre-twisted circuit trace (not shown) and an external connection electrode provided with a plurality of gold fingers. The second surface u of 110. The circuit traces on the first surface 10 of the first surface are electrically connected to the corresponding electrodes 110 on the second surface 11 in a suitable manner. In the present embodiment, the control 1C 3 is flip-chip mounted on the first surface 10 of the first carrier 1 so as to form a conductive contact on the conductive-contact mounting surface 30 of the control 1C 3 . The point is electrically connected to the circuit trace on the first surface 1〇. It should be noted that on the other surface ίο of the carrier 1, a plurality of passive elements 7 like resistors and capacitors are mounted in the same manner as the control 1C3. The second carrier 2 can be a printed circuit board or a lead frame. In the example of the implementation of the 2008 200834427, the second carrier 2 is a printed circuit board and the county has a first surface 20 provided with a predetermined circuit trace (not shown) and a predetermined circuit trace (in the figure). The second surface 21 is not shown. The circuit trace on the first surface 20 is electrically connected to the circuit trace corresponding to 5 on the second surface 21 in a suitable manner. In the present embodiment, the circuit trace on the second surface 21 of the second carrier 2 is electrically connected via a conductor 8 to a circuit trace corresponding to φ on the first surface 10 of the first carrier 1. In this embodiment, the first memory 4 is flip-chip mounted on the first surface 20 of the 10 second carrier 2 so as to be formed on the conductive contact mounting surface 40 of the first memory 4. The conductive contact 41 is electrically connected to a corresponding circuit trace on the first surface 2〇, and the second memory 5 is also flip-chip mounted on the second surface 21 of the second carrier 2 such that The conductive contacts 51 formed on the conductive contact mounting surface 50 of the second memory 5 are 15 electrically connected to corresponding circuit traces on the second surface 21. ^ The outer casing 6 is a through hole 60 in which all of the above-described elements are housed and has a plurality of exposed electrodes 110. As such, the storage medium having the stacked component structure of the first embodiment of the present invention is completed. Referring to the third embodiment, the storage medium having the structure of 20 stacks of the second embodiment of the present invention is not included in a carrier 1, a control 1C 3, a memory 4, And a casing 6. The carrier 1 can be a printed circuit board or a lead frame. In the present embodiment, the carrier 1 is the same as the first carrier 1 in the first embodiment except that the carrier 1 is formed with a through hole 12 in a predetermined region. 15 200834427 Electricity. » * In the present embodiment, the memory 4 is flip-chip mounted on the first surface 10 of the carrier 1 such that its conductive contact mounting surface 4 is via the through hole 12 The conductive contacts 41 that enter and exit and thus are formed on the surface 4 are electrically connected to the circuit traces corresponding to the first surface 10 of the carrier 1. The control 1C 3 is flip-chip mounted on the surface 4 of the memory 4 such that the control 1C 3 is located within the via 12 and so that the conductive contact 31 of the control φ 1C 3 is Corresponding circuit traces on the surface 40 of the memory 4 are electrically connected. A plurality of passive components 7 are also mounted on the surface 40 of the memory 4 in a manner similar to the control 1C3. Similar to the first preferred embodiment, the outer casing 6 is a through hole 60 〇 15 in which all of the above-described elements are housed and has a plurality of exposed electrodes 11 第四. The fourth figure shows the third aspect of the present invention. A storage medium having a stacked meta-component structure of the preferred embodiment. Different from the second preferred embodiment, the storage medium of the embodiment further includes a second memory 5 and is electrically formed on the second surface 11 of the carrier 1 and the corresponding electrode 110 in this embodiment. The predetermined circuit trace of the connection (not shown). The second memory 5 is mounted on the second surface 11 of the carrier 1 in a flip chip manner so that the conductive contacts 51 formed on the conductive contact mounting surface 50 are the second ones in the carrier The corresponding electrodes 11 on the surface 11 are electrically connected. It should be noted that, in this embodiment, the second memory 5 is displayed symmetrically with respect to the carrier 1 and the first memory 4, however, the second memory 5 may not be 16 200834427 * » ^ * . The first memory 4 is symmetrically set. Fig. 5 is a schematic cross-sectional view showing a storage medium having a stacked 70-piece structure showing a fourth preferred embodiment of the present invention. In the present embodiment, the storage medium includes a carrier 1, a control IC 3, first and fifth memories 4 and 5, and a casing 6. The carrier 1 can be a printed circuit board or a lead frame. In the present embodiment, the carrier 1 is the same as the first carrier 第二 in the second embodiment. φ In the present embodiment, the control IC 3 and the passive elements 7 are mounted on the first surface 1 of the carrier as in the first embodiment. The first memory 4 is disposed in the through hole 12 of the carrier 1 and is formed on the conductive contact mounting surface 40 thereof with a conductive contact 41 and a predetermined circuit electrically connected to the corresponding conductive contact 41. Track (not shown). • * * The second memory 5 is flip-chip mounted on the first surface 10 of the carrier and the conductive contact forming surface 4 of the first memory 4 such that the 15 second memory The conductive contacts 51 of 5 are electrically connected to corresponding circuit traces on the first φ surface 10 of the carrier and corresponding circuit traces on the surface 40 of the first memory 4. • Figure 6 is a schematic partial cross-sectional view showing a storage medium having a stacked component structure in accordance with a fifth preferred embodiment of the present invention. Different from the fourth preferred embodiment, the second memory 5 is mounted only on the surface 40 of the first memory 4 such that the conductive contacts 51 of the second memory 5 are in the first memory. Corresponding circuit traces on surface 40 of body 4 are electrically connected. The circuit traces on the surface 40 of the first memory 4 are electrically connected via conductors 8 to corresponding circuit traces on the surface 10 of the carrier 1. 17 200834427 * The seventh figure is a schematic partial cross-sectional view of a storage medium having a stack-up element structure showing a sixth preferred embodiment of the present invention. The storage medium of this embodiment includes a carrier, a control IC 3, first and second memory bodies 4 and 5, and a casing 6. The carrier 1 can be a printed circuit board or a lead frame. In the present embodiment, the carrier 1 is the first carrier in the first embodiment! the same. In addition, in the present embodiment, the first memory 4, the control ic3, and the plurality of passive components 7 are mounted on the wafer as described above (4) - the surface 10 is 0 10 15 20 5 is a portion of the conductive impurity 51 which is not overlapped on the first memory 5 and has a conductive contact trace 8 corresponding to the surface 1G of the surface 1 The circuit rail portion is similar to the preferred embodiment. The outer casing 6 is centered on the components described above; and has a plurality of through holes 60 for exposing the corresponding electrodes 110. </ RTI> Referring to the storage medium having the structure of the seventh preferred embodiment of the present invention, which is shown in the drawings, is shown. In the present embodiment, the body includes a na, a control IC 3, first and second memories 4 and 5, and a casing 6. The j-plant 1 can be a printed circuit board or a lead frame. In this embodiment, the carrier 1 is a lead frame having a plurality of conductive pins. The fifth memory layer 4 is mounted on the conductive pins of the carrier 1 via the conductor 8 so that the conductive contacts 41 of the first memory 4 are electrically connected to the corresponding conductive pins. The first memory 4 is at the edge of the shape 18 200834427 ft &quot; ο * • * is formed with a plurality of plating recesses 42 electrically connected to the corresponding conductor 8''. The second memory 5 is flip chip The first memory 4 is mounted on the first memory 4 via the conductor 8, so that the conductive contact 51 of the second memory 5 is electrically connected to the corresponding plating recess 42 of the first memory 4. The body 5 4 is identical, and the second memory 5 is formed at its edge with a plurality of plated four grooves 52 electrically connected to the corresponding conductor 8''. In addition, the second memory body 5 and the conductive contact mounting surface The opposite surface 53 of the 50 is formed with a predetermined circuit trace (not shown) electrically connected to the corresponding plating recess 52. The control 1C 3 and the passive components 7 are covered by the above-mentioned crystal. The type 10 is mounted on the surface 53 of the second memory 5. Similar to the first preferred embodiment The outer casing 6 is a through hole 60 for accommodating all of the above-mentioned components and having a plurality of exposed conductive pin portions. Referring to the ninth embodiment, the eighth preferred embodiment of the present invention The storage medium having the structure of 15 stacked components is shown in the embodiment. In the embodiment, the storage medium includes a carrier 1, a control 1C 3, a memory 4, and a housing 0. The carrier 1 may be a printed circuit board or a lead frame. In the present embodiment, the crucible carrier 1 is a lead frame having a plurality of conductive pins. 20 The memory 4 is flip-chip as in the seventh embodiment. Mounted on the conductive pins of the carrier via conductors 8. A predetermined circuit trace is formed on the surface 43 of the memory 4 opposite the conductive "women's surface 40" (not shown). In this embodiment, the conductive pin of the carrier has an inverted L-shaped extension that extends upwardly and is electrically connectable to a corresponding track 19 on the surface 43 of the memory 4. The control 1C 3 and the material passive element 7 are mounted on the surface 43 of the memory 4 in a flip chip manner as described above. • The embodiment is similar, and the difference 6 is to listen to all of the above. And a plurality of through holes 60 having a portion of the conductive pins exposed to the corresponding ones. FIG. 10 is a storage medium having the structure of the element structure of the ninth preferred embodiment of the present invention. A schematic partial cross-sectional view. Unlike the fifth embodiment, the control button 3 and the passive element 7 of the present embodiment are mounted on the surface 40 of the memory 4 in a flip chip manner as described above. Figure 12 is a schematic plan view showing a storage medium having a Utg structure in accordance with a tenth preferred embodiment of the present invention, and a tenth view showing a schematic partial sectional view of the storage medium of the twelfth embodiment. . As shown in the tenth and twelfth drawings, the storage medium pack 15 of the present embodiment includes a carrier i, a control IC 3, first and second memory systems, and φ a casing 6. The carrier 1 can be a printed circuit board or any board made of a suitable material. The carrier 1 has a first surface 10 and a second surface u. • A predetermined circuit trace (not shown) is formed on the first surface 10. A 20th external-connecting electrode U1 and a plurality of second external connecting electrodes (10) are formed on the second surface 11 and they are electrically connected to the corresponding circuit traces on the first surface 10 in a conventional manner. connection. In this embodiment, the first external connection electrode lu is an electrode generally used on a SIM card, and the second external connection electrodes are electrodes used on a memory card for a 2008. The control 1C 3, the memories 4, 5 and the passive elements 7 are mounted on the first surface 1 of the carrier in a flip chip manner as described above. Fig. 12 shows the state of use of the storage medium of the tenth embodiment. • 5 As shown, the storage medium is placed in a card mount s that is placed on the PCB unit PCB of the mobile phone. The fourteenth and fifteenth figures show another application of the tenth preferred embodiment of the present invention. As shown in the figure, in the embodiment, the first external connection electrode m of the storage medium is an electrode generally used on an ic card, and the storage medium is slidably disposed on the IC card. The body (10) is such that when the storage medium is placed in the memory to make it secret (see the second external connection electrode 11G, which is suitable for electrical connection with an external circuit (not shown)), the memory can be achieved. The access operation of the body. The sixteenth figure shows another use of the tenth preferred embodiment of the present invention. As shown in the figure of the first and the first cut (four), in this application, the body B is Forming a through hole Bh and the storage medium is pivotally connected to the body B such that the storage medium is rotatable between a use position of the IC card in a memory use position, in the memory In the use position, the storage medium is perpendicular to the body B. In the use position, the medium is parallel to the age and placed in the through hole. Referring to the seventeenth to nineteenth As shown, the manufacturing method of the storage medium of the present invention is disclosed. As shown in the drawing, the memory contact mounting surface 4 () of the memory body is provided with a conductive contact η and a predetermined circuit trace electrically connected to the corresponding conductive contact 41 (not shown in the figure) 200834427. _ shows). Then, a control IC3 and a plurality of passive components 7 are mounted on the conductive contact mounting surface 4 of the memory 4 in a flip chip manner as described above such that their conductive contacts (Fig. (not shown) is electrically connected to a corresponding circuit trace on the conductive contact mounting surface 40 of the memory 4. 5, then the memory 4 is mounted on the lead frame 1 in a flip chip manner as described above. So that the conductive contacts 41 of the memory 4 are electrically connected to the corresponding pins of the lead frame. φ Next, a housing 6 in which all of the above-described components are housed is formed. 6 has a part of several conductive pins corresponding to the exposure: 10 holes 60. m In summary, the "the library with the stacked component structure.. storage media" can indeed be disclosed by the above. Structure and device to achieve the intended purpose and efficacy' It has not been disclosed in the publication before the application, and it is not in public use. It is in accordance with the novelty, progress and other requirements of the invention patent. '15 However, the drawings and descriptions disclosed above are only for the embodiments of the present invention. EXAMPLES; Other equivalent changes or modifications made by the person skilled in the art, which are based on the characteristics of the present invention, should be included in the scope of the patent application of the following case. [Simplified illustration] BRIEF DESCRIPTION OF THE DRAWINGS The first drawing is a schematic partial cross-sectional view of a storage medium having a stacked component and a structure according to a first preferred embodiment of the present invention. The figure is a stacked-type thousand according to a first preferred embodiment of the present invention. A schematic bottom plan view of a storage medium of the present invention; * FIG. 7C is a schematic cross-sectional view of a storage medium having a stacking element 22 200834427 » * . Is a schematic partial cross-sectional view of a storage medium having a stacked component structure according to a third preferred embodiment of the present invention; • FIG. 5 is a stacked component of the fourth preferred embodiment of the present invention. FIG. 6 is a schematic partial cross-sectional view of a storage medium having a stacked component structure according to a fifth preferred embodiment of the present invention; and FIG. 7 is a sixth preferred embodiment of the present invention. FIG. 1 is a schematic partial cross-sectional view of a storage medium having a stacked component structure according to a seventh preferred embodiment of the present invention; 9 is a schematic partial cross-sectional view of a storage medium having a stacked component structure according to an eighth preferred embodiment of the present invention; FIG. 10 is a storage of a stacked component structure according to a ninth preferred embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 11 is a schematic partial cross-sectional view of a storage medium having a stacked 70-piece structure according to a tenth preferred embodiment of the present invention; A schematic bottom plan view of a preferred embodiment of a storage medium having a stacked, component structure; and FIG. 13 is a storage medium showing a tenth preferred embodiment of the present invention. A schematic perspective view placed in a mount; fourteenth and fifteenth views are schematic plan views showing a storage medium for use in a tenth preferred embodiment of the present invention for use on a 1C wafer card; Show another embodiment of the storage device of the tenth preferred embodiment of the present invention. 200834427 - another schematic plan view of the storage medium for use on an ic wafer card; and seventeenth to nineteenth views are schematic views showing a method of manufacturing the storage medium of the present invention; Figure 20 is a schematic exploded view showing a conventional storage medium; 5 and 21 are schematic plan views showing the back side of the storage medium of the seventeenth embodiment.

[Main component symbol description] 1 carrier 40 conductive contact mounting surface 10 first surface 41 conductive contact 11 second surface 5 second memory 12 through hole 50 conductive contact mounting surface 2 carrier 51 conductive contact 20 first surface 6 Housing 21 Second surface 60 B3 Control 1C 7 Passive component 30 Conductive contact mounting surface 8 Conductor 31 Conductive contact 4 First memory 24

Claims (1)

200834427 〇* 〇· X. Patent application scope: 1. A storage medium having a stacked memory structure, comprising: a carrier having a first surface and a second surface opposite to the first surface; Forming a predetermined circuit trace on the first surface and the second surface 5, respectively, the circuit traces on the first surface and the corresponding circuit traces on the second surface are electrically connected to each other; φ an installation a control integrated circuit on the first surface of the carrier, the control integrated circuit being configured such that its conductive contacts are electrically connected to corresponding circuit traces on the first surface of the 10; a first memory on a first surface of the carrier, the first memory being configured such that a conductive contact thereof is electrically connected to a corresponding circuit trace on the first surface; a partial overlay a second memory on the first memory such that the conductive 15 contact is not covered by the first memory, the conductive contact of the second memory φ body is opposite to the first surface Corresponding circuit electrical connection; and a housing covering the carrier, the control integrated circuit and the memory, the housing being formed with a plurality of surfaces for exposure to the second surface 20 of the carrier Corresponding to the through hole of the circuit trace. 2. A storage medium having a stacked memory structure, comprising: a carrier having a first surface, a second surface opposite the first surface, and a through hole extending through the carrier Forming, on the first surface and the second surface, a predetermined circuit holder 25 200834427 - a track on which the circuit traces on the first surface and the corresponding circuit traces on the second surface are electrically connected to each other; Forming on the first surface of the carrier such that it is formed. The surface of the conductive contact is a memory accessible through the through hole, and the conductive contact of the memory 5 is on the first surface of the carrier Corresponding circuit trace electrical connection, a predetermined circuit trace is formed on a surface of the memory formed with the conductive contact; φ is mounted on a surface of the memory formed with the conductive contact so as to be a bit a control integrated circuit within the through hole, the control integrated circuit 10 is electrically connected to a circuit trace on a surface of the memory formed with a conductive contact; and Overlying the support, the control of the integrated circuit and external memory • '· · housing, the housing is formed for several of the exposed through hole corresponding to the upper surface of the support of the second circuit traces. The storage medium of claim 2, further comprising a second memory formed on the second surface of the carrier, the conductive contact of the second memory being associated with the carrier The corresponding circuit on the second surface is _ electrical connection. 4. A storage medium having a stacked memory structure, comprising: 20 a carrier having a first surface, a second surface opposite the first surface, and a through hole extending through the carrier The first surface and the second surface are respectively formed with predetermined circuit traces, and the circuit traces on the first surface and the corresponding circuit traces on the second surface are electrically connected to each other; 26 200834427 〇» o. - a control integrated circuit mounted on the first surface of the carrier, the conductive solution point of the control integrated circuit being electrically connected to a corresponding circuit trace on the first surface of the carrier; a first memory in the through hole of the carrier, the first memory has a surface on which the conductive contact is formed; a surface mounted on the surface of the first memory formed with the conductive contact and the carrier a second memory on the surface, the second memory being φ configured such that the conductive contact of the second memory is a conductive contact corresponding to the first memory and on the carrier Corresponding 10 circuit traces on the first surface are electrically connected; and a housing covering the carrier, the control integrated circuit and the memory, the housing being formed with a plurality of surfaces for exposure to the second surface of the carrier Corresponding to the through hole of the circuit trace. 5. A storage medium having a stacked memory structure, comprising: 15 a carrier having a first surface, a second surface opposite the first φ surface, and a through hole extending through the carrier Forming predetermined circuit traces on the first surface and the second surface, respectively, the circuit traces on the first surface and the corresponding circuit traces on the second surface are electrically connected to each other; 20 A memory disposed within a via of the carrier, the memory having a surface formed with a conductive contact and a predetermined circuit trace electrically coupled to the corresponding conductive contact, circuitry on a surface of the memory The track is electrically connected to a corresponding circuit trace on the first surface of the carrier via a conductor; 27 200834427 A control integrated circuit mounted on a surface of the memory formed with a conductive contact, the control integrated body The circuit is configured such that the conductive contacts of the control integrated circuit are electrically connected to the circuit traces on the surface of the memory; and • 5 The carrier, the control integrated circuit and the outer casing of the memory are formed, the outer casing being formed with a plurality of through holes for the corresponding circuit traces exposed on the second surface of the carrier. Φ 6. A storage medium having a stacked memory structure, comprising: a first carrier having a first surface and a second surface opposite to the first surface, the first carrier The first surface and the first surface are respectively formed with predetermined circuit traces, wherein the circuit traces on the first surface and the corresponding circuit traces on the second surface are electrically connected to each other; a second carrier partially overlapping the carrier, the second carrier 15 having a first surface and a second surface opposite the first surface, on the first surface of the second carrier The circuit traces on the second surface are respectively formed by the circuit traces on the first surface and the corresponding circuit traces on the first surface of the first surface are electrically connected to each other on the second carrier H surface. The circuit secret is electrically connected to a corresponding circuit trace on the 20th surface of the first carrier; a control integrated circuit mounted on the first surface of the first carrier, the control integrated circuit is configured So that the control body a conductive contact of the circuit is electrically connected to a corresponding circuit trace on a first surface of the first carrier; 28 200834427 ^ * &amp; a first memory mounted on the first surface of the second carrier, The first memory is configured such that the conductive contacts of the first memory are electrically connected to a circuit on a first surface of the second carrier; 5 one mounted on the second carrier a second memory on the two surfaces, the second memory being configured such that the conductive contacts of the second memory are electrically connected to the corresponding circuit traces 10 on the second surface of the second carrier And a housing encasing the carrier, the control integrated circuit and the memory 10, the housing being formed with a plurality of through holes for the corresponding circuit traces exposed on the second surface of the carrier. a storage medium having a stacked memory structure, comprising: a carrier having a plurality of conductive pins; a first memory mounted on the carrier, the first memory 15 having a surface formed with a conductive contact and a circuit trace electrically connected to the corresponding conductive contact φ, the first memory being configured such that the conductive contact of the first memory is a corresponding conductive connection to the carrier Foot electrical connection; _ a second memory mounted on the first memory, the second 20 memory having a surface formed with a conductive contact and a circuit trace electrically connected to the corresponding conductive contact, The second memory is configured such that the conductive contacts of the second memory are electrically connected to corresponding conductive contacts of the first memory; and a surface of the second memory formed with circuit traces - * * 29 Control integrated circuit on 200834427, the control integrated circuit is configured such that the conductive contact of the control integrated circuit is a circuit trace corresponding to the second memory a gas connection; and a housing that encloses the carrier, the control integrated circuit, and the memory, the housing being formed with a plurality of through holes for corresponding circuit traces exposed on the second surface of the carrier. 8. A storage medium having a stacked memory structure, comprising: a carrier having a first surface and a second surface opposite the first surface, forming a 10 on a first surface of the carrier Having a predetermined circuit trace, and a second surface of the carrier is formed with a special purpose interface circuit and a predetermined circuit trace, the circuit trace on the first surface and the circuit trace corresponding to the winter on the second surface And the specific application interface circuits are electrically connected to each other; a control integrated circuit mounted on the first surface of the carrier, 15 the control integrated circuit is configured such that the conductive contacts of the control integrated circuit are Corresponding circuit traces on the first surface of the carrier are electrically connected, a memory mounted on the first surface of the carrier, the memory being configured such that the conductive contacts of the memory are associated with the carrier Corresponding circuit trace electrical connection on the first surface; and a housing covering the carrier, the control integrated circuit and the memory, the outer Forming exposed for several circuit traces corresponding to the through hole of the second upper surface of the carrier. 9. The storage medium of claim 8, wherein the specific interface circuit is a user identity module interface circuit. 10. The storage medium of claim 8, wherein the specific use interface circuit is a user identity module interface circuit. 11. The storage medium of claim 8, wherein the specific use interface circuit is a financial chip card interface circuit. 12. A method of manufacturing a storage medium, comprising the steps of: installing a control integrated circuit on a conductive contact mounting surface of a memory, and mounting a plurality of conductive contacts on a conductive contact mounting surface of the memory a predetermined electrical 10 track electrically connected to the corresponding conductive contact, the control integrated circuit being configured such that the conductive contact thereof is electrically connected to a corresponding circuit trace on a surface of the memory; Mounting the memory on a lead frame such that the conductive contact of the memory is electrically connected to a corresponding conductive pin of the lead frame; and forming a memory, the control integrated circuit and the wire The outer casing of the frame 15 is covered by a conductive pin, and the outer casing is formed with a plurality of through holes for exposing a portion of the corresponding conductive pin of the lead frame. 31