200832326 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種面板控制電路，尤其係一種液晶顯 示裝置之面板控制電路。 【先前技術】 液晶顯示裝置因具有低輻射性、體積輕薄短小及耗電 低等特點’已廣泛應用於手機、個人數位助理、筆記型電 腦、個人電腦及電視等領域。面板控制電路係液晶顯示裝 置之一重要元件，其將該液晶顯示裝置之系統控制電路傳 輸之訊號轉換為面板驅動電路所需訊號，從而使面板顯示 晝面。 明參閱圖1，其係一種先前技術面板控制電路之模塊 示意圖。該面板控制電路i包括一直流電壓輸入線u、'」 時序控制電路16、一直流轉換電路13、複數資料訊號線 1胃8及一與該直流轉換電路13連接之輸出端15。該直流電 鲁壓輸=線11之一端分別經由一第一直流電壓輸入端 及一第二直流電壓輸入端112連接至該時序控制電路Μ 及該直流轉換電路13,其另一端連接至一系統控制電路 19。該複數資料訊號線18之—端分別連接至該時序控制電 路16’其另-端亦連接至該系統控制電路19。該系統控制 電路19輸出一直流電壓訊號為該時序控制電路16及該直 流轉換電路U提供工作電壓；該系統控制電路^輸出複 數貧料訊號分別經由該複數資料訊號線18傳輸至該時序 控制電路16。該直流轉換電路13係—直流對直流轉 路，其將該直流電壓訊號轉換為其所連接之積體電路（、圖 200832326 未示）所需之工作電壓訊號，並經由該輸出端15輸出。 該時序控制電路16包括並聯於該第一直流電壓輸入 端hi及一接地端之間之複數防靜電線路161，其分別包 括複數正負極依序相連之二極體162。每一防靜電線路161 之複數二極體162中直接與該第一直流電壓輸入端ln連 接之二極體162均以其負極與該第一直流電壓輸入端 連接，直接接地之二極體162均以其正極接地。該複數資 料訊號輸入線18分別連接至每一與該第一直流電壓輸入 端111直接連接之二極體162之正極，其用於傳輸由該系 統控制電路19輸出之複數資料訊號至該複數防靜電線路 161。該複數資料訊號均係脈衝訊號，其高電平之脈衝電壓 值vH與該系統控制電路19所輸出之直流電壓值Vc相等。 該面板控制電路1開始工作時，如果該直流電壓訊號 優先於該複數資料訊號傳輸至該面板控制電路i，或該直 流電壓訊號與該複數資料訊號同時傳輸至該面板控制電路 1，該直流電壓訊號經由該直流電壓輸入線u傳輸至該時 序=制電路16及該直流轉換電路13，該直流轉換電路13 正系工作，且由於該二極體162之負極電壓Vc與其正極 之電壓vH相等’故該二極體162不導通，該資料訊號不 影響該直流轉換電路13之工作。 J如下一方面原因通常會導致該面板控制電路1開 啟時該資料錢優先於該直流電壓訊號傳輸至該面板控制 電路1 : 其-係該液晶顯示裝置處於省電模式時，該系統控制 電路19不再輸出直流電壓訊號.，同時持續輸出資料訊號至 200832326 該時序控制電路16 ;該液晶顯示裝置重新開始正常顯示 時，該系統控制電路19重新輸出直流電壓訊號至該面板控 制電路1，此時該資料訊號已優先於該直流電壓訊號傳輸 至該面板控制電路1。 其'一係為保證經由該直流電堡輸入線11至該面板控 制電路1之直流電壓訊號不含有雜訊及紋波，該直流電壓 輸入線11通常連接一電阻-電容串聯濾波電路（圖未示）， 該濾波電路之延遲效應易導致該面板控制電路1開始工作 之瞬間，該資料訊號優先於該直流電壓訊號傳輸至該面板 控制電路1。 該資料訊號優先於該直流電壓訊號傳輸至該面板控制 電路1時，該複數資料訊號之高電平脈衝電壓Vjj分別施 加於每一最鄰近該第一直流電壓輸入端m之二極體162 之正極，進而導通該複數二極體162並經由該複數防靜電 線路161、該第一直流電壓輸入端ln及該第二直流電壓 ⑩輸入端112傳輸至該直流轉換電路13。由於處於導通狀態 之二極體162具有分壓作用，故傳輸至該直流轉換電路13 之電壓值Vi小於該直流轉換電路13之工作電壓Vc，該直 流轉換電路13無法正常工作。當該直流電壓訊號Vc經由 該直流電壓輸入線11及該第二直流電壓輸入端112傳輸至 該直流轉換電路13時，由於先前傳輸之電壓訊號％之存 在，該直流轉換電路13仍無法正常工作，從而導致其無法 輸出其所連接之積體電路所需之工作電壓訊號；影響&晶 面板之正常顯示。 【發明内容】 200832326 有鑑於此，有必要提供一種可穩定輸出電壓訊號之面 板控制電路。 一種面板控制電路，其包括一直流轉換電路，該直流 轉換電路包括順序連接之一比較器、一還原電路及一直流 對直流轉換電路，該面板控制電路開始工作時，一電壓訊 號分別傳輸至該比較器及該直流對直流轉換電路，該比較 器具有一參考電壓，其比較該電壓訊號之電壓值與該參考 電壓值，如果該電壓值大於或等於該比較電壓值，該比較 •器輸出一高電平至該還原電路使其驅動該直流對直流轉換 電路還原為無訊號輸入之起始狀態。 相較於先前技術，本發明之面板控制電路於該直流轉 換電路内增加一比較器及一還原電路，當大於或等於該比 較器之參考電壓值的該直流轉換電路之工作電壓訊號滯後 於一小於該參考電壓值的電壓訊號傳輸至該比較器及該直 流對直流轉換電路時，該比較器輸出一高電平至該還原電 路，使該還原電路驅動該直流轉換電路之直流對直流轉換 ®電路還原為起始狀態，從而保證該小於參考電壓值的電壓 訊號不影響該直流轉換電路之正常工作，使得該直流轉換 電路可穩定輸出電壓訊號。 【實施方式】 請參閱圖2，其係本發明面板控制電路之模塊示意 圖。該面板控制電路2包括一直流電壓輸入線21、一時序 控制電路26、一直流轉換電路23、複數資料訊號線28及 一輸出端25。 該直流轉換電路23包括一比較器231、一還原電路232 200832326 及一直流對直流轉換電路233，該比較器231、該還原電路 232及該直流對直流轉換電路233順序連接。該直流電壓 輸入線21之一端分別經由一第一直流電壓輸入端211、一 第二直流電壓輸入端212連接至該比較器231及該直流對 直流轉換電路233，其另一端連接至一系統控制電路29。 該系統控制電路29輸出一直流電壓訊號Vc經由該直流電 壓輸入線21及該第二直流電壓輸入端212傳輸至該直流對 直流轉換電路233作為其之工作電壓，該直流對直流轉換 ®電路233將該直流電壓訊號轉換為其所連接之積體電路 (圖未示）所需之工作電壓訊號，並經由該輸出端25輸出。 該直流電壓輸入線21之一端連接至該系統控制電路 29，其另一端經由一第三直流電壓輸入端213連接至該時 序控制電路26，該系統控制電路29輸出之直流電壓訊號 Vc經由該第三直流電壓輸入端213傳輸至該時序控制電路 26作為其之工作電壓。該時序控制電路26包括並聯於該 第三直流電壓輸入端213及一接地端之間之複數防靜電線 β路261，其分別包括複數正負極依序相連之二極體262。每 一防靜電線路261之複數二極體262中直接與該第三直流 電壓輸入端213連接之二極體262均以其負極與該第三直 流電壓輸入端213連接，直接接地之二極體262均以其正 極接地。該複數資料訊號輸入線28分別連接至每一直接與 該第三直流電壓輸入端213連接之二極體162之正極，其 用於傳輸由該系統控制電路29輸出之複數資料訊號至該 複數防靜電線路261。該複數資料訊號均係脈衝訊號，其 高電平之脈衝電壓值VH與該系統控制電路29輸出且經由 200832326 該直流電壓輸入線21傳輸之直流電壓訊號之值Vc相等。 該直流轉換電路23之比較器231具有一設定之參考電 壓VR，其取值需滿足Vc —0.7V< VR< Vc，其中，Vc係該 直流對直流轉換電路233之工作電壓，0.7V係二極體262 處於正向導通狀態之電壓降。通常VR取（Vc — 0.5V)〜（Vc 一0.2V)範圍内之值。該比較器231比較輸入之直流電壓 值VI與該參考電壓VR之值，如果V!小於VR，則該比較 器231輸出低電平至該還原電路232，該還原電路232不 ⑩工作；如果V!不小於VR，則該比較器231輸出高電平至 該還原電路232，該還原電路232驅動該直流對直流轉換 電路233還原為無訊號輸入之起始狀態，且如果V!持續输 入，該比較器231不再輸出高電平。 該面板控制電路2開啟時，該複數資料訊號優先於該 直流電壓訊號傳輸至該面板控制電路2，其經由該複數資 料訊號輸入線28傳輸至該時序控制電路26，該資料訊號 之高電平脈衝電壓VH分別施加於每一最鄰近該第三直流 電壓輸入端213之二極體262之正極，進而導通該複數二 極體162並經由該複數防靜電線路261、該第三直流電壓 輸入端213及該第一直流電壓輸入端211傳輸至該比較器 231，經由該複數防靜電線路261、該第三直流電壓輸入端 213及該第二直流電壓輸入端212傳輸至該直流對直流對 直流轉換電路233。由於處於導通狀態之二極體262具有 分壓作用，故傳輸至該直流對直流轉換電路233之電壓值 Vs較該直流對直流轉換電路23之工作電壓Vc小0.7V， 該直流對直流轉換電路233無法正常工作。同時，該比較 11 200832326 器231比較Vs與其參考電壓VR的值，由於Vs小於VR， 故該比較器231輸出低電平至該還原電路232，該還原電 路232不工作，其對該直流對直流轉換電路233無輸出訊 號。瞬間後，該直流電壓訊號傳輸至該比較器231及該直 流對直流轉換電路233，由於該直流電壓值Vc大於VR之 取值範圍（VC— 0.5V)〜（Vc—0.2V)之最大值（Vc — 0.2V)， 故該比較器231輸出一高電平至該還原電路232，該還原 電路232輸出一控制訊號驅動該直流對直流轉換電路233 ⑩還原為無訊號輸入之起始狀態，亦即先前傳輸至該直流對 直流轉換電路233之資料訊號消失。該直流電壓訊號持續 輸入該比較器231及該直流對直流轉換電路233，該比較 器231不再輸出高電平至該還原電路232，該直流對-直流 轉換電路233正常工作。 相較於先前技術，本發明之面板控制電路2於該直流 轉換電路23内增加一比較器231及一還原電路232,當該 直流電壓訊號滯後於該資料訊號傳輸至該直流轉換電路 23時，該比較器231比較該直流電壓值¥(：與其參考電壓 VR，並輸出一高電平至該還原電路232,使該還原電路232 驅動該直流轉換電路23之直流對直流轉換電路233還原為 起始狀態，從而保證該資料訊號不影響該直流轉換電路23 之正常工作，使得該直流轉換電路23可穩定輸出電壓訊號 至其所連接之積體電路。 綜上所述，本發明確已符合發明之要件，爰依法提出 專利申請。惟，以上所述者僅為本發明之較佳實施方式， 本發明之範圍並不以上述實施方式為限，舉凡熟習本案技 12 200832326 藝之人士援依本發明之精神所作之等效修飾或變化，皆應 涵蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係一種先前技術之面板控制電路之模塊示意圖。 圖2係本發明面板控制電路之相:塊不意圖。 【主要元件符號說明】 面板控制電路 2 直流電壓輸入線 21 第一直流電壓輸入端 211 第二直流電壓輸入端 212 第三直流電壓輸入端 213 直流轉換電路 23 比較器 231 還原電路 232 直流對直流轉換電路 233 輸出端 25 時序控制電路 26 防靜電線路 261 二極體 262 貧料訊號輸入線 28 系統控制電路 29 13200832326 IX. Description of the Invention: [Technical Field] The present invention relates to a panel control circuit, and more particularly to a panel control circuit for a liquid crystal display device. [Prior Art] Liquid crystal display devices have been widely used in mobile phones, personal digital assistants, notebook computers, personal computers, and televisions because of their low radiation, small size, and low power consumption. The panel control circuit is an important component of the liquid crystal display device, and converts the signal transmitted by the system control circuit of the liquid crystal display device into a signal required by the panel driving circuit, thereby causing the panel to display the surface. Referring to Figure 1, there is shown a block diagram of a prior art panel control circuit. The panel control circuit i includes a DC voltage input line u, '" timing control circuit 16, a DC conversion circuit 13, a plurality of data signal lines 1 stomach 8 and an output terminal 15 connected to the DC conversion circuit 13. One end of the DC voltage transmission line 11 is connected to the timing control circuit Μ and the DC conversion circuit 13 via a first DC voltage input terminal and a second DC voltage input terminal 112, and the other end thereof is connected to a system control. Circuit 19. The ends of the complex data signal lines 18 are connected to the timing control circuit 16', respectively, and the other ends thereof are also connected to the system control circuit 19. The system control circuit 19 outputs a DC voltage signal for the timing control circuit 16 and the DC conversion circuit U to provide an operating voltage; the system control circuit ^ outputs a plurality of lean signals to the timing control circuit via the complex data signal line 18, respectively. 16. The DC conversion circuit 13 is a DC-to-DC conversion circuit that converts the DC voltage signal into an operating voltage signal required by the integrated circuit (not shown in FIG. 200832326), and is output via the output terminal 15. The timing control circuit 16 includes a plurality of antistatic lines 161 connected in parallel between the first DC voltage input terminal hi and a ground terminal, and respectively includes a plurality of diodes 162 sequentially connected to the positive and negative electrodes. The diode 162 of the plurality of diodes 162 of each antistatic line 161 directly connected to the first DC voltage input terminal ln is connected to the first DC voltage input terminal with a negative electrode thereof, and the diode is directly grounded. 162 is grounded with its positive pole. The plurality of data signal input lines 18 are respectively connected to the anodes of the diodes 162 directly connected to the first DC voltage input terminal 111 for transmitting the plurality of data signals output by the system control circuit 19 to the plurality of Electrostatic circuit 161. The complex data signals are pulse signals, and the high-level pulse voltage value vH is equal to the DC voltage value Vc outputted by the system control circuit 19. When the panel control circuit 1 starts working, if the DC voltage signal is transmitted to the panel control circuit i in preference to the complex data signal, or the DC voltage signal and the complex data signal are simultaneously transmitted to the panel control circuit 1, the DC voltage The signal is transmitted to the timing=system 16 and the DC converter circuit 13 via the DC voltage input line u. The DC converter circuit 13 operates normally, and since the anode voltage Vc of the diode 162 is equal to the voltage vH of the anode thereof Therefore, the diode 162 is not turned on, and the data signal does not affect the operation of the DC conversion circuit 13. J. The reason for the following is that when the panel control circuit 1 is turned on, the data money is transmitted to the panel control circuit 1 in preference to the DC voltage signal: when the liquid crystal display device is in the power saving mode, the system control circuit 19 The DC voltage signal is no longer output. At the same time, the data signal is continuously outputted to the timing control circuit 16 of 200832326. When the liquid crystal display device resumes normal display, the system control circuit 19 re-outputs the DC voltage signal to the panel control circuit 1. The data signal has been transmitted to the panel control circuit 1 in preference to the DC voltage signal. The first step is to ensure that the DC voltage signal passing through the DC power input line 11 to the panel control circuit 1 does not contain noise and ripple, and the DC voltage input line 11 is usually connected to a resistor-capacitor series filter circuit (not shown). The delay effect of the filter circuit is likely to cause the panel control circuit 1 to start working. The data signal is transmitted to the panel control circuit 1 in preference to the DC voltage signal. When the data signal is transmitted to the panel control circuit 1 in preference to the DC voltage signal, the high-level pulse voltage Vjj of the complex data signal is respectively applied to the diode 162 of each of the first DC voltage input terminals m. The positive electrode further turns on the plurality of diodes 162 and is transmitted to the DC conversion circuit 13 via the plurality of antistatic lines 161, the first DC voltage input terminal ln, and the second DC voltage 10 input terminal 112. Since the diode 162 in the on state has a voltage dividing action, the voltage value Vi transmitted to the DC converter circuit 13 is smaller than the operating voltage Vc of the DC converter circuit 13, and the DC converter circuit 13 cannot operate normally. When the DC voltage signal Vc is transmitted to the DC conversion circuit 13 via the DC voltage input line 11 and the second DC voltage input terminal 112, the DC conversion circuit 13 still cannot work normally due to the presence of the previously transmitted voltage signal %. Therefore, it is unable to output the working voltage signal required for the integrated circuit to which it is connected; affecting the normal display of the crystal panel. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a panel control circuit that can stabilize an output voltage signal. A panel control circuit includes a DC conversion circuit including a comparator, a reduction circuit, and a DC-to-DC conversion circuit. When the panel control circuit starts working, a voltage signal is respectively transmitted to the panel. a comparator and the DC-to-DC converter circuit, the comparator has a reference voltage, which compares the voltage value of the voltage signal with the reference voltage value, and if the voltage value is greater than or equal to the comparison voltage value, the comparator output is high Leveling to the restore circuit causes it to drive the DC-to-DC conversion circuit to the initial state of no signal input. Compared with the prior art, the panel control circuit of the present invention adds a comparator and a reduction circuit to the DC conversion circuit, and the operating voltage signal of the DC conversion circuit that is greater than or equal to the reference voltage value of the comparator lags behind When a voltage signal smaller than the reference voltage value is transmitted to the comparator and the DC-DC conversion circuit, the comparator outputs a high level to the reduction circuit, so that the reduction circuit drives the DC-to-DC conversion of the DC conversion circuit. The circuit is restored to an initial state, thereby ensuring that the voltage signal less than the reference voltage value does not affect the normal operation of the DC conversion circuit, so that the DC conversion circuit can stabilize the output voltage signal. [Embodiment] Please refer to Fig. 2, which is a schematic block diagram of a panel control circuit of the present invention. The panel control circuit 2 includes a DC voltage input line 21, a timing control circuit 26, a DC conversion circuit 23, a complex data signal line 28, and an output terminal 25. The DC conversion circuit 23 includes a comparator 231, a reduction circuit 232 200832326, and a DC-to-DC conversion circuit 233. The comparator 231, the reduction circuit 232, and the DC-DC conversion circuit 233 are sequentially connected. One end of the DC voltage input line 21 is connected to the comparator 231 and the DC-DC conversion circuit 233 via a first DC voltage input terminal 211 and a second DC voltage input terminal 212, and the other end thereof is connected to a system control. Circuit 29. The system control circuit 29 outputs a DC voltage signal Vc via the DC voltage input line 21 and the second DC voltage input terminal 212 to the DC-DC conversion circuit 233 as its operating voltage. The DC-to-DC conversion control circuit 233 The DC voltage signal is converted into a working voltage signal required by an integrated circuit (not shown) connected thereto, and is output through the output terminal 25. One end of the DC voltage input line 21 is connected to the system control circuit 29, and the other end thereof is connected to the timing control circuit 26 via a third DC voltage input terminal 213. The DC voltage signal Vc outputted by the system control circuit 29 passes through the first The three DC voltage input terminal 213 is transmitted to the timing control circuit 26 as its operating voltage. The timing control circuit 26 includes a plurality of antistatic lines β 261 connected in parallel between the third DC voltage input terminal 213 and a ground terminal, and respectively includes a plurality of diodes 262 connected in series with the positive and negative electrodes. The diode 262 directly connected to the third DC voltage input terminal 213 of the plurality of diodes 262 of each antistatic line 261 is connected to the third DC voltage input terminal 213 by its negative pole, and is directly grounded to the pole. Body 262 is grounded with its positive pole. The plurality of data signal input lines 28 are respectively connected to the anodes of the diodes 162 directly connected to the third DC voltage input terminal 213 for transmitting the plurality of data signals output by the system control circuit 29 to the plurality of Electrostatic line 261. The complex data signals are pulse signals, and the high-level pulse voltage value VH is equal to the value Vc of the DC voltage signal output by the system control circuit 29 and transmitted via the DC voltage input line 21 of 200832326. The comparator 231 of the DC conversion circuit 23 has a set reference voltage VR, which is required to satisfy Vc - 0.7V < VR < Vc, wherein Vc is the operating voltage of the DC-to-DC converter circuit 233, 0.7V is two The polar body 262 is in a voltage drop in the forward conduction state. Usually VR takes values in the range of (Vc - 0.5V) ~ (Vc - 0.2V). The comparator 231 compares the value of the input DC voltage value VI with the reference voltage VR. If V! is less than VR, the comparator 231 outputs a low level to the reduction circuit 232, and the reduction circuit 232 does not work 10; Not less than VR, the comparator 231 outputs a high level to the reduction circuit 232, and the reduction circuit 232 drives the DC-to-DC conversion circuit 233 to return to the initial state of no signal input, and if V! continues to input, The comparator 231 no longer outputs a high level. When the panel control circuit 2 is turned on, the complex data signal is transmitted to the panel control circuit 2 in preference to the DC voltage signal, and is transmitted to the timing control circuit 26 via the complex data signal input line 28, and the data signal is high level. The pulse voltage VH is respectively applied to the anode of each of the diodes 262 adjacent to the third DC voltage input terminal 213, thereby turning on the plurality of diodes 162 and inputting the third DC voltage via the plurality of antistatic lines 261. The terminal 213 and the first DC voltage input terminal 211 are transmitted to the comparator 231, and are transmitted to the DC-DC pair via the plurality of anti-static lines 261, the third DC voltage input terminal 213, and the second DC voltage input terminal 212. DC conversion circuit 233. Since the diode 262 in the on state has a voltage dividing effect, the voltage value Vs transmitted to the DC-DC conversion circuit 233 is 0.7 V smaller than the operating voltage Vc of the DC-DC conversion circuit 23, and the DC-DC conversion circuit 233 is not working. At the same time, the comparison 11 200832326 231 compares the value of Vs with its reference voltage VR. Since Vs is less than VR, the comparator 231 outputs a low level to the reduction circuit 232, and the reduction circuit 232 does not operate. The conversion circuit 233 has no output signal. After the instant, the DC voltage signal is transmitted to the comparator 231 and the DC-DC conversion circuit 233, because the DC voltage value Vc is greater than the maximum value range of VR (VC - 0.5V) ~ (Vc - 0.2V) (Vc - 0.2V), the comparator 231 outputs a high level to the reduction circuit 232, and the reduction circuit 232 outputs a control signal to drive the DC-to-DC conversion circuit 233 10 to return to the initial state without the signal input. That is, the data signal previously transmitted to the DC-to-DC conversion circuit 233 disappears. The DC voltage signal is continuously input to the comparator 231 and the DC-to-DC conversion circuit 233. The comparator 231 no longer outputs a high level to the reduction circuit 232, and the DC-DC conversion circuit 233 operates normally. Compared with the prior art, the panel control circuit 2 of the present invention adds a comparator 231 and a reduction circuit 232 to the DC conversion circuit 23, and when the DC voltage signal lags behind the data signal to the DC conversion circuit 23, The comparator 231 compares the DC voltage value ¥(: with its reference voltage VR, and outputs a high level to the reduction circuit 232, causing the reduction circuit 232 to drive the DC-to-DC conversion circuit 233 of the DC conversion circuit 23 to be restored. The initial state, thereby ensuring that the data signal does not affect the normal operation of the DC conversion circuit 23, so that the DC conversion circuit 23 can stably output the voltage signal to the integrated circuit to which it is connected. In summary, the present invention has indeed met the invention. The above is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiments, and those who are familiar with the present technology 12 200832326 Equivalent modifications or variations made by the spirit of the invention are intended to be included in the scope of the following claims. Figure 2 is a schematic diagram of the panel control circuit of the present invention. Figure 2 is the phase of the panel control circuit of the present invention: block is not intended. [Main component symbol description] panel control circuit 2 DC voltage input line 21 first DC voltage input terminal 211 second DC voltage Input terminal 212 DC voltage input terminal 213 DC conversion circuit 23 Comparator 231 Reduction circuit 232 DC-to-DC conversion circuit 233 Output terminal 25 Timing control circuit 26 Anti-static line 261 Diode 262 Lean signal input line 28 System control circuit 29 13