TW200832218A - Fast sorting circuit architecture - Google Patents

Fast sorting circuit architecture Download PDF

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Publication number
TW200832218A
TW200832218A TW96103672A TW96103672A TW200832218A TW 200832218 A TW200832218 A TW 200832218A TW 96103672 A TW96103672 A TW 96103672A TW 96103672 A TW96103672 A TW 96103672A TW 200832218 A TW200832218 A TW 200832218A
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Taiwan
Prior art keywords
input
circuit architecture
sorting
group
module
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TW96103672A
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Chinese (zh)
Inventor
Wen-Jyi Hwang
Yao-Jung Yeh
Hui-Ya Li
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Wen-Jyi Hwang
Yao-Jung Yeh
Hui-Ya Li
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Application filed by Wen-Jyi Hwang, Yao-Jung Yeh, Hui-Ya Li filed Critical Wen-Jyi Hwang
Priority to TW96103672A priority Critical patent/TW200832218A/en
Publication of TW200832218A publication Critical patent/TW200832218A/en

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Abstract

A fast sorting circuit architecture has a number of process modules connected in series. Each process module contains a comparator, and a multiplexer with a register. Each input datum is broadcasted to all process modules. After comparing the stored value kept in the register with the input datum, the comparator gives the comparison result as the control line value of the multiplexers in current and next process module so that the stored values can be sorted. This fast sorting circuit architecture can finish the sorting operation for a single input datum within one cycle, and the area complexity of this fast sorting circuit linearly depends on the number of process modules.

Description

200832218 九、發明說明： 【發明所屬之技術領域】 本龟明係關於一種快速排序電 · 士 排序電路架構之處理模組的餘，構少關種快速 單筆輸入資料之排序操作，且，巧於早—時脈週期内完成 咖)亦無包含控制單元(⑽加γ且 =)遞延遲(卿—^ 【先前技術】 斑全ίϊίΓίΓ)操作可細分為部份排序(partiai s〇r_) -擇之4 ’且常需在時間與空間兩者 、—中華民目案號2_13 一種最佳化高速排序 接複數個相同電路之處理單元戶斤、、4 σ〜、 ’、串 sort)為基礎，事先移動（pre_shi=^^=x (carry lookahead)的設計方式，達到# 及=置進位 ϊΐ=ΐ3ίΓ=、且J於單—時脈二=尨c 度:卻增加“ 1前。置移^策略雖然提高速 遲(购delay)的問題，也使控^==^_延 【發明内容】 ii麵 ss 存值做比雛，直·比較絲秘該處理二 組的多工器之控制線，以提高處理速度、 =椒 低傳遞延遲、免去採用控制單元所帶來的額外^擔硬，又、降 5 200832218 【實施方式】 户理之一種快速排序電路架構，係由複數個才目同電路的 内含乡賴組5G均包含一比較器 值為00，且編號第G個處理模組5G其控制線37的内容恒為 於入私可分為兩個步驟：第一步驟’比較器40對 諡?蝴啦，則比 =控苐制線4及^ 決定存於暫，=之多二41根據控制線37與38的内容來 線與暫存器42 ^第i個處理模組之控制 —37 — 38 X ^0~ 0 1200832218 IX. Description of the invention: [Technical field of invention] This turtle is about the processing module of a quick sorting electrician sorting circuit architecture, and constructs a sorting operation of fast single input data, and In the early-clock cycle, there is no control unit ((10) plus γ and =) delay (clear-^ [previous technique] spot full ίϊίΓίΓ) operation can be subdivided into partial sorting (partiai s〇r_) - Choose 4' and often need to be based on both time and space, - China Civil Case No. 2_13, an optimized high-speed sequencing, which is connected to several processing units of the same circuit, 4 σ~, ', string sort) , move in advance (pre_shi=^^=x (carry lookahead) design method, reach # and = set carry ϊΐ = ΐ 3ίΓ =, and J in single - clock two = 尨 c degrees: but increase "1 before. shift ^Strategy, although the problem of speeding up (purchasing delay) is improved, it also makes control ^==^_延[Summary of the invention] ii surface ss stored value is more than the younger, straighter and more filthy to handle the control of the two groups of multiplexers Line to increase processing speed, = low transfer delay of pepper, eliminating the need to use control unit The additional ^ 硬 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The content of the control line 37 of the Gth processing module 5G is always divided into two steps: the first step 'the comparator 40 is opposite to the butterfly, then the ratio = the control line 4 and the ^ decision In the temporary, = 2 or 41 according to the contents of the control lines 37 and 38 line and the register 42 ^ control of the i-th processing module - 37 - 38 X ^ 0 ~ 0 1

保持既有内存值 輸出 ct 第一 在此以一簡單實例來說明操 a 圖為示意利用本發明快速排序電照第二圖。第二 存器内存狀魏。例如本翻雜序猶時，各暫 處理模組，其暫存器42-1、暫存哭49序電路架構包括有3個 值均被設定為〇〇，第一個輸入 ^暫存态42-3之初始 ，问日寸和暫存器犯一^暫存 200832218 ^2-2、暫存器42-3的内存值做比較，而比較 2疋卜於是將輸入值3放到暫存器U T及 暫存器42-3的内存值則分別由暫存器42-1及^^ ^ ^來。第二個輸入值4，同時和暫存器们、暫：、 暫存裔42-3的内存值做比較，而比較紝 _ 42 2 為1，於是將輸入值4放到暫存器』X果暫 丄，C2和C3 不變，暫存器42-3的内存值則由暫存哭42_t務I—1則保持 存益42-3的内存值分別為丨、3、4。 °。 2暫 明ί速排序電路賴，在輸人㈣魄量棒咬等於 S=;巧時’可以直接套用;在輸入資料的 日、^之數里柃，只要對輸入流程稍做改 ;之處理模組’來對不限數量之輸入資料進行二:利=數 有J筆’處理模組的數目有Κ個，Ν與κ為自二數 能將輸入㈣騎猶理—次後，就 =完成排; 逐漸料再次輸人本發明高速排序電路架構、，貝ί可 程序即§可、==刪制馳量，且峰难 運同時滿足高 說明本發明之較佳實施例，藉由實施例 發日===，特點’其目的在使熟習該技術者能了解本 凡運用杯ίΐ"ί貫施，並義以限定本發日狀實施範圍。舉 彡年白應包括於本發明申請專利之範圍内。 【圖式簡單說明】 7 200832218 f 厂圖顯示本發明的處理模組之—種較佳電路實施例。 郎速麟祕賴進行排 排序程ί之輸人ί料數量時，每輪 【主要元件符號說明】 50處理模組 40比較器 41多工器 42暫存器 37多工器的一控制線 38夕工裔的一控制線 39多工器的輪出線Maintaining Existing Memory Values Output ct First, a simple example is used to illustrate the operation. The figure is a second diagram illustrating the use of the present invention for quick sequencing of the same. The second memory is memory-like. For example, the temporary processing module, each temporary processing module, its temporary storage 42-1, temporary storage crying sequence circuit structure includes three values are set to 〇〇, the first input ^ temporary storage state 42 -3 initial, ask the day and the scratchpad to commit a ^ temporary storage 200832218 ^ 2 2, the memory value of the register 42-3 to compare, and compare 2 疋 于 then put the input value 3 into the scratchpad The memory values of the UT and the scratchpad 42-3 are respectively obtained by the temporary registers 42-1 and ^^^^. The second input value is 4, and compared with the memory values of the scratchpads, temporary:, and temporary storage 42-3, and the comparison 纴 _ 42 2 is 1, so the input value 4 is placed in the register 』X If the C2 and C3 are unchanged, the memory value of the scratchpad 42-3 is stored by the temporary crying 42_t service I-1, and the memory values of the stored benefit 42-3 are respectively 丨, 3, 4. °. 2 Temporary clarification of the speed of the sorting circuit Lai, in the input (four) 棒 棒 咬 等于 equal to S =; smart when 'can be applied directly; in the input data of the day, ^ number, as long as the input process is slightly modified; The module 'is to perform an unlimited number of input data: the number of the number of processing modules with a number of J pens is Κ, Ν and κ are from the two numbers and can be input (four). Completing the row; gradually expecting to input the high-speed sequencing circuit architecture of the present invention again, and the program can be suffixed, == deleted, and the peak is difficult to meet the high-precision embodiment of the present invention. The example of the day ===, the characteristics of 'the purpose of the familiar with the technology can understand the use of the cup ΐ ί ί , , , , , , , , , , , , , , , , , , 。 。 。 。 。 。 。 。 。 。 It should be included in the scope of the patent application of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS 7 200832218 f The factory diagram shows a preferred circuit embodiment of the processing module of the present invention. Lang Suolin secrets the sorting process. When the number of the input is ί, the number of the main components is explained. [The main component symbol description] 50 processing module 40 comparator 41 multiplexer 42 register 37 multiplexer of a multiplexer 38 The turn of the 39 multiplexer of a control line

Claims (1)

200832218 十、申請專利範圍： 一種快速排序電路架構，包括： 資料模、㈣有處職咖時接收一輸入 二ίίΠ—暫存11，該暫存器具有—内存值； 紝果值’用以比較該輸入資料與該内存值，並將比較 模組與次個處賴組❹4之控制線，使 多工2哭=出月^^圍J/f所述之快速排序電路架構，其中 多工二的=;之一輸入線，且 之輸出。 Μ勒人貝顺—別個處理模組的多工器 :内ς值前個處理模組的多工器之輸“二= 内含==，為= 5、如申請專利範圍第i、2、3：tt所構成二 架構，其中在輸入資料數量大於處理模的^、速:非 排序程序後’所有輸人資料被分為已經 排序的第二群。 工娜序的弟一鲆，和未經 /私6、-ί申請專利範圍第5項所述之快速排序電路架構，立中 在輸入賢料數量大於處理模組的情況下 〃、/、广 後的第二群㈣輸人雜速解電U—:人排序程f 料的數量，並重覆此操作至第二君==數Ifff第二群f 到全部排序。 、 里為0為止，以達 7、如申請專利範圍第1項所述之伊“ 每-個處理模組均適於接收一重置(、、)_^电路采構〜、中 ^ set)k唬，使其内存值被 9 200832218 初始化為00。200832218 X. Patent application scope: A fast sorting circuit architecture, including: data module, (4) receiving an input two when there is a service, _ temporary storage 11, the temporary memory has - memory value; The input data and the memory value, and the comparison module and the second control line of the group 4, so that the multiplex 2 cry = the moon ^ ^ circumference J / f described in the quick sort circuit architecture, wherein multiplex 2 = one of the input lines, and the output. Μ勒人贝顺—a multiplexer that handles the module: the input of the multiplexer of the previous processing module is “two = embedded ==, = 5, as in the patent application scope i, 2 3: tt constitutes the second architecture, in which the input data is larger than the processing mode, the speed: non-sorting program, 'all the input data is divided into the second group that has been sorted. The fast-sorting circuit architecture described in item 5 of the patent scope of the application/private 6, and the second group (four) input speed of the 〃, /, and Guanghou in the case that the input quantity is greater than the processing module. Solving U—: the number of people sorting f, and repeating this operation to the second king == number Ifff second group f to all sorts. The "each processing module is adapted to receive a reset (,,) _^ circuit configuration ~, middle ^ set) k 唬, so that its memory value is initialized to 00 by 9 200832218.
TW96103672A 2007-01-31 2007-01-31 Fast sorting circuit architecture TW200832218A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111949241A (en) * 2019-05-15 2020-11-17 瑞昱半导体股份有限公司 Sorting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111949241A (en) * 2019-05-15 2020-11-17 瑞昱半导体股份有限公司 Sorting device
CN111949241B (en) * 2019-05-15 2024-04-12 瑞昱半导体股份有限公司 Sequencing device

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