TW200830507A - Carrier film to prevent cracking at bends of leads and semiconductor package utilizing the film - Google Patents

Carrier film to prevent cracking at bends of leads and semiconductor package utilizing the film Download PDF

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Publication number
TW200830507A
TW200830507A TW96100368A TW96100368A TW200830507A TW 200830507 A TW200830507 A TW 200830507A TW 96100368 A TW96100368 A TW 96100368A TW 96100368 A TW96100368 A TW 96100368A TW 200830507 A TW200830507 A TW 200830507A
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TW
Taiwan
Prior art keywords
semiconductor package
pins
pin
dielectric layer
carrier film
Prior art date
Application number
TW96100368A
Other languages
Chinese (zh)
Inventor
Ming-Hsun Li
Tzung-Li Hung
Men-Shew Liu
Original Assignee
Chipmos Technologies Inc
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Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to TW96100368A priority Critical patent/TW200830507A/en
Publication of TW200830507A publication Critical patent/TW200830507A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Wire Bonding (AREA)

Abstract

Disclosed is a carrier film to prevent cracking at bends of leads, which mainly includes a flexible dielectric layer, a plurality of leads on the dielectric layer, and a solder resist layer partially covering the leads. Each lead has an interconnection wiring and an outer lead, and there is a smallest included angle between the interconnection wiring and the outer lead ranging from 90 degrees to 180 degrees. Therein, at least one of the leads has a buffer pad connecting the interconnection wiring and the outer lead and covered by the solder resist layer so as to prevent cracking/breaking near bends of the leads caused by stress. Also a semiconductor package utilizing the film is disclosed.

Description

200830507 九、發明說明： 【發明所屬之技術領域】 本發明係有關於—種半導_裝制，特別係有關於- 種防止引腳_折處斷裂之半導體封裝載膜以及使用該載膜 之封裝構造。 【先前技術】200830507 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor package, and in particular to a semiconductor package carrier film for preventing pin breakage and use of the carrier film Package construction. [Prior Art]

依據半導體產品之用途變化，其晶片載趙可以選用印刷 電路板、導線架與電路薄膜，其中電路薄膜具有可撓曲性與 薄化的優點。例如，目前的捲帶式承載（Tape carrier Package，TCP)封裝與薄膜覆晶（Chip 〇n Fiim c〇f)封裝皆是㈣電路薄㈣為晶片㈣。在封裝之前， 電路薄膜是-捲帶中之-單元，而能以捲帶傳輸方式進行半 導體封裝作業❶ 如第1圖所示，習知半導體封裝載膜1〇〇包含一可撓性 介電層11〇、複數個引腳12〇以及一防焊層13〇。該些引腳 120係形成於該可撓性介電| UGJi，而該防銲層13〇係局 部覆蓋該些引腳！20。大部份之每__引腳12G係區分為一内 引腳121、一外引腳122及一斜向之扇出線123，該些扇出 線123係連接該些内引腳121與該些外引腳122，而使該些 外引腳122能更加分散，以供接合至一外部印刷電路板或一 玻璃面板。該防銲層130係具有一開口 131，其係顯露該些 引腳120之内引腳121，以供接合晶片。然而在半導體封裝 產品的使用狀態中，該半導體封裝載冑1〇〇包含有扇出線 123之。P位需要彎曲呈弧形方可使用，該些引腳1之彎折 200830507 處谷易受應力拉扯或彎折。特別是當該載膜1〇〇之可撓曲彎 曲部位係包含該些外引腳122與該些扇出線123之連接處， 、考曲該載膜100造成該些引腳120之外應力會集中至該些引 腳120之彎折處，導致少數之該些引腳12〇會有斷裂之問題 (如第1圖所示之引腳斷裂處124)，但卻使得整個封裝產品 無法運作。 【發明内容】 〔本發明之主要目的係在於提供一種防止引腳彎折 處斷裂之半導體封裝載膜，利用緩衝墊設置於引腳彎 折處，可防止引腳受應力拉扯而造成斷裂之問題。 本發明的目的及解決其技術問題是採用以下技術 方案來實現的。依據本發明，一種防止引腳彎折處斷 裂之半導體封裝載膜主要包含一可撓性介電層、複數 個引腳以及一防銲層。該些引腳係形成於該可撓性介 電層上。該防銲層係形成於該可撓性介電層上，以局 I 部覆蓋該些引腳。其中，每-引腳係具有一内接線與 外引腳，該内接線與該外引腳之最小失角係介於90 度至180度，其中至少一引腳係具有一緩衝墊，其係 連接該内接線與該外引腳。此外，本發明另揭示使用該 半導體封裝載膜之一半導體封裝構造。 本^月的目的及解決其技術問題還可採用以下技 術措施進一步實現。 在刖述❾_導體封装載膜中，#緩衝塾係概呈圓形 且其直徑大於該内接線之寬度。 6 200830507 在前述的半導體封裝栽膜中，該緩衝墊係被該防銲 層所覆蓋。 在刖述的半導體封裝載膜中，該内接線係為一斜向 之扇出線。 在前述的半導體封裝載膜中，該内接線係為一内引 腳。 在前述的半導體封裝載膜中，該緩衝墊係具有一外 弧邊。 在前述的半導體封裝載膜中，該些引腳係更具有複數 個第一緩衝墊與複數個第二緩衝墊，該些第一緩衝墊與該些 第二緩衝墊係#列在不同直線上且位於該可撓性介電層之 同一側。 【實施方式】 依據本發明之第一具體實施例，揭示一種防止引腳 彎折處斷裂之半導體封裝載膜。如第2圖所示並配合 參閱第3圖，該半導體封裝載膜2〇〇主要包含一可撓 性介電層210、複數個引腳22〇以及一防銲層23〇。該 些引腳220係形成於該可撓性介電層2ι〇上，該防銲 層230係局部覆蓋該些引腳22〇。通常該可撓性介電 層210之材質係可為聚醯亞胺（p〇lyimide，或聚酯類 (PET)等。在封裝前，複數個載膜2〇〇可一體形成於一 捲帶，以供捲帶式傳輸進行半導體封裝作業。 該些引腳220係為高導電性金屬材質，例如銅，並 且應相當地薄以提供適當之可撓曲性，其厚度遠低於 7 200830507 傳統導線架之引腳厚度。每一引腳220係具有一内接 線221與一外引腳222，該些内接線221與該些外引 腳2 2 2之最小夾角係介於9 0度至1 8 0度。在本實施例 中，該些内接線221係為斜向之扇出線，用以連接較 大節距之外引腳222至較小節距之内引腳224。 其中至少一引腳220係具有一緩衝墊223，其係連 接該内接線221與該外引腳222。在本實施例中，大 部分之引腳220均具有一緩衝墊223。較佳地，如第2 Γ 圖所示，該緩衝墊223係具有一外弧邊225，用以分 散原集中在引腳彎折點之應力，可為導散應力之任意 形狀。在本實施例中，該緩衝墊2 2 3係概呈圓形且其 直徑大於該内接線221之寬度。 該防銲層23 0係形成於該可撓性介電層2丨〇上，以 局部覆蓋該些引腳220，能防止該些引腳220外露被污染 而短路。該防銲層2 3 0係具有一開口 2 3 1，其係顯露該 些引腳220之内引腳224之内端，以供一晶片310之複 數個凸塊3 1 1接合（如第3圖所示）。通常該防銲層2 3 0 係可為液態感光性鲜罩層（liquid photoimagable solder niask’ LPI)、感光性覆盡層（photoimagable cover layer，PIC)、 或可為一般非感光性介電材質之非導電油墨或覆蓋層（ cover layer)。在本實施例中，該緩衝墊223係被該防銲層230 所覆蓋，以增強該緩衝墊223之應力緩衝能力並避免 與鄰近之引腳220產生電性短路。 依據本發明之第一具體實施例，該半導體封裝載膜 8 200830507 fDepending on the application of the semiconductor product, the wafer carrier can use a printed circuit board, a lead frame and a circuit film, wherein the circuit film has the advantages of flexibility and thinning. For example, current Tape Carrier Package (TCP) packages and Chip 〇n Fiim c〇f packages are (4) circuit boards (4) for wafers (4). Before the package, the circuit film is a unit in the tape, and the semiconductor package operation can be performed by the tape transfer method. As shown in FIG. 1, the conventional semiconductor package carrier film 1 includes a flexible dielectric The layer 11 〇, the plurality of pins 12 〇 and a solder resist layer 13 〇. The pins 120 are formed on the flexible dielectric | UGJi, and the solder resist layer 13 partially covers the pins! 20. The majority of each __ pin 12G is divided into an inner pin 121, an outer pin 122 and an oblique fan-out line 123. The fan-out lines 123 are connected to the inner pins 121 and The outer pins 122 allow the outer pins 122 to be more dispersed for bonding to an external printed circuit board or a glass panel. The solder mask 130 has an opening 131 that exposes the leads 121 of the pins 120 for bonding the wafer. However, in the state of use of the semiconductor package product, the semiconductor package carrier 1 includes a fan-out line 123. The P-bit needs to be curved and curved to be used. The bends of the pins 1 are susceptible to stress pulling or bending at 200830507. In particular, when the flexible bending portion of the carrier film 1 includes the connection between the outer leads 122 and the fan-out lines 123, the stress of the carrier film 100 is caused to cause external stress on the pins 120. Will focus on the bends of the pins 120, resulting in a few of the pins 12 〇 will break (such as the pin break 124 shown in Figure 1), but make the entire package product inoperable . SUMMARY OF THE INVENTION [The main object of the present invention is to provide a semiconductor package carrier film that prevents breakage of a pin bend, and is provided at a bend of a pin by a cushion pad to prevent the pin from being pulled by stress and causing breakage. . The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a semiconductor package carrier film for preventing breakage of a pin bend mainly comprises a flexible dielectric layer, a plurality of leads, and a solder resist layer. The leads are formed on the flexible dielectric layer. The solder resist layer is formed on the flexible dielectric layer to cover the pins with a portion I. Wherein, each pin has an inner wire and an outer pin, and the minimum wire angle of the inner wire and the outer pin is between 90 degrees and 180 degrees, and at least one of the pins has a cushion. Connect the inner wiring to the outer lead. Furthermore, the present invention further discloses a semiconductor package construction using one of the semiconductor package carrier films. The purpose of this month and solving its technical problems can be further realized by the following technical measures. In the description of the conductor package, the # buffering system is generally circular and has a diameter larger than the width of the inner wiring. 6 200830507 In the aforementioned semiconductor package film, the buffer pad is covered by the solder resist layer. In the semiconductor package carrier described above, the internal wiring is an oblique fan-out line. In the aforementioned semiconductor package carrier film, the internal wiring is an inner lead. In the aforementioned semiconductor package carrier film, the pad has an outer arc edge. In the foregoing semiconductor package carrier film, the pin lines further have a plurality of first buffer pads and a plurality of second buffer pads, and the first buffer pads and the second buffer pads are listed on different lines. And located on the same side of the flexible dielectric layer. [Embodiment] According to a first embodiment of the present invention, a semiconductor package carrier film for preventing breakage of a pin bend is disclosed. As shown in FIG. 2 and referring to FIG. 3, the semiconductor package carrier 2 〇〇 mainly includes a flexible dielectric layer 210, a plurality of leads 22 〇, and a solder resist layer 23 〇. The pins 220 are formed on the flexible dielectric layer 2 ,, and the solder resist layer 230 partially covers the pins 22 〇. Generally, the material of the flexible dielectric layer 210 may be polypyrene (PET) or the like. Before the package, a plurality of carrier films 2 can be integrally formed on a roll. For tape and tape transfer for semiconductor packaging operations. The pins 220 are made of highly conductive metal, such as copper, and should be relatively thin to provide adequate flexibility, which is much less than 7 200830507. The lead thickness of the lead frame. Each pin 220 has an inner wire 221 and an outer pin 222, and the minimum angle between the inner wire 221 and the outer pins 2 2 2 is between 90 degrees and 1 In this embodiment, the inner wires 221 are oblique fan-out lines for connecting the pins 222 outside the larger pitch to the pins 224 within the smaller pitch. The pin 220 has a buffer pad 223 that connects the inner wire 221 and the outer pin 222. In this embodiment, most of the pins 220 have a cushion 223. Preferably, as in the second As shown in the figure, the cushion 223 has an outer arc 225 for dispersing the stress originally concentrated on the bending point of the lead, which may be a divergence. Any shape of the stress. In this embodiment, the cushion 2 2 3 is substantially circular and has a diameter larger than the width of the inner wire 221 . The solder resist layer 30 0 is formed on the flexible dielectric layer 2 . In order to partially cover the pins 220, the pins 220 can be prevented from being contaminated and short-circuited. The solder resist layer 203 has an opening 23, which exposes the pins 220. The inner end of the inner lead 224 is joined by a plurality of bumps 31 1 of a wafer 310 (as shown in Fig. 3). Usually, the solder resist layer 2 3 0 can be a liquid photosensitive fresh cover layer (liquid Photoimagable solder niask' LPI), photoimgable cover layer (PIC), or a non-conductive ink or cover layer which may be a generally non-photosensitive dielectric material. In this embodiment, the buffer The pad 223 is covered by the solder resist layer 230 to enhance the stress buffering capability of the pad 223 and to avoid electrical shorting with the adjacent pin 220. According to the first embodiment of the present invention, the semiconductor package carrier film 8 200830507 f

2 00可進一步應用於一半導體封裝構造。請參閱第3 圖’一種半導體封褒構造主要包含該載膜2〇〇以及一 晶片3 1 0。該晶片3 1 〇係設置於該载膜2〇〇並電性連 接至該些引腳220。在本實施例中，該晶片31〇係設 有複數個凸塊311’其係接合至該些引腳220之内引 腳224。該封裝構造可另包含有一封膠體32〇，例如一 種在固化前具高流動性之點塗膠體，其係密封該些凸 塊311。其中，該緩衝墊223係位於該載膜2〇〇上介於該 晶片310與該些外引腳222之間之一可撓曲部位，以避免在 彎曲狀態之該載膜200會有應力集中於連接該些外引腳222 之彎折處，防止外引腳與内接線之間的彎折連接點附近產生 斷裂。 在第二具體實施例中，揭示另一種防止引腳彎折處 斷裂之半導體封裝載膜。如第4圖所示，該半導體封 裝載膜4 00主要包含一可撓性介電層41〇、複數個引 腳420以及一防銲層43〇。該些引腳42〇係形成於該 每一引腳 420 可撓性介電層4 i 0上。在本實施例中 均具有一内接線421、426與一外引腳422。其中，部 刀引腳420之内接線421係直接形成為一内引腳424, 且該些内接線421與對應之該些外引腳422之最小夹 角係；丨於90度至180度，較佳的，該些内接線421與 對應之該些外引腳422之最小夹角係以接近18〇度為 例，但實際上並不以此為限。且上述該些部分引腳42〇 上係分別具有一緩衝墊423，其係連接對應之内接線 9 200830507 421與外引腳422。其中，該緩衝墊423 弧邊4 2 5。 於本實施例中，其餘的每一引腳420 係形成為一斜向之扇出線，且連接彼此 424與外引腳422。其中，該緩衝墊423 當地設置於該些引腳420上。當該些扇出 與該些外引腳 422之連接點足以承受 時，該些引腳420可不需設置該緩衝墊 該防銲層43 0係形成於該可撓性介電 局部覆蓋該些引腳 420，更覆蓋該些緩 此，該半導體封裝載膜400能防止外引 線421彎折處發生斷裂。此外，該防銲 一開口 43 1，以顯露該些引腳420之内 端，以供晶片接合。 在第三具體實施例中，揭示另一種防 斷裂之半導體封裝載膜。如第5圖所示 裝載膜500主要包含一可撓性介電層 5 腳520以及一防銲層 530。大致與第一 同這般，該些引腳520係形成於該可撓 上。該防銲層5 3 0係形成於該可撓性介 以局部覆蓋該些引腳520。其中，每一】 有一内引腳523、至少一斜向廣出之内— 外引腳522，其中該内接線521與該外 小夾角係介於9 0度至1 8 0度。其中在部 係可具有一外 之内接線426 對應之内引腳 可視所需而適 之内接線426 可撓曲之應力 423 ° 層4 1 0上，以 衝墊 423 。因 腳422與内接 層430係具有 弓1腳424之内 止引腳彎折處 ，該半導體封 10、複數個引 具體實施例相 性介電層 5 1 0 電層510上， 51腳520係具 後線521與一 引腳522之最 分容易斷裂的 10 200830507 引腳520係更具有一第一緩衝墊541或一第二緩衝塾 542，其係連接對應之内接線521與外引腳522，並且 該防銲層530可覆蓋該些第一緩衝墊541與該些第二 緩衝墊542，以防止該半導體封裴載膜500在管曲使 用時導致外引腳522與内接線521彎折處發生斷裂。 此外，該防銲層5 3 0係具有一開口 5 3丨，以顯露該些 内引腳523之内端，以供晶片接合。 在本實施例中，該些第一緩衝墊5 4 1與該些第二緩 〇 衝墊5 4 2係排列在不同直線上且位於該可撓性介電層 5 1 0之同一側，即該些第一緩衝墊5 4 1排列在一直線 且較靠近該可撓性介電層5 1 0之側緣，該些第二緩衝 墊542排列在另一直線且較遠離該可撓性介電層$ i 〇 之側緣，此種緩衝墊之錯位排列架構可以避免外應力 集中在特定的緩衝墊541或542,進一步降低該些外 引腳522與對應内接線521彎折處發生斷裂之機率。 ( 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實 施例揭露如上，然而並非用以限定本發明，任何熟乘 本項技術者，在不脫離本發明之申請專利範圍内，所 作的任何簡單修改、等效性變化與修飾，皆涵蓋於本 發明的技術範圍内。 【圖式簡單說明】 第1圖：習知半導體封裝載膜之頂面示意圖。 第2圖：依據本發明之第一具體實施例，一種防止引腳彎折 200830507 處斷裂之半導體封裝載膜之頂面示意圖。 圖依據本發明之第一具體實施例，該半導體封裝載膜 應用至一半導體封裝構造之截面示意圖。 第4圖·依據本發明之第二具體實施例，另一種防止引腳彎 折處斷裂之半導體封装載膜之頂面示意圖。 第5圖：依據本發明之第三具體實施例，另一種防幻丨卿弯 折處斷裂之半導體封裝載膜之頂面示意圖。 【主要元件符號說明】 100 半導體封裝載 膜 110 可撓性介電層 120 引腳 121 内 引腳 122 外 引腳 123 扇出線 124 斷 裂處 130 防銲層 131 開 π 200 半導體封裝載膜 210 可撓性介電層 220 引腳 221 内 接線 222 外 引腳 223 緩衝塾 224 内 引腳 225 外 孤邊 230 防銲層 231 開 Π 310 晶片 311 凸 塊 320 封膠體 400 半導體封裝載膜 410 可撓性介電層 420 引腳 421 内 接線 422 外 引腳 423 緩衝墊 424 内 引腳 425 外 弧邊 426 内接線 12 200830507 430防銲層 431開口 500半導體封裝載膜 5 10可撓性介電層 520引腳 523内引腳 530防銲層 541第一緩衝墊 521内接線 531 開口 542第二緩衝墊 522外引腳 ( 1 13200 can be further applied to a semiconductor package construction. Referring to Fig. 3, a semiconductor package structure mainly includes the carrier film 2 and a wafer 3 10 . The wafer 3 1 is disposed on the carrier film 2 and electrically connected to the pins 220. In the present embodiment, the wafer 31 is provided with a plurality of bumps 311' which are bonded to the inner pins 224 of the pins 220. The package construction may additionally comprise a gel 32 〇, such as a point coating gel with high fluidity prior to curing, which seals the bumps 311. The buffer pad 223 is located on the carrier film 2 at a flexible portion between the wafer 310 and the outer leads 222 to avoid stress concentration of the carrier film 200 in a bent state. The bends connecting the outer leads 222 prevent breakage near the bent connection point between the outer leads and the inner wires. In a second embodiment, another semiconductor package carrier film that prevents breakage of the pin bends is disclosed. As shown in Fig. 4, the semiconductor package film 00 mainly includes a flexible dielectric layer 41, a plurality of pins 420, and a solder resist layer 43. The leads 42 are formed on the flexible dielectric layer 4 i 0 of each of the pins 420. In this embodiment, there are an inner wiring 421, 426 and an outer lead 422. The inner wiring 421 of the knives 420 is directly formed as an inner lead 424, and the minimum angle between the inner wirings 421 and the corresponding outer leads 422 is between 90 degrees and 180 degrees. Preferably, the minimum angle between the inner wires 421 and the corresponding outer pins 422 is approximately 18 degrees, but is not limited thereto. Each of the partial pins 42A has a buffer pad 423 connected to the corresponding inner wire 9 200830507 421 and the outer pin 422. Wherein, the cushion 423 has an arc edge of 4 2 5 . In this embodiment, each of the remaining pins 420 is formed as an oblique fan-out line, and is connected to each other 424 and the outer pin 422. The buffer pad 423 is locally disposed on the pins 420. When the connection points of the fan-outs and the outer pins 422 are sufficient, the pins 420 may not need to be provided with the buffer pad. The solder resist layer 43 is formed on the flexible dielectric to partially cover the leads. The foot 420 is covered more so that the semiconductor package carrier film 400 can prevent the outer lead 421 from being broken at the bend. In addition, the solder resists an opening 43 1 to expose the inner ends of the pins 420 for wafer bonding. In a third embodiment, another rupture resistant semiconductor package carrier film is disclosed. As shown in Fig. 5, the loading film 500 mainly comprises a flexible dielectric layer 5 pin 520 and a solder resist layer 530. As is the case with the first, the pins 520 are formed on the flexible. The solder resist layer 530 is formed by the flexible portion to partially cover the pins 520. Each of the internal pins 523 and at least one of the inner and outer pins 522 are obliquely wide, wherein the inner wire 521 and the outer small angle are between 90 degrees and 180 degrees. Wherein the portion can have an outer wire 426 corresponding to the inner pin as desired, and the inner wire 426 can be flexed to a stress of 423 ° on layer 4 1 0 to pad 423 . Since the leg 422 and the inscribed layer 430 have the inner pin bend of the bow 1 424, the semiconductor package 10, a plurality of specific embodiments of the phase dielectric layer 5 10 electric layer 510, 51 foot 520 system The top of the line 521 and the pin 522 are easily broken. The 2008 520 520 has a first cushion 541 or a second buffer 542, which is connected to the corresponding inner and outer pins 521 and 522. The solder resist layer 530 can cover the first buffer pad 541 and the second buffer pads 542 to prevent the semiconductor package carrier film 500 from bending the outer lead 522 and the inner wire 521 during the use of the tube. A break occurred at the place. In addition, the solder resist layer 530 has an opening 5 3 丨 to expose the inner ends of the inner leads 523 for wafer bonding. In this embodiment, the first buffer pads 514 and the second buffer pads 524 are arranged on different lines and on the same side of the flexible dielectric layer 510, that is, The first buffer pads 514 are arranged in a straight line and are closer to the side edges of the flexible dielectric layer 510. The second buffer pads 542 are arranged on another straight line and away from the flexible dielectric layer. The side edge of the $i ,, the misalignment structure of the cushion can prevent the external stress from being concentrated on the specific cushion 541 or 542, further reducing the probability of breakage of the outer lead 522 and the corresponding inner joint 521 at the bend. The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the present invention has been disclosed above in the preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes, and modifications made by those skilled in the art without departing from the scope of the present invention are included in the technical scope of the present invention. [Simplified Schematic] FIG. Schematic diagram of a top surface of a semiconductor package carrier film. Fig. 2 is a top plan view of a semiconductor package carrier film for preventing pin breaks at 200830507 according to a first embodiment of the present invention. In an embodiment, the semiconductor package carrier film is applied to a schematic cross-sectional view of a semiconductor package structure. FIG. 4 is a top plan view of another semiconductor package carrier film for preventing breakage of a pin bend according to a second embodiment of the present invention. Fig. 5 is a top plan view showing a semiconductor package carrier film which is broken at the bending point of another anti-theft illusion according to the third embodiment of the present invention. Main component symbol description] 100 semiconductor package carrier film 110 flexible dielectric layer 120 pin 121 inner pin 122 outer pin 123 fan-out line 124 break 130 solder resist layer 131 open π 200 semiconductor package carrier 210 flexible Dielectric layer 220 Pin 221 Inner wiring 222 Outer pin 223 Buffer 塾 224 Inner pin 225 Outer edge 230 Solder mask 231 Opening 310 Wafer 311 Bump 320 Sealant 400 Semiconductor package carrier film 410 Flexible interface Electrical layer 420 pin 421 inner wiring 422 outer pin 423 cushion 424 inner pin 425 outer arc side 426 inner wiring 12 200830507 430 solder mask 431 opening 500 semiconductor package carrier film 5 10 flexible dielectric layer 520 pin 523 inner pin 530 solder mask 541 first buffer pad 521 inner wiring 531 opening 542 second buffer pad 522 outer pin (1 13

Claims (1)

200830507 十、申請專利範面： 卜-種防止引腳-折處斷裂之半導體封裝載膜，包含： 一可撓性介電層； 複數個引腳，其係形成於該可撓性介電層上；以及 一防銲層，其係形成於該可撓性介電層上，以局部覆蓋 該些引腳； 其中，每-引腳係具有一内接線與一外引腳，該内接線 與該外引腳之最小夾角係介於9〇度至18〇度其中至少 -引腳係具有'緩衝墊，其係連接該内接線與該外引腳。 2、 如申請專利範圍第1項所述之半導體封裝載膜，其中 該緩衝墊係概呈圓形且其直徑大於該内接線之寬度。 3、 如申請專利範圍第所述之半導體封裝載臈其中 該緩衝墊係被該防銲層所覆蓋。 4、 如申請專利範圍第1項所述之半導體封裝載膜，其中 該内接線係為一斜向之扇出線。 5、 如申请專利範圍第！項所述之半導體封裝載膜，其中 該内接線係為一内引腳。 6、 如申請專利範圍第！項所述之半導體封裝載膜，其中 該緩衝墊係具有一外弧邊。 7、 如申請專利範圍第i項所述之半導體封裝裁膜，放中 該些引腳係更具有複數個第—緩衝墊與複數個第二緩衝 塾’該些第—緩衝塾與該些第二緩衝塾係排列在不同直 線上且位於該可撓性介電層之同一侧。 8、 一種半導體封裝構造，包含： 200830507 一載膜’其係包含： 一可撓性介電層； 複數個引腳，其係形成於該可撓性介電層上；以及 一防銲層，其係形成於該可撓性介電層上以局部覆 蓋該些引腳； 其中，每一引腳係具有一内接線與一外引腳，該内接 線與該外引腳之最小夾角係介於90度至18〇度其中至 少一引腳係具有一緩衝墊，其係連接該内接線與該外引 腳；以及 一晶片，其係設置於該載膜並電性連接至該些引腳該 緩衝墊係位於該載膜上介於該晶片與該些外引腳之間之 一可撓曲部位。 9、如申請專利範圍第8項所述之半導體封裝構造，其中 該晶片係設有複數個凸塊，其係接合至該些引腳該封 裝構造另包含有一封膠體，其係密封該些凸塊。 10如申味專利範圍第8項所述之半導體封裝構造其中 該緩衝塾係概呈圓形且其直徑大於該内接線之寬度。 11如申凊專利範圍帛8項所述之半導體封裝構造，其中 該緩衝墊係被該防銲層所覆蓋。 12如申凊專利範圍第8項所述之半導體封裝構造，其中 該内接線係為一斜向之扇出線。 13如申4專利範圍第8項所述之半導體封裝構造，其中 該内接線係為一内引腳。 14、如申請專利範圍第8項所述之半導體封裝構造，其中 15 200830507 該緩衝塾係具有一外弧邊。 15、如申請專利範圍第8項所述之半導體封裝構造，其中 該些引腳係更具有複數個第一緩衝墊與複數個第二緩衝 墊，該些第一緩衝墊與該些第二緩衝墊係排列在不同直 線上且位於該可撓性介電層之同一側。200830507 X. Patent application face: A semiconductor package carrier film for preventing pin-fold breakage, comprising: a flexible dielectric layer; a plurality of pins formed on the flexible dielectric layer And a solder resist layer formed on the flexible dielectric layer to partially cover the pins; wherein each pin has an inner wire and an outer pin, and the inner wire is connected The minimum angle of the outer pin is between 9 degrees and 18 degrees, at least - the pin has a 'cushion pad, which connects the inner wire to the outer pin. 2. The semiconductor package carrier film of claim 1, wherein the buffer pad is substantially circular and has a diameter greater than a width of the inner wire. 3. The semiconductor package of claim 1, wherein the buffer is covered by the solder resist layer. 4. The semiconductor package carrier film of claim 1, wherein the inner wiring is an oblique fan-out line. 5, such as the scope of patent application! The semiconductor package carrier of claim 7, wherein the inner wiring is an inner lead. 6, such as the scope of application for patents! The semiconductor package carrier of the invention, wherein the cushion has an outer arc edge. 7. The semiconductor package film according to claim i, wherein the pins are further provided with a plurality of first cushions and a plurality of second buffers 该 the first buffers and the first The two buffered lanthanides are arranged on different straight lines and on the same side of the flexible dielectric layer. 8. A semiconductor package structure comprising: 200830507 a carrier film comprising: a flexible dielectric layer; a plurality of pins formed on the flexible dielectric layer; and a solder mask layer, Formed on the flexible dielectric layer to partially cover the pins; wherein each pin has an inner wire and an outer pin, and the minimum angle between the inner wire and the outer pin is At least one of the leads has a pad that connects the inner wire and the outer pin, and a wafer that is disposed on the carrier film and electrically connected to the pins The buffer is located on the carrier film at a flexible portion between the wafer and the outer leads. 9. The semiconductor package structure of claim 8, wherein the wafer is provided with a plurality of bumps that are bonded to the pins. The package structure further includes a gel that seals the bumps. Piece. 10. The semiconductor package structure of claim 8, wherein the buffer system is substantially circular and has a diameter greater than a width of the inner wiring. The semiconductor package structure of claim 8, wherein the cushion is covered by the solder resist layer. The semiconductor package structure of claim 8, wherein the inner wiring is an oblique fan-out line. The semiconductor package structure of claim 8, wherein the inner wiring is an inner lead. 14. The semiconductor package structure of claim 8, wherein 15 200830507 the buffer system has an outer arc edge. The semiconductor package structure of claim 8, wherein the pins further comprise a plurality of first buffer pads and a plurality of second buffer pads, and the first buffer pads and the second buffers The pads are arranged on different straight lines and on the same side of the flexible dielectric layer.
TW96100368A 2007-01-04 2007-01-04 Carrier film to prevent cracking at bends of leads and semiconductor package utilizing the film TW200830507A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106855953A (en) * 2015-12-08 2017-06-16 智慧光科技股份有限公司 Magnetic card

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106855953A (en) * 2015-12-08 2017-06-16 智慧光科技股份有限公司 Magnetic card

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