TW200830460A - Method of reducing the parasitic capacitance of ICs and apparatus of the same - Google Patents

Abstract

A method and an apparatus of reducing the parasitic capacitance of ICs are provided. The apparatus includes a first layer, multiple conducting lines, multiple interconnections and a second layer. The method includes steps of forming the interconnections in the first layer, defining a recess on the first layer where the recess contains one or more than one interconnections, depositing a conductive layer electrically connected to the interconnections on the first layer, patterning the conductive layer form the conducting lines corresponding respectively to the interconnections, and depositing the second layer on the first layer where the conducting lines are held in the two layers. The conducting lines are staggered and have height differences between the lines to reduce the parasitic capacitance.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to the field of semiconductor fabrication, and more particularly to an apparatus and method for eliminating parasitic capacitance between wires. [Prior Art] As the advancement of semiconductor manufacturing technology and the increasing demand for use, the density of components in the wafer is also increased to produce better performance. When the density of the component is increased, the line width of the wire must also be reduced to achieve the required size of the wafer. When the line width is reduced (especially when the design rule is below 〇·25 μπι), the effect of the RC-delay effect will become larger and larger and affect the performance of the circuit. The existing method is to reduce the influence of RC_delay, mainly to reduce the equivalent dielectric value, and the method used can be divided into two types: one is to select the ultra-low dielectric constant (Uhra 1〇w_k) The material 'is an air-gapS'. However, the use of ultra-low dielectric constant materials or air gaps is a complicated process in the process, which increases the cost of manufacturing costs. In addition, the dielectric layer formed by the foregoing method has a problem of poor mechanical strength, which causes process challenges in the subsequent back-end process, especially the chemical mechanical polishing (CMP) process and the packaging process. influences. SUMMARY OF THE INVENTION [0007] Therefore, an object of the present invention is to provide a method and apparatus for eliminating parasitic capacitance between integrated circuit conductors for eliminating parasitic capacitance between different conductors in an integrated circuit. According to a preferred embodiment of the present invention The method for eliminating parasitic capacitance between the integrated circuit wires comprises at least forming a plurality of interconnects on the first layer, and forming a plurality of recesses on a surface of the first layer, each of the recesses including at least one of the inner portions a conductive layer is formed on the surface, and the conductive layer is electrically connected to the interconnecting lines, and the conductive layer is patterned, so that the conductive layer forms a wire respectively corresponding to each of the interconnecting positions. Forming a first layer on the surface of the first layer such that the wires located in the recesses and the wires on the surface have a height difference with respect to the surface, so that the second layer is The first layer includes the plurality of wires. According to a preferred embodiment of the present invention, an integrated circuit device capable of eliminating parasitic capacitance between wires includes at least: a first layer and a plurality of interconnects a plurality of wires and a second layer, the first layer having a surface, the interconnecting wires being disposed in the first layer, the wires being disposed on the first layer, and electrically connecting the wires An inner wire having a height difference with respect to the surface, the second layer being disposed on a surface of the first layer, wherein the second layer and the first layer are included The wire has the wires. Therefore, the effect that the invention can achieve is that a height difference can be formed between different wires in the integrated circuit component, that is, a different arrangement of the wires is arranged in a staggered arrangement. The spacing between the wires is increased, that is, the wire spacing is increased to reduce the parasitic capacitance of the line-to-line source. 200830460 When the parasitic capacitance in the integrated circuit component is eliminated, the resistance can be improved. The effect of the RC-delay effect increases the efficiency of the circuit. In addition, the use of ultra-low dielectric constant materials or air gaps is eliminated, which reduces manufacturing costs and maintains mechanical strength. Will not continue The latter stage process has an influence. [Embodiment] Please refer to Fig. 1, the parasitic capacitance in the integrated circuit can be mainly divided into two source items, one is the line-to-line (line_t (Mine, cL), the other is Layer-to-Layer (cv). Therefore, total parasitic capacitance (T〇tal

Parasitic Capacitance, CT) is equal to cv plus 2Cl (Ct = Cv + 2Cl). that is,

Cy= C/L = WA1 ε 〇χ/Τ〇χ (1) CL= C/L=TAi ε 〇x/SA1 (2) where 'WA1 is the width of the wire, τΑ1 is the height of the wire, and sA1 is the spacing between the wires , ε ο χ and Tox are the dielectric constant and thickness of the dielectric layer.

The parasitic capacitance of the Cv source term decreases as the wire size shrinks, and the parasitic capacitance of the CL source term increases exponentially as the wire size shrinks. Please refer to Fig. 2 further. Since the capacitance value of the dielectric material is inversely proportional to its thickness, adjusting the effective height Tai and the spacing SA1 between the wires 1 can reduce the parasitic capacitance of the Cl source term. It can be known from equation (2) that if the effective height TA1 between the turns 1 or the increase of the pitch SA1 can be reduced, the parasitic capacitance of the CL source term can be reduced (in the second figure, SAL1, SAL2 200830460, and SAl3 respectively represent different wires). The spacing sA1). According to a preferred embodiment of the present invention, an integrated circuit device for eliminating parasitic capacitance between wires includes a first layer 200, a plurality of interconnects 300, a plurality of wires 1〇〇, and a second layer 4〇〇. The interconnecting wires 3 are provided in the first layer 200, and the interconnecting wires 300 can be formed by using a tungsten plug. The first layer 200 is provided with the wires 100, and the wires 100 are electrically connected to the interconnect wires 3〇〇, respectively. For those of ordinary skill in the art, it should be recognized that the number of interconnects 300 and wires 1 may actually be in the millions or more, and the connection between the interconnects 300 and the wires 1〇〇 It is a design choice, that is, each wire 100 is selectively connectable to a predetermined interconnect 300. A layer 400 is disposed on the first layer 200, wherein the second layer 400 and the first layer 200 include the wires 1〇〇. There is a height difference between the wires 1 ,, for example, there may be a height difference between adjacent wires 1 、, a height difference between adjacent pairs of wires 100 or other wire arrangement Combination (ie, there is a height difference between different wires 1〇〇) and the like. Also in this embodiment, the method of eliminating the parasitic capacitance between the integrated circuit wires is mainly to form a height difference between the different wires 1〇〇. Referring to Figure 3, the method mainly forms a first layer 200, which may be a layer of germanium dioxide (Si 2 ). A plurality of interconnects 300 are formed on the first layer 2''. The interconnect 300 can be formed in a plug process. In this embodiment, the plug is a tungsten plug process. For those of ordinary skill in the art, it is possible to form a through hole 301 in the first layer 200 by the tungsten plug process of 200830460, and after chemically grinding (CMP) after the through hole 301 is filled with tungsten metal. After the tungsten plug structure.

ί. «Monthly reference to FIG. 4 and FIG. 5 do not form a plurality of recesses 202 on a surface 201 of the first layer 200 (only one is shown for convenience of explanation), each of the recesses The 202 series includes at least one interconnect 300 (for ease of illustration, only one interconnect 3 包含 is shown). In this embodiment, the method of forming the recess 202 is mainly to apply a photoresist layer 5 on the first layer 200 and pattern the photoresist layer 5, and then form the recess 202 by using a dry etching process. Thereafter, the photoresist layer 500 is removed. Wherein, in the dry etching process, the first layer 200 and the interconnect 300 located in the recess 202 are etched such that the top of the interconnect 3〇3 located in the recess 2〇2 is lower than the first The surface of the layer is 2〇1 (as shown in Figure 5). Referring to FIG. 6 in May, a conductive layer 6〇〇 is formed on the surface 2〇1, and the conductive layer 600 is electrically connected to the interconnect lines 3〇〇. In the present embodiment, the "Hyle V electrical layer 600 comprises aluminum and the in-situ conductive layer 600 can be formed using a physical vapor deposition (pvD) process. After the conductive layer 600 is formed, the conductive layer 6 is patterned to form a conductive line 600 corresponding to each of the interconnect lines. Thereby, the wires 1〇〇 located in the recesses 2〇2 and the wires 100 on the surface 201 have a height difference with respect to the surface (as shown in Fig. 1). The manner of patterning the conductive layer 600 mainly includes planarizing the conductive layer 600' to form a flat layer 7 on the conductive layer. In this embodiment, the flat layer 7 is an anti-reflective coating (200830460 coating), and the anti-reflective coating is applied by spin coating. Further, referring to Fig. 7, a mask layer 800 is formed on the flat layer 700. In this embodiment, the mask layer 800 can be a photoresist layer. The mask layer 800 is patterned to form a patterned mask layer 81A. Referring to Fig. 8, the patterned mask layer 810 is subjected to chemical biasing. In this embodiment, the patterned mask layer 81 is plated using a Silylation process. Referring to FIG. 9 and FIG. 10, the flat layer 6 is patterned. The planarized layer 7Q0 is etched using the mineralized patterned mask layer 81 until the conductive layer 600. Thereafter, a patterned planarization layer 710 is formed. The patterned mask layer 810 is removed. The conductive layer 60 is patterned by using the patterned planarization layer 710 to etch the conductive layer 600 until the first layer 200 is removed. The conductive lines 100 are removed to form the conductive lines 100. In this embodiment, etching the planar layer 700 and etching the conductive layer 600 uses dry etching. Referring to FIG. 11, the second layer 400 is formed on the surface 201 of the first layer 200, and the wires 100 are included between the second layer 400 and the first layer 200. The second layer 400 can be a layer of silica dioxide (si〇2). Referring to Fig. 12, when the present invention is actually applied to an integrated circuit, a height difference can be formed between adjacent wires 100. Referring to Fig. 13, when the present invention is actually applied to an integrated circuit, a height difference is formed between adjacent pairs of wires 100. Thereby, a height difference can be formed between the different wires 1〇〇 in the integrated circuit component. This increases the spacing between the different conductors 100, that is, increases the sA1' of 200830460 to reduce the parasitic capacitance of the cL source term (see Figure i). Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious, the detailed description of the drawings is as follows: FIG. 1 is in the integrated circuit, the capacitance and A diagram of the design rules. 2 is a schematic diagram of an integrated circuit device capable of eliminating parasitic capacitance between wires according to a preferred embodiment of the present invention. 3 to π are schematic views showing a flow of forming a wire in a method for eliminating parasitic capacitance between conductors of an integrated circuit according to a preferred embodiment of the present invention. Figure 12 is a schematic view showing the formation of a height difference between adjacent wires in accordance with the present invention - a preferred embodiment of the integrated circuit t. Figure 13 is a view showing the difference in height between adjacent wires in an integrated circuit in accordance with the preferred embodiment of the present invention. 4〇〇: second layer 500: photoresist layer [main component symbol description] 1〇〇: wire 200: first layer 12 200830460 201 : surface 600: conductive layer 202: recess 700: flat layer 300: interconnect 710 : Patterned Flat Layer 301 : Through Hole 800 : Mask Layer 810 : Patterned Mask Layer

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Claims (1)

200830460 X. Patent application scope: 1. A method for eliminating parasitic capacitance between conductors of an integrated circuit, comprising at least: (a) forming a first layer; (b) forming a plurality of interconnects on the first layer; Forming a plurality of recesses on a surface of the first layer, each of the recesses comprising at least one interconnecting line; (4) forming a conductive layer on the surface and electrically connecting to the interconnect lines; (e) patterning the conductive layer such that the conductive layer forms a wire respectively corresponding to each of the interconnect lines to enable The wires of the recesses and the (four) wires on the surface respectively have a height difference with respect to the surface; and (1) forming a second layer on the surface of the first layer, so that the second layer and the first layer The wires are included between the layers. 2. A method of eliminating a parasitic capacitance between integrated circuit conductors as described in claim 4, wherein the step (8) comprises forming the interconnections using a plug process. 3. The method for eliminating the capacitor of the patent application range, wherein the plug process between the integrated circuit wires of the two items is a tungsten plug process. 4. The method for eliminating the capacitance of the integrated circuit between the integrated circuit wires described in claim 1 of the patent application, wherein the step (4) comprises forming the concave portion by using a dry etching process, and the first sound is η... A ^ etching process column, with # # &quot;&lt; in each of the recesses in the inner line of the eclipse. The top of the interconnect in each of the recesses is lower than the step of the first layer (in the sentence, the conductive layer contains aluminum. The electroporation-transfer vapor deposition (PVD) process forms a conductive layer. The method for separating the integrated circuit wires according to the item 1 of the method of using the material of the present invention, wherein the step (e) comprises a flat layer of 4 conductive layers, forming a flat layer Forming a mask layer on the flat layer; patterning the mask layer to form a patterned mask layer; plating the patterned mask layer; using the mineralized patterned mask The cap layer is etched into the layer until the conductive layer; the patterned mask layer is removed; the acoustic layer V electrical layer 'subscribes the conductive g using the patterned flat layer until the first Up to the layer; and 15 200830460 to remove the flat layer. 8. The method for eliminating parasitic capacitance between integrated circuit wires as described in claim 7 wherein the flat layer is an anti-reflective coating (Anti-reflective) Coating) 〇9·Integrated battery as described in item 8 of the patent application The method for eliminating parasitic capacitance between the wires of the circuit, wherein the anti-reflective coating is coated by a spin-on method. 10. Elimination of parasitic electric valleys between the integrated circuit wires as described in claim 7 The method, wherein the mask layer is a photoresist layer. • The method for eliminating parasitic capacitance between integrated circuit wires as described in the first paragraph of the patent application scope, #, the patterned mask layer is used The Silylation process is plated. • The method of removing the capacitance between the integrated circuit wires as described in the seventh paragraph of the patent application scope, the towel is etched using the dry (four) conductive layer. - 曰 曰 电 电 , , , , , 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 The method for eliminating the parasitic capacitance between the conductors of the integrated circuit described in the patent application scope ^^^^^ 固芙i item, complex Φ, 夂分^ — ', each "concave system contains an interconnection line, worse, The adjacent wires are respectively ^ (7) /, which is relative to Height difference surface 0 For example, the method for eliminating the parasitic capacitance between the integrated circuit wires described in the item i of the patent-monthly patent, wherein each of the recesses comprises two interconnecting lines, and the adjacent ones have the same The difference in height from the surface. 16. An integrated circuit device capable of eliminating parasitic capacitance between wires, comprising at least: a first layer having a surface; a plurality of interconnects disposed in the first layer; a plurality of wires, 5 in the a layer, and electrically connecting the interconnect lines ' respectively, and each of the (10) has a height difference with respect to the surface; and a second layer disposed on the surface of the first layer, wherein The wires are included between the second layer and the first layer. 17. The device of claim 16, wherein the (four) line is a crane plug. 17 </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; An integrated circuit device in which a ruthenium oxide layer. 20. The integrated circuit device of claim 16, wherein the height difference is relative to the surface. 21. The integrated circuit device of claim 16, wherein the adjacent-pair conductors have a height difference with respect to the surface. 18