TW200830178A - Method and system of executing a sequential program and a cache management unit thereof - Google Patents

Abstract

A system for executing a sequential program comprises a NAND flash, a processor, a cache , and a cache controller. The NAND flash is configured to store the sequential program and the processor is configured to execute the sequential program. The cache with a size of about twice the maximum offset of a conditional jump of the sequential program is configured to store instructions received from the NAND flash. And a cache controller is configured to control the instructions stored in the cache. The cache controller is further configured to maintain a program counter that indicates the current location of execution of the sequential program by the processor. Besides, the cache controller is configured to maintain in the cache instructions with addresses within the range of the program counter minus the maximum offset of a conditional jump to the program counter plus the maximum offset of a conditional jump.

Description

200830178 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a quick-recovering-snake-snake, a τ 匕, a body 兀 理. In particular, there is a NAND flash test and method for the Axe J. The system for storing and executing the gate-sequence program [Prior Art] The NAND-type flash memory is used to store data devices such as a USB flash drive, a digital camera, and a fat player. Compared to its body-shaped flash memory, N-type flash memory can be used in later, lower cost, and faster write and erase times. Face D ^ flash memory can usually be erased and written quickly, but it is slow to read non-contiguous data through the serial port. SUMMARY OF THE INVENTION The present invention discloses a system for executing a sequential program, comprising: __ _ 厕 垔 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 岭 。 。 。 。 。 。 。 。 。 。 。 。 。 (d) The system also includes - the cache memory is configured to store instructions received from the lion-type flash memory. The system also includes a cache controller configured to control instructions stored in the cache. Multiple embodiments of the system can include the following ones at most

Wt η The cache memory can have the highest capacity - the capacity is equal to or greater than -

Client’s Docket Ν〇·:94-062 ΓΓ. Docket No: 〇492-A40896.TW/Final^ta/2〇〇7/〇1/〇5 6 200830178 2 times larger offset. The cache controller is configured to maintain a program counter to indicate the current location of the sequence program executed by the processor. The cache controller is further configured to maintain an instruction in the cache memory, the address range of which is assigned from the program count to the maximum offset of the conditional jump, to the program counter plus a conditional jump Maximum offset. The cache controller is further configured to determine whether a target address is stored in the cache memory in response to a skip command received by the processing benefit; the target address is stored in the 'Change the program to the target address when the memory is cached. The cache controller is further configured to determine, when the target address is not aged in the cache memory, clear the cache and pass the target N-type flash memory body. When the skip command is a -forward command and the address is stored in the wire memory = the control gain is further configured to continuously fetch additional instructions from the d-type flash memory. The cache memory can be a device for catering to the device. The invention is further disclosed in the present invention. The first interface is configured from the biliary D-frequency The N-lion flash memory, and the second interface are configured to process the crying transmission and receive the data. Cache memory management unit purely - silk record (four) is received by the singularity of the memory. ' ^ Multiple embodiments of the foregoing system may include one or more of the following fk 〇

Clients Docket No. :94-062 TT^s Docket No: 〇492-A40896-TW/FinaL^Rita/2007/01/〇5 7 200830178 The cache can have a capacity equal to or greater than a condition The skip most of the cache controller is configured to maintain a program counter (PC) to indicate the current location of the sequence program executed by the processor. The cache controller is further configured to maintain instructions in the cache. In some embodiments, such as -SRAM, in accordance with the size range from PC+CW to PC-〇_et), is configured to store data, where 〇 is the absolute offset of the conditional jump. When a skip instruction is issued, storing the address between PC+〇(offset} to Pc_~out(4) can reduce the waiting time because the target address is already stored in the SRAM towel. Therefore, Lai Ship-New The address is to the NAND type flash memory. The above objects, features and advantages of the present invention will become more apparent and understood. The following specific embodiments, together with the accompanying drawings, are described in detail below. Referring to Fig. 1, a system 10 is shown comprising a _D type flash memory 22 as a program R 〇 M. The system 1 〇 also includes a microprocessor unit I2 (MPU), and a cache memory In general, the MPU U interprets and executes the instructions. However, the Mpu 12 does not directly access the NAND type flash memory & but uses the cache memory management unit 14 to access the NAND type. The flash memory a and the program stored therein. ^ The cache memory management unit 14 includes: a cache controller 6

Clienfs Docket No.:94-062 TT,s Docket No: 〇492-A40896-TW/Final/Rita/2007/01/〇5 200830178 A NAND interface; l 8 and a srAM :> n 斗^上ΑΜ 20. The cache controller 16 controls and manages the SRAM 2. The content stored in it. The cache controller W reads the program from the D-type flash memory 22 and then stores the program to the SRAM 2 port. MPU u can access the program of _ shooting. The NAND interface 18 provides a communication path between the memory management unit 14 and the ΝΑλτη _ u* 兀 兀 14 and the _D type flash memory 22. The k4 cache memory management unit 14 uses the NAND interface 18 to receive programs from the coffee flash memory 22, as well as transfer address and instructions to the n-type flash memory 22. In some embodiments, the D-type flash memory 22 stores a sequential program of sequential execution instructions. During the execution of the sequential program by the MPU 12, a conditional skip or an unconditional jump may occur. - The conditional jump is when a particular condition is met, an instruction is used to jump to - (c) to indicate the address, and the program is executed at the target address. - The more unconditional peaches are, under any conditions, an instruction is used to jump to a target address. The absolute offset of a conditional jump of the MPU 12 is represented here by a variable, 'o(offset) 〃. Referring to Fig. 2, an exemplary block diagram of the memory location in SRAM2 is shown. The SRAM 20 is configured with a minimum capacity of 2 times a conditional skip: 2*Q_et)). In the case of 1st, the magnitude of the offset is about 128 to " 2768, so the fast capacity of the SR_ 2〇 is between 25 " 65536. - has ~set)

Clienfs Docket No.:94-062 TT5s Docket No: 0492-A40896-TW/Final/Rita/2007/01/05 9 200830178 跳跳0 Recalling 'Allow coffee 12 to skip forward or reverse a conditional jump The cake offset, λ,, 0 (offset) 〃 ' does not require the cache controller I6: two addresses to the type-flash memory 22. When it is necessary to perform -2〇, P, and 'unconditional jumps, by storing the set of instructions, the SRAM U, # transmits a new address and receives the NAND type flash memory; the bucket-related delay' And can provide the benefit of reducing the delay time. : ° 冨 5 S SRAM 2 〇 is not accessed by the MPU 12 H Xuan Cache Controller 16 automatically grabs the material from the n-type flash memory. The cache control is difficult to continue to grab data from the face (four) flash memory ^ until the test 2 is full. When the sram2〇i is full, the cache controller 16 waits for the extra material to be fetched from the N-type flash memory ^ until the sneak has been accessed in the SRAM 2 ' because the SRAM2Q Some of the information is no longer available; C plus 〇 (〇ff 3 Du) or p C minus 〇 (治3杜) can be overwritten. During execution of the program, the MPU 12 can span pages or span blocks. A block includes, for example, 32 pages or 64 pages. All pages of the same block are the same block address. When the MPU 12 straddles a new page with one of the same block addresses as the previous page, there is no need to find a new block address. The cache controller 16 automatically generates a read command and transmits the address to the NAND t h flash memory 2 2 ' to fetch the new page. When spanning blocks, you must decide

Client's Docket No.: 94-062 TT^ Docket No: 0492-A40896-TW/Final/Rita/2007/01/05 200830178 Fixed_block address. Therefore, when the Mpu 12 spans the block, the cache controller 16 does not fetch new data from the deleted flash memory 22. Conversely, the cache controller 16 generates a _read error signal. As described above, the D-type flash memory 22 stores a sequential program. Although the sequence program is executed 12, the cache controller η obtains the required data from the surface d-type flash clock 22 and (4) stores the material until the s_ 2 〇 is generally continuous. Therefore, during execution of the program by _12, the cache controller 16 attempts to be in the SRAM 2. The address from 仏〇(.na to PC+0(offset) is maintained (that is, the data stored in the current program counter and the offset of the program counter 〇(〇ffset)). It is stored in SRAM 20. Actual address, at any given time, the required range from pc_〇(.(10) to PC+0(offset) will change slightly, because accessing the SRAM 2〇 and accessing the surface D-type is fast. Flash memory a takes time. % Referring to Fig. 3, it is shown that when the - forward conditional jump is encountered, the flow of the information is obtained by the flash controller through the cache controller. When the MPU I2 executes an instruction according to a condition, it encounters a forward conditional jump. If the condition is met, the program skips to an address located after the current execution address (referred to as the target address). The maximum offset of the forward conditional jump is denoted as 〇, 。. When the MPU 12 receives (52) - the forward conditional jump and meets the condition 'the cache controller I6 determines (54) The goal of the positive condition Tao Yue

Client’s Docket Ν〇·:94-062 TT^ Docket No: 0492-A40896-TW/Final/Rita/2007/01/〇5 11 200830178 Whether the address is in a SRAM20. If the target address is not in _μ2〇, the cache controller 16 clears (56) the location, and transmits (6〇) the target address to the NAND-type flash memory 22 to The birch address began to crawl the new program. If the target address is in the SRAM 2, the target address is not required to be transferred to the NAND flash memory 22. Conversely, the cache controller 16 sets (58) the program counter (pc) to the destination address. When the MPU 12 does not access the SRAM 20, the cache controller is also from! ^+1 to Pc+〇(〇ffset) to get the program. When the target address of the conditional jump is in the SRAM 2◦ and there is no new address only transmission | the ISLAND type flashes the memory, since the help flash is still continuously transmitted The data is sent to the SRAM 2G, so during the -forward conditional skip period, the delay time for transmitting a new address to the NAND-type flash memory U and waiting for the NAND-type flash memory a to prepare data is eliminated.

Figure 4 of the multi-test shows a flow 70 for obtaining information from the D-flash memory 22 through the cache control n le' when a reverse conditional jump is encountered. When the MPU 12 executes an instruction according to a condition, it encounters a reverse conditional jump. If this condition is met, the program skips to an instruction, which is located in the address before the address (referred to as the target address). 1 The maximum offset of the reverse conditional jump is denoted as ', _〇 (〇 ffset), 〇 When the MPU 12 receives (72) a reverse conditional jump and matches, the cache controller 16 determines (74) The reverse condition is difficult to see

Client’s Docket N〇.:94-062 TT’s Docket No: 0492-A40896-TW/Final/Rita/2007/01/05 12 200830178 Whether the address is in this SRAM 2 file. If the address of the address is not in SRAM 2, the cache controller 16 clears/saves (76) the SRAM 2〇 and transmits (7 8 ) 4 mesh; ^ address to the type 丨 > K Flash memory 22 to capture the new program from the target address. If the right address is in the SRAM 20, the target address is not transmitted to the flash memory 22. Conversely, the cache controller I6 sets (80) 哕 1 〇) ° private counter (PC) to the target address. Because the program of the requested target address has been stored in the SRAM, the job is not captured from the type of flash memory 22, so the lion type is not required. Body 22 grabs any new information. More specifically, the cache controller 16 does not immediately grab any additional data from the zero-type flash memory 22 until a portion of the instructions currently stored in the SRAM 20 are executed. When the target address of the reverse condition jump is in the SRAM 2, since the face D-type flash memory 22 only delays transmitting additional data to the SRAM 2 0 (but the data is still transmitted continuously), - During the reverse conditional jump, the delay time of the transfer-new address to the curry type flash memory 22 and the isochronous flash memory file preparation (4) is eliminated. Referring to Fig. 5, the flow of information obtained by the _D type flash ticker 22 through the cache controller 16 is shown when an unconditional jump or a call function is encountered; !_〇〇. When ΜΡυ 12 receives (1〇2) an unconditional skip, the cache controller 16 determines (1〇4) whether the target address of the hop is in the SRAM 2〇. If the target address is not in the SRAM 2〇,

Clienfs Docket No. :94-062 TT5s Docket No: 0492-A40896-TW/Final/Rita/20〇7/〇1/〇5 13 200830178 Then the cache controller 16 clears (1〇6) the SRAM2〇, And, the target address to the NAND type flash memory & to fetch the new program from the transmission of 11 (1〇8). If the target address is in the sram directory address

Send the target address to the NAND type flash memory (2). The phase does not need to pass the controller to set (110) the program counter to the ground, the address. Next, the cache controller 16 determines whether there is a stripless two: whether the target bit is a reverse skip or a call (112). If the no-following or calling is not a reverse skip or call (for example, a forward peach or a call, the cache controller 16 maintains the slave in the SRAM 2), PC+0 (offset) The address (11S). If the offset of the skip is (C)ff, it is necessary to delay the capture of the extra flash from the NAND flash memory 22, in which case the cache memory retains the command in the SRAM. In PC_〇(〇ffset) to PC +〇(offset) ( 1 14 ). The first 6A_6G diagram is based on the flow described above, during the execution of one of the sequential programs in SRAM 2, providing the cache control boundary; one of the various conditions of the reaction. In Figure 6A-6G, by " (b), the time indicated by Τ = 不 does not represent a single-time step or period of the MPU 12. Referring to Figure 6 'Before time Τ = ,, the SRAM 2 〇 is empty. In order to fill the S RAM 2 0 ' at time T = ,, the cache controller 传 6 transmits a bit address '' to the NAND-type flash memory 22. The NAND flash memory

Client's Docket Ν〇.:94-062 TT5s Docket No: 0492-A40896-TW/Final/Rita/2007/01/〇5 14 200830178 Memory 22 will start at address, 'A,, pass (such as block 122 2: 'The axis order will be stored in the address set to the request, ie two: arrow two _

, quote, 2〇 No. Since the NAND genre stores the 1-sequence program, there is no need to transmit a new address to the type 7, _«22, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ At the time, the fast coffee 16 fills the remaining portion of the SRAM 20. Since the MPU 12 executes the command, the speed is slower than the dirty one.

s Check the speed of Λ0, which will fill the address A+1 to A+2D (offset)-1 with the success score of the program as shown in the section. The absolute offset of a conditional jump is a variable, '◦(~" indicates. The actual offset of any special conditional jump can be any value smaller than the ratio '0(offset)〃. Refer to Figure 6B, in Time T=1, Mpui2 has executed the address to M〇(offset> instruction. Since Mpuu has executed the instruction at address A to A+〇(offset), the program counter is set to a+〇(4)^(4)) As indicated by the arrow 130. Therefore, at time T=1, the cache memory stores instructions from pc_〇(.(4)) to PC+〇(offset) (for example, from a to. Reference to the SC map' when the time is from T When =1 is increased to τ=2, Mpu 12 has executed the instruction to address A+〇(offset), and the program counter is increased from A+〇(〇ffset) to A+O^ffset^+l, as indicated by arrow 132. When the program counter is incremented to A+O^ffse^+l, the cache controller attempts to maintain the slave in SRAM 2〇

Client's Docket No.: 94-062 TT’s Docket No: 0492-A40896-TW/Final/Rita/2007/01/05 200830178 - PC-Offset} to the address. Therefore, the cache controller 6 overwrites the cache memory location of the address a (shown by arrow Af) at address T + 1 with the address A + 2 〇 (offset). Therefore, when the time T = 2, the program count boundary is located at A + 〇 (offset) + 1, and the address Α +1 to A + 2 〇 (〇 ffset) is stored in the rupture 20. Referring to FIG. 6D, between time τ=2 and T=3, a positive conditional jump with one of the target addresses A+2〇(Qffset)-1 is satisfied, or an unconditional 'forward jump The more. Since the address address is stored in the SRAM 2, the cache controller I6 does not need to transmit a new address to the NAND type flash memory 22. The cache controller 16 changes the program counter to the target address, i.e., A + 2 〇 (offset) -1, as indicated by arrow I34. Since a forward jump has occurred, the portion of the cache memory 36 is overwritten to maintain the SRAM address in the range of PC-〇 (offset) to PC + 〇 (offset) (since the program counter is A+2〇(offset)-l, so the cache controller tries to provide i A+〇(offset) to A+3〇(offset wide 1) in sram 2〇. Especially in order to maintain the SRAM 2〇 The range required by the cache controller 16 overwrites one part of the sRAM 2 丄 36 with an address range of A+2〇(offset)+l to A+3〇(offset)4, the part The copy previously contains the address Α+ι to A+〇(〇ffset). Referring to the 6E®, at the time of the temple, the target address Α+0 (.Off-there is a conditional reverse condition jump, Or - unconditional reverse skip. Since the address α + 〇 (ο £_ stored in sram 2〇, the cache control

Client's Docket No. :94-062 TT^ Docket No: 0492-A40896-TW/Final/Rita/2007/01/〇5 16 200830178 • I6 does not need to transmit a new address to the NAND flash memory 22 . To complete the jump, the cache controller I6 only changes the program counter from A+2〇(Qffset) (i.e., the program counter at time T=3) to the target address A+〇(Qffset). When the program counter is changed to A + 〇 (offset), the address from A + 〇 (offset) to A + 3 〇 (offset) -1 will remain in the SRAM 20. Therefore, there will be a period of time during which the SRAM 2 stores the instruction from ^ to PC + 2 〇 (〇 ffset) instead of from pC - off (offset) to pc + 〇 (offset). As shown in Figure 6F, due to time τ=4

Shou 2, SRAM 2 0 contains the range of pc to pc + 2 〇 (offset), will not receive any new data and store any new data to the 2 〇 by the NAND flash § 丨 丨 〇 22 until the The program counter A+〇(offset) is increased to A_2〇(〇ffset is wide, so the range of PC-〇(offset) to PC+〇(offset) is once again stored to 31^^/[ 2〇 (eg·········· (offset) to A+3〇(offset)-l and the program counter is A+2〇(〇ffset) -1) 〇 Refer to the 6G diagram. At time τ=6, the address is not in the ι One of the SRAM 2〇 conditions or an unconditional jump. The target address λ, Β〃 is not in the SRAM 20. To fill in the SRAM 20, the cache controller 16 transmits the target at time Τ=6. The address is transferred to the NAND type flash memory 22. The NAND type flash memory μ will start transmitting instructions at the address b, and the instructions will be stored to the SRAM 20. The program counter (PC) is set to the required The address, that is, the address B, and when the yiPU 2 0 does not access the SRAM 2, the cache controller I6 fills with the address B+1 to B + 2〇(offset)-!

Client’s Docket N〇.:94-062 TT s Docket No: 〇492-A40896-TW/Final/Rita/2007/01/05 200830178 , the remainder of the SRAM 2 0. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

Client's Docket No.:94-062 TT's Docket No: 0492-A40896-TW/Final/Rita/2007/01/05 18 200830178 [Simplified Schematic] Figure 1 shows a block diagram of a memory access system; Figure 2 shows a block diagram of a cache memory; Figure 3 shows a flow chart of a forward conditional skip step; Figure 4 shows a flow chart of a reverse condition skip step; Figure 5 shows an unconditional jump Flowchart of the steps; Figures 6A-6G show cache memory consistent with the embodiment to store information from the NAND. [Main component symbol description] 1 0~ 糸, 12~ microprocessor unit (MPU); 14~ cache memory management unit; 16~ cache controller; 18~NAND interface; 2〇~SRAM; 2 2 ~ NAND type flash memory.

Client’s Docket No·:94-062 TT^s Docket No: 0492-A40896-TW/Final/Rita/2007/01/05 19

Claims (1)

200830178 X. Patent application scope: 1. - Used to execute a sequential program - NAND flash flash memory, first included. 仏 破 配置 以 以 馆 馆 馆 馆 馆 馆 馆 馆 馆 馆 馆 一 一 一 馆 一 馆 一 一 一 一 一 ; ; ; ; ; ; ; ; ; , a cache memory is configured to store instructions, the maximum offset received by the size of the silk coffee; "and ... 4 phase - conditional jump ΓΓ ^ Γ tree / control compiled in the record shop instruction. • As stated in the first paragraph of the patent scope, the system is cumbersome, wherein the cache memory has the minimum capacity of the _, 2 division = line-sequence program.最大 2 L is the maximum offset of a conditional jump. 3. A system for executing a sequential program as described in the scope of the patent application, wherein the cache memory has a capacity equal to a large jump. Moved twice. /, 越出取4. The system, wherein the cache controller is further configured to execute a program counter of the execution-sequence program as described in claim 1 to maintain instructions in the cache memory The range of the address is the maximum offset of the conditional skip minus the conditional jump, and the program counts the maximum offset of the I-hop on the crying force. /' 5. For performing a sequential system as described in claim 4, wherein the cache controller is configured to: Client^ Docket No.: 94-062 TT^ Docket No: 0492-A40896 -TW/Final/Rita/2007/01/05 20 200830178 In response to determining whether a target address is stored in the cache memory, one of the skip commands received by the processor; and when the target address When stored in the cache memory, the device is changed to the target address; and X ^ is cleared when the target address is not stored in the cached U body, and the cache memory is cleared. Transmitting the target address to the NAND flash / ί 6· The system for executing a program of a person program as described in item s of the patent application' wherein the cache controller is further configured to continuously fetch from the coffee _ flash memory An additional instruction when the skip command is a forward skip command and the address is stored to the cache. The system for executing a sequential program, as described in Section 5, wherein the cache controller is further configured to delay _ surface D-type flash memory capture for additional The instruction, when the skip command is a reverse skip command and the address is stored to the cache memory. / 8. A system using a pure-sequence program as described in the scope of work of the patent scope, wherein the cache memory is an SRAM device. 9. A cache memory management unit, comprising: - the - interface - is configured to receive from - NAND type flash memory - sequential program 'and view age miscellaneous D type (four) memory; a second interface, Configured to transmit and receive data from the processor, the process is configured to execute the sequence program; Client's Docket No .94-062 wketN_2.A4G896_Tw/Fina_2__ 21 200830178 l Cache though "Configuration _ 贱 贱 D D The received '^' is the largest (four) times the maximum offset of the condition; the instruction. Wherein - (record) (four) H is configured to exhaust __ cache memory to perform a sequential program, including: by - NAND flash memory - partial sequence program; cache memory; Part of the sequence program received by the D-type flash memory to - maintain - the program H, mail the _ test of the position of the line; the memory of the received part of the sequence program including the storage instructions, and the range of bits Subtract from the program counter - the conditional retrace maximum offset, to the maximum number of deviations from the conditional jump. 11. The method for executing a sequence program as described in claim 1 of the patent application, further comprising executing the sequence program. II. The method for executing the one-sequence program as described in claim 10, further comprising: determining whether the target address is stored in the cache memory in response to the processor Receiving one of the skip commands; and when the target address is stored in the cache, the changer to the target address; and Client's Docket Ν〇:: 94-062 TT's Docket No: 0492-A40896 -TW/Final/Rita/2007/01/〇5 22 200830178 When the target address is not stored in the cache (4), the cache memory is cleared and the target address is transmitted to the _D touch flash Memory. I3. The method for executing a sequential program as described in the scope of the patent application, 'including when the skip command is a -forward_command and the address is stored to the cache,' from the coffee D Wei flash memory cap continues to grab additional instructions. 14• The method for performing a sequential program as described in claim 12 of the patent application further includes: when the skip command is a reverse simple command and the address is stored in the cache memory, the delay is from the Grab extra instructions in the _ flash memory. 15. The green memory of the singular-sequence program described in the above-mentioned application is a sub-capacity of -2 times the maximum offset of the conditional jump. w (4) Executing the _sequence program tr as described in the first item (1), wherein the cache memory has a capacity equal to twice the maximum offset of the - conditional jump. Client’s Docket No.:94-062 TT5s Docket No: 0492-A40896-TW/Final^lita/2007/01/05 23