TW200828780A - Crystal oscillator emulator - Google Patents

Crystal oscillator emulator Download PDF

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Publication number
TW200828780A
TW200828780A TW96138629A TW96138629A TW200828780A TW 200828780 A TW200828780 A TW 200828780A TW 96138629 A TW96138629 A TW 96138629A TW 96138629 A TW96138629 A TW 96138629A TW 200828780 A TW200828780 A TW 200828780A
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Taiwan
Prior art keywords
temperature
circuit
oscillator
integrated circuit
frequency
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Application number
TW96138629A
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Chinese (zh)
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TWI429187B (en
Inventor
Sehat Sutardja
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Marvell World Trade Ltd
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Priority claimed from US11/649,433 external-priority patent/US7768360B2/en
Priority claimed from US11/732,304 external-priority patent/US7791424B2/en
Application filed by Marvell World Trade Ltd filed Critical Marvell World Trade Ltd
Publication of TW200828780A publication Critical patent/TW200828780A/en
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Publication of TWI429187B publication Critical patent/TWI429187B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H03L1/022Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
    • H03L1/026Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature by using a memory for digitally storing correction values
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H03L1/022Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
    • H03L1/027Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/substract logic circuit
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L5/00Automatic control of voltage, current, or power
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/16235Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A crystal oscillator emulator integrated circuit comprises a first temperature sensor that senses a first temperature of the integrated circuit. Memory stores calibration parameters and selects at least one of the calibration parameters based on the first temperature. A semiconductor oscillator generates an output signal having a frequency, which is based on the calibration parameters, and an amplitude. An amplitude adjustment module compares the amplitude to a predetermined amplitude and generates a control signal that adjusts the amplitude based on the comparison.

Description

200828780 九、發明說明: 【發明所屬之技術領域】 涉及具有晶體振盪器模擬器的積 本發明涉及積體電路,更具體地說 體電路。 【先前技術】 ^諸如行動電話和其他手持設備之類的許多電子設備中需要精確的頻 ίίί 體振盈器來在這些設備中提供精確的頻率參考。然而, 存干缺陷,包括較大的體積、易碎並且成本較高。另 p之=丨_僅②的尺寸和成本與譜振頻率相關,所以隨着頻率增大,尺寸 本和钟㈣稍大。縣電子設個財销縮ί 、、曾易!!性和成本限制,使用晶體振盤器越成為問題。 “V體振盪器對晶體振盪器而言已是較差的選擇,且一 精確的頻率茶考,因為其振蘯頻率變動過大,尤其是隨着温度的^變。 【發明内容】 ㈣缝11模擬11碰,包括:第—温度感舶,哕 校正參數並卿 參數的頻^的^信二^導體^器’其產生具有基於校正 的溫㈣地調整一校正方^以產些輸入至其中 應校正電 5 200828780 々、、曰由⑭u ·· ·/ 、 土於測5式貝料對該預定温度特性直線和該預 定温度特性曲線中的至少一個的朽温度狩性置綠和該預 測試點時,該自適獻T位置進仃機。當測試資料包括三個温度 曲線的曲率中的至;生直線的斜率和預定温度特性 -次可編程記憶i 中的至少—個·置進行調整。該記憶體包括200828780 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to an integrated circuit, and more particularly to a bulk circuit. [Prior Art] ^ Many electronic devices, such as mobile phones and other handheld devices, require precise frequency oscillators to provide accurate frequency references in these devices. However, dry defects, including large volumes, are fragile and costly. The other p = 丨 _ only 2 size and cost are related to the spectral frequency, so as the frequency increases, the size and clock (four) are slightly larger. County Electronics has set up a financial sales contract, and has been!! Sex and cost constraints, the use of crystal vibrators has become a problem. "V-body oscillator is a poor choice for crystal oscillators, and a precise frequency tea test, because its vibration frequency changes too much, especially with temperature changes. [Summary of the invention] (4) Slit 11 simulation 11 touches, including: the first - temperature sense, the correction parameter and the parameter of the frequency of the ^ ^ two ^ conductor ^ 'the production of a correction based on the temperature (four) to adjust a correction square ^ to produce some input to which should be corrected Electric 5 200828780 々, 曰 by 14u · · · /, soil 5 test strips of the predetermined temperature characteristic line and the predetermined temperature characteristic curve of at least one of The adaptive T position is entered into the machine. When the test data includes the curvature of the three temperature curves; the slope of the growth line and the predetermined temperature characteristic - at least one of the sub-programmable memories i are adjusted. include

應該,包括:第-温度感應裝置,用於感 温度選擇校辟i巾的- 有基於校正參數的頻率的輸出 ^ 2體振盥衣置,用於產生具 入到其中的温度測試點,自伽:敕 、H正裝置,其基於一些輸 在其他特徵中,該方法 r;p:^ ° 步署用二 包括用於調整該第—温度的減裝置.並且生处 衣置^錢正參缝齡之彳_加絲置失絲力並且失症 料由單;固=:點=裝;=該第-温度感測裝置操作。當測試資 斜率和財温度=曲=曲置採^;温度特性直線的 測試資料由兩個温朗試少—個的位置進行調整。當 直線的斜率和預定温曲 ^該預定温度特性直線和該預定温度特性二^於測試資料 ^當測試資料由兩個溫度測試點組成時,該自適應位置,調 =性直線的斜率和預定溫度特性曲線的定溫度 基於測試資料對該預定、、曰庠胪 乂個進仃调整,並且 的位置進行調整。當測;;二括三』 生直線的斜率和預定溫置 調正亚嫩職細峨温度特性直線和峨溫度雜= 6 200828780 的至行調整。該館存裝置包括—次可編程 半導體振―產生具有基於校正參“半導體顧器,該 入到其中的_,跑於-些輸 包括利用加熱器有選擇地調ίί第導的,溫度。該方法 該加熱器失去能力。該加熱器回應該H显度數被儲存之後使 包括’當測試資料由單個溫度測ί點組1時,該方法進牛 進一步包括採用預定温产特由兩個温度職點組成時,該方法 至少-個;並且基於測;率和預定温度特性曲線的曲率中的 線中的至少—個的位行^<温度特性直線和該預定温度特性曲 中的至少-個===直:線,率和預定温度特性崎 定温度特性曲線中的:少一個二位^貧料2該預定温度特性直線和該預 ==r 二:=== 第—臟麵擬器包括: 第—溫度定址的校正1=1=存基於該 操作不相其中,該積體電路不包括與該晶體振盪器模擬器 輪入’該晶體振盪11模擬11進—步包括-選擇輸人,該選擇 進二勺=一域的頻率作為外部被動元件的函數。該晶體振盈器模擬器 乂匕一加熱器,該加熱器有選擇地調整該第一温度。該加熱器回應 200828780 該第-温度錢ϋ作。該加鮮是從包括電M加熱旨和電阻加熱器組 成的組中選出的。校正電路與記憶體通信並且產生校正參數。 -種積體電路,包括:產生參考頻率的微機電系統(MEMS 體聲波諧振器(FBAR)雜器電路;温度感絲,其缝該韻電路^ 度;記憶體,其儲存校正參數並且選擇校正參數巾的至少—個校正參數^ 為所感應的温度的函數;以及谢目稱做,其純參考健,該鎖相迴 路模組包括具有回饋環路參數的回饋環路並且基於所 來 一個校正參數有選擇地調整該回饋環路參數。 ^数中的至夕It should include: a temperature sensing device for sensing the temperature of the wiper - an output based on the frequency of the correction parameter ^ 2 body vibrating garment for generating the temperature test point into which Gamma: 敕, H positive device, which is based on some of the other features, the method r; p: ^ ° step 2 includes a means for adjusting the first temperature - and the device is placed缝 彳 彳 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ When the test slope and the financial temperature = 曲 = 曲置采^; the test data of the temperature characteristic line is adjusted by the position of two tempering trials. When the slope of the straight line and the predetermined temperature curve are the predetermined temperature characteristic line and the predetermined temperature characteristic are the test data. When the test data is composed of two temperature test points, the adaptive position, the slope of the adjusted straight line and the predetermined The fixed temperature of the temperature characteristic curve is adjusted based on the test data, and the position is adjusted. When measured;; two-three-three-slide straight line slope and the predetermined temperature adjustment, the adjustment of the temperature of the sub-native job, the linear characteristic and the 峨 temperature miscellaneous = 6 200828780 to the line adjustment. The library device includes a sub-programmable semiconductor oscillator-generated with a calibration-based "semiconductor device", the _ into which the _, the run-to-the-sequence includes the use of a heater to selectively adjust the temperature, the temperature. Method The heater is disabled. The heater returns to the H-significance number after being stored to include 'when the test data is measured by a single temperature, the method of entering the cattle further includes using the predetermined temperature production by two temperature positions. At the time of dot composition, the method is at least one; and based on the measurement rate and at least one of the lines in the curvature of the curvature of the predetermined temperature characteristic curve, at least one of the temperature characteristic line and the predetermined temperature characteristic curve === Straight: line, rate and predetermined temperature characteristics in the rugged temperature characteristic curve: one less two bits ^ poor material 2 the predetermined temperature characteristic straight line and the pre == r two: === first - dirty surface Including: the first - temperature addressing correction 1 = 1 = stored based on the operation is not in phase, the integrated circuit does not include the crystal oscillator simulator wheeled 'the crystal oscillation 11 simulation 11 steps - including - input , the choice to enter two scoop = the frequency of a domain a function of the external passive component. The crystal oscillator simulator is a heater that selectively adjusts the first temperature. The heater responds to the 200828780. The electric M heating is selected from the group consisting of electric resistance heaters. The correction circuit communicates with the memory and generates correction parameters. - The integrated circuit includes: a microelectromechanical system (MEMS bulk acoustic wave resonator (FBAR)) that generates a reference frequency. a noise circuit; a temperature sense wire, which is sewn to the rhyme circuit; the memory stores the correction parameters and selects at least one correction parameter of the correction parameter towel as a function of the sensed temperature; and Pure reference health, the phase locked loop module includes a feedback loop with feedback loop parameters and selectively adjusts the feedback loop parameters based on a corrected parameter.

一在其他特徵中,該鎖相迴路模組包括分數鎖相迴路模組,並且該回 數,括縮放因子的比例。該分數鎖相迴路模組包括:相位頻率探^ ^MEMS❹臟譜振㈣路通信並且触參考頻率;電荷栗 其與該她鮮探·模崎信;壓控紐器,其與該 哺 率;以及縮放模組,與該壓控振盪器和該相位頻 組通k,有選擇地將該輸出頻率除以第一和第二縮放因子 數恤少-個⑽財娜娜,二縮放因 且該回饋環路參數包括對縮放除數的調制 _ 、'★、 5 :rMs ^ fbar 愈該其與該她鮮探測賴組通信;·振蘯器,並 位生輸=率;縮放模組,其與該壓控振盈器 二權二ί 亚且有選擇地將該輸出頻率除以第一和第 數、,讲第’二及δ_Σ調制11,其基於所述校正參數中的至少-個校正來 周正弟一和弟二縮放因子之間對縮放模塊的調制。 / 並且第二縮放因子分别是等於Ν和N+1的除數, 盡-其產生具=====振器電路包括:半導體振 器,其接收該咖ittt自振働域,以及_s細从譜振 一種積體魏,其包括:產生參考鮮的_電纽(娜⑹或薄 8 200828780 膜體聲波諧振器(fbar)諧振器穿詈· 電路的温度;儲存裝置,其用於儲存=應裝置’其祕感應該積體 的至少-個校正參數作為所感應的温,並且用於選擇校正參數中 於接收參考信號,以用於提供且右二的㈡數,以及鎖相迴路裝置’其用 於所述校正_的至少—個校’並且用於基 環路參數包括縮放因子的比;數鎖相迴路模組,並且該回饋 置’其與_S或FBAR諧振^置數甬=迴路包括:相位頻率探測器裝 置,以用於與該相位頻率探測器奸‘貝率^荷«裝 和該相位頻率探測器裝置通信,以用於^ j控振Μ置 並且 率;電荷泵浦裝置,其用於與該相I率裝f信以接收參寺頻 其與該電棘職置聽喊讀;壓練盪裝置, 置==頻率探測器裝置通信,以有_=^ ==振= -城因子,以及δ_Σ調制裝置,用於基於所述校正夂除以弟一和弟 參數^整第-和第二_子之間縮放裝置‘;數中的至少一個校正 並且其中Ν是大於零的錄。該施Ms或Ν和㈣的除數, 紐裝置,其產生具有驅動頻麵$動自振城置包括:半導體 F臟諸練置,其用於接收_振器遽,以及職S或 體聲波諧振器(FBAR)諧振統(MEMS)或薄膜 擇校正參射的至少-做正參雜正參數;選 考信號的鎖相迴路’該鎖細路包括具有回‘=數钟如供接收參 基於所述拉纽㈣倾衫財獅‘數並且 9 200828780 在其他特徵中,該鎖相迴路包括分數鎖相迴路,並且該回饋環路參數 包括^放因子的比例。該方法包括提供與MEMS或FBAR諧振器通信並且 ,收參考頻率的相位頻率探測器;以及提供與該相位頻率探測器通信的電 荷泵浦。 ^在,他特,中,該方法包括產生一輸出頻率;且有選擇地將該輸出頻 率除以弟一和弟二縮放因子;以及基於所述校正參數中的至少一個校正參 數有選擇地對第一和第二縮放因子的比例進行調整。 、,在其他特徵中,該第一和第二縮放因子分别是等於N*N+1的除數, 亚且其中N是大於零的整數。該鎖相迴路包括δ-Σ分數鎖相迴路,並且該回 饋環路參數包括縮放除數的調制。In other features, the phase locked loop module includes a fractional phase locked loop module and the number of rounds, including the scaling factor. The fractional phase-locked loop module comprises: a phase frequency probe, a MEMS smear spectrum (four) road communication and a touch reference frequency; a charge pump and the her fresh probe, a pressure control, and a feed rate; a scaling module, and the voltage controlled oscillator and the phase frequency group k, selectively dividing the output frequency by the first and second scaling factors, the number of the shirts is less than one (10), and the second scaling factor and the feedback The loop parameters include the modulation of the scaling divisor _, '★, 5: rMs ^ fbar, which is the communication with the fresh detection group; the vibrator, the bitrate output rate; the scaling module, which is The voltage-controlled oscillator has a second power and selectively divides the output frequency by the first and third numbers, and the second and δ_Σ modulations 11 are based on at least one of the correction parameters. The modulation of the scaling module between Zhou Zhengdi and the second scaling factor. And the second scaling factor is a divisor equal to Ν and N+1, respectively, and the generating circuit has a ===== oscillator circuit comprising: a semiconductor oscillator receiving the coffee self-tapping region, and _s Finely synthesizing an integrator, which includes: producing a reference fresh _ electric (N (6) or thin 8 200828780 film bulk acoustic resonator (fbar) resonator through the temperature of the circuit; storage device for storage = should the device's secret sense the at least one correction parameter of the integrated body as the sensed temperature, and used to select the correction parameter in the received reference signal for providing and the second (two) number, and the phase-locked loop device 'It is used for at least one calibration of the correction_ and for the ratio of the base loop parameter including the scaling factor; the number phase-locked loop module, and the feedback is set to 'the _S or FBAR resonance ^ set 甬= loop includes: a phase frequency detector device for communicating with the phase frequency detector and the phase frequency detector device for use in controlling the rate and rate; charge pump a device for loading the signal with the phase I to receive the sacred frequency and the electricity Speaking and screaming; swaying device, setting == frequency detector device communication, with _=^ == vibration = - city factor, and δ_Σ modulation device for dividing the brother based on the correction And the other parameters are adjusted between at least one of the first and second sub-subsequences; at least one of the numbers is corrected and wherein Ν is greater than zero. The divisor of the Ms or Ν and (4), the neon device, which has a drive The frequency plane is set to be: the semiconductor F is dirty, and it is used for receiving the _ vibrator, and the at least S or the bulk acoustic resonator (FBAR) resonance system (MEMS) or the film is selected to correct the reflection. - Do positive mixed parameters; select the phase-locked loop of the signal 'The lock path includes having back '= several clocks for receiving the reference based on the pull (four) tilting lion's number and 9 200828780 among other features, The phase locked loop includes a fractional phase locked loop, and the feedback loop parameter includes a ratio of a scaling factor. The method includes providing a phase frequency detector in communication with the MEMS or FBAR resonator and receiving a reference frequency; and providing the phase Charge pump communication for frequency detector communication. ^ In, special, medium, The method includes generating an output frequency; and selectively dividing the output frequency by a first and second scaling factor; and selectively scaling the first and second scaling factors based on at least one of the correction parameters Adjusting, in other features, the first and second scaling factors are respectively a divisor equal to N*N+1, and wherein N is an integer greater than zero. The phase-locked loop includes a delta-sigma fractional lock A phase loop, and the feedback loop parameter includes a modulation of the scaling divisor.

在其他特徵中,該方法包括提供與MEMS *FBAR諧振器通信並且接 ί二ί頻率__率探湖;以及提供與該相位_探測騎信的電荷 2她。該方法包括產生—輸出頻率;有選擇地將該輸出頻率除以 亡=縮放因子;以及基於所述校正參數中的至少—個校正參數,調整第 縮放因子之間的調制。該第—和第二縮放因子分别是等於N和N+1 的除數’並且其中N是大於零的整數。 (FB^m電路,其包括微機電系統(_s)或薄膜體聲波諧振器 、m) #振㈣路,該諧振器電路產生參考鮮,並且包括:半導體据 ί ΐί生具有驅動頻率的错振器_說;以及-规·或FBAR, Ξ二错振器驅動信號。温度感應器,感應該積體電路的温^ H -轉%UE參數亚且選擇校正參數中的至少—個校正參數 感應温度的函數,其中該驅動頻率是基於校正參數的。 ”、、 針ίΐΪΐ徵中’―加熱器’其將溫度調整到魷温度;並且-失能電 ίΪΪϋίΐ齡至纖織賴加細失絲力。—自適應校正^ J選擇ίΓϋΞϊΓ自適應地調整校正方法以用於產生校 從由電晶體錄―數。該加熱器 ,其他特徵中當測試資料由單個温度測試點組成時,該 疋溫度特性直線的斜率和預定温度特性曲線的曲率中的 =ΐ該測試f料對該默溫度特性直線和該敢温度特性曲i中 的至>位置進行赃。當測試資糾兩個温度職馳成時,該自 200828780 性曲線中的至少-伽純、4 預U度祕直線和該預定温度特 時,該自適應校正模二預定=二2試紐由兩個温度測%組成 個温度測試點時,該自搞綠^贿I胃咐貝枓包括三 度特性曲線的曲率中的至度特性直線的斜率和預定温 温度特性直線和該;特:::::至===3=該;定 憶體包括-次可編程記憶體。 7個的位置進仃嶋。該記 (f_裝置!:生;=機盪::振器 ί _,置 儲存裝置儲存校ΐ參數並且,應該積體電路的溫度。 感應温度的t數,其中該驅;的一個校正參數以作為所 參數温度;並且失能裝置在校正 輸入到其巾的—失去,自適應校域置基於 法》選擇輪入裝正參數的校正方 裝置從由㈣“絲和電阻料祕。該加熱 裝置;=:特應校正 適應校正裝置採用預温度測試點組成時,該身 和G定、、^ 整’獻基於該戰f料_預定溫度特性直線 和/預疋4祕曲射的至少—個的位置進行調整。當職資^^^ 11 200828780 個;::=率 _:?二?,包括提供一微機電系統(MEMS)或薄膜體聲波諧振哭 路,魏喊p參考鮮,紅包括:半導體振盪器: 收^振器驅動信號。該方法包域應該積體電路的溫度;儲存校正失數接 ==二:正參數以作為所編的溫度的函數: =ί=整用於產生校正參數的校正方法。該方法包括選擇Si 組成的組ιϊΓ耕的函數。該加熱11從由電㈣加無和電阻加熱器 包括當峨龍由單個温度般驗成時,财法進一步 温度特性直線的斜率和預❹度特性曲線的曲率中的至少— =二rr賴整° #測試資料由兩個温制試點組成時,該方 岐度特性直線的斜率和預粒度特性曲線的曲率中 性曲線中的至少-定温度特性直線和該預定温度特 曲率温度特性直線的斜率和預定温度特性曲線的 和該預定、、日师性,亚且基於該測試龍對該預定温度特性直線 個温度測位f f于調整。當測試資料包括三 度特性曲線的曲率中的至少疋/胤度特性直線的斜率和預定温 温度特性直線和整;並且基於該測試資料對該預定 體包括-柯編程記推鱗巾的至少—侧位置進行調整。記憶 積體;擬器積體電路,包括:第-温度感應器,其感應該 、電路的弟-〉皿度;記憶體,其儲存校正參數並且基於該第—温度選擇 12 200828780 ^正參數中的至少-個校正參數;半導體振i器,其產生 生的頻率的輸出信號;加熱器,其將調整 定,二 白適ί地適應校正電路基於輸入到其中的-些溫度測試點, ;產生校正參數。選機人«該輸峰__ 熱器從由ϋΐΐΐ °該加熱器回應該第"'溫度感應器操作。該加 可編電阻加熱器組成的組中選出。該記憶體包括-次 缝器模擬器積體電路,包括:第-溫度感縣置,盆用於 :後使該加熱裝置失去能力 正參射的至少—個校轉數;半導體振盪裝ΐ 該第二參數的鮮的輸出錢,·加餘置,其用於調整 置後使該及失能裝置,其在校正參數被儲存至儲存裝 測試點, 該儲存 ί函數。該加熱裝置回應該第-裝置包括===加熱器和電阻加熱器組成的組中選出 第-温括丄’感,應積體電路的第一温度;储存校正參數;基於該 器,Ζίϊΐ有Sfn中的至少—個校正參數;提供一半導體振盪 能ί預疋温度,以及在校正參數被儲存至記憶體中後使該加熱器失去 以 該 應地ii:s:以:於輸入到其中的-些温度測試點’自適 作為外部被動元件的函數法包率 加熱:由電晶體加熱器和電阻加熱器組成的組中選出又口,'、、益 體咖:ί具ίΐ率;其包含-半導體趣,該半導 八賴羊的輸出^虎,感應該積體電路的第—温度;利用加 13 200828780 ========_號的頻 後使該加熱器失去能力。 杈多數被儲存至記憶體中 在其他特徵巾,财法包括__積 、胃 該積體電路的温度,·以及基於該温度 口 感 數,其中該半導體振盪器的輸出信號的 ;至^個校正參 該方法包括基於輸入到其中的一些行的一個校正參數。 產生校正參數。該方法句括、阳淫&山又“μ自適應地調整校正方法以 的函數。該加熱器蝴晶作為外部被動元件 ^ i ~和電阻加熱器組成的組中選出。 包括;用=特 個;並且基於該測料對性曲線的曲率中的至少一 的至少-個的位置進行調整二直線和該預定温度特性曲線中 性曲射社少-個驗ϋ彳溫度雛直肺_定温度特 時,該方法進—步包括對預定溫^性温;測試點組成 曲率中的至少—個進行調整和預定温度特性曲線的 和該預定温度特性曲射的至少^二料^該預定財特性直線 度特性曲線的曲率中=3一^括2定温度特性直線的斜率和預定温 温度特性躲和該縣;奴基_職龍對該預定 該積體電路的第-温度。記情體 二▲ ^ /皿度感應时,其感應 擇校正參針的至少-敏^/儲^正减並且級鱗—温度選 振幅的輸出信號,其中頻率是體振盪器,其產生具有頻率和 幅與預定飾她,將該振 -偏ΐίίΪί^Ϊί^Ϊ盪11包括譜振電路。該半導體振盪器包括 生偏置产ί 周正電路接收該控制信號並且基於該控制信號產 生偏置W ’該偏置域使諧振電路偏置來調整振幅。該偏置信號包括電 14 200828780 壓偏置信號。該偏置信號包括電流偏置信號 ⑽電路;以及與該LC電路通信的ί電感-電容 件的ii他鶴怖綱物卜部被動元 從由電咸-雷玄Qr、恭湯哭Μ 度感應操作。該半導體振盪器 出 電容(RC) _和環_器組成 模路’包括第-溫度感測裝置,以感應該 積體包路㈣-㈤度,齡裝置,_魏 温度選擇校正參數中的至少-個校正參數 ;基於該弟一 頻率和振幅的輸出信號,其中頻率是盟衣,以產生具有 以比較該振巾咖麵卜以及振幅調整裝置, 號。 驟基於該比較產生調整該振幅的控制信 導體半導體振盡器裝置包括用於讀振的譜振裝置。該半 —置包括偏置調整裝置,其用於接收 耦合電晶體。 Amc諧振裝置通信的交叉 伽ίϊ他概巾,選職置聰輸出信號鱗的解以作為外部被動元 士批四。加熱裝置調整該第一温度。失能裝置在校正灸皮 裝置回應該第—温度感測裝置操作。該半“ 環_容⑽紐裝置和 電路盪器模擬器積體電路的方法,包括:感應該積體 -個^ 參數;基於娜-温度選擇校正參數中的至少 的輪#,供半導體振盪11,該半導體振I器產生具有頻率和振幅 以, 以校正參數為基礎;_振幅與預定振幅相比較; 土於該比較產生調整該振幅的控制信號。 信!卢,該半導體振盪11包括雜電路。該方法包括基於控制 私號’該偏置信號使諧振電路偏絲機振幅。該偏置信號 15 200828780 包括電壓偏置信號。該偏置錄包括電流偏置信號。該方法還包括提供電 感-電容(LC)電路’·並且提供與LC電路通信的交叉輕合電晶體。該方法 包括選擇輸紐麵率_率崎為外部被動元件的函數。該絲包括提 2調整該温度的加熱H ;以及錢正錄被齡之後傾加熱器失去 能力。該方法包括回應該第-温度感應器操作該加熱器。該找還包括從 由,電容(LC) «H、•餘(RC)振懸和獅減器 組中選出該半導體振盪器。 該半導體振盪器可以包括包含金或銅之一的電感。 從下文提供轉細綱’本發_其他可義細將變得清楚。應合 理解,在翻本㈣具體辦,詳細的綱以於^ 例說明的目的,而不是想要限制本發明的範圍。 』惶用於牛 【實施方式】 Π) 生確頻率的輸出信號12的晶體減器模擬器 導體(CMOS) jT蓺在擬^1〇可以利用包括互補式金屬氧化層-半 ¥體(CMOS)工云在内的任何工藝被建構在單個半導體管芯上。In other features, the method includes providing communication with the MEMS*FBAR resonator and connecting the frequency to the lake; and providing the charge with the phase_detection rider 2 her. The method includes generating an output frequency; selectively dividing the output frequency by a dead = scaling factor; and adjusting a modulation between the first scaling factors based on at least one of the correction parameters. The first and second scaling factors are divisors equal to N and N+1, respectively, and wherein N is an integer greater than zero. (FB^m circuit, which includes a microelectromechanical system (_s) or a film bulk acoustic resonator, m) #vibration (four) way, the resonator circuit generates a reference fresh, and includes: the semiconductor according to ί 生 生 has a drive frequency of the vibration _ said; and - gauge / or FBAR, Ξ two damper drive signal. a temperature sensor that senses a temperature of the integrated circuit and selects a function of at least one of the correction parameters to sense a temperature, wherein the drive frequency is based on the correction parameter. "," 针 ΐΪΐ ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The method is used to generate a calibration slave. The heater, in other features, when the test data consists of a single temperature test point, the slope of the temperature characteristic straight line and the curvature of the predetermined temperature characteristic curve = ΐ The test f material 赃 默 默 默 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃 赃4 pre-U degree secret line and the predetermined temperature special time, the adaptive correction mode 2 predetermined = two 2 test button from two temperature measurement % constitutes a temperature test point, the self-inflicted green bribe I stomach 咐 枓 枓The slope of the characteristic curve of the curvature of the third-degree characteristic curve and the predetermined temperature-temperature characteristic line and the; the special::::: to ===3=the; the memory of the memory includes the -time programmable memory. The position of the entry. The record (f_ device!: raw; = machine:: ί _, the storage device stores the calibration parameters and should be the temperature of the integrated circuit. The t-number of the induced temperature, wherein a correction parameter of the drive is used as the parameter temperature; and the disabling device inputs the correction to the towel - Loss, adaptive school-based method based on the method of selecting the wheel to install the correct parameter of the correcting device from (4) "wire and resistance material secret. The heating device; =: special correction correction device using pre-temperature test points At the time, the body and G Ding, and the whole set are adjusted based on at least one of the predetermined temperature characteristic line and/or the pre-疋4 secret curve shot. When the job is ^^^ 11 200828780; := rate _:? 2?, including providing a micro-electromechanical system (MEMS) or film bulk acoustic resonance crying road, Wei shouting p reference fresh, red includes: semiconductor oscillator: receiving vibration drive signal. The temperature of the integrated circuit should be stored; the stored correction error == 2: The positive parameter is used as a function of the programmed temperature: = ί = the correction method used to generate the calibration parameters. The method includes selecting the group consisting of Si Function of the heating 11 from electricity (four) The sumless resistance heater includes at least the slope of the straight line of the temperature characteristic curve and the curvature of the pre-twist characteristic curve when the Snapdragon is tested by a single temperature. The test data consists of two temperatures. When the pilot composition is composed, the slope of the square characteristic curve and the curvature-neutral curve of the pre-granularity characteristic curve are at least a constant temperature characteristic straight line and the slope of the predetermined temperature characteristic curvature temperature characteristic line and the predetermined temperature characteristic curve Predetermined, Japanese, and based on the test dragon, the linear temperature measurement ff of the predetermined temperature characteristic is adjusted. When the test data includes the slope of the at least 疋/胤 characteristic line in the curvature of the third characteristic curve and the predetermined temperature The temperature characteristics are straight and complete; and based on the test data, the at least one side position of the predetermined body including the keel scale is adjusted. A memory integrated circuit comprising: a first temperature sensor that senses the circuit, a memory, a memory that stores calibration parameters and is based on the first temperature selection 12 200828780 ^ positive parameter At least one calibration parameter; a semiconductor oscillator that produces an output signal of a raw frequency; a heater that adjusts to a correction circuit based on the temperature test points input thereto; Correct the parameters. The selector «The peak __ heat exchanger from the ϋΐΐΐ ° the heater should return to the 'temperature sensor operation'. The additive is made up of a group of programmable resistor heaters. The memory comprises a -stitcher simulator integrated circuit, comprising: a first temperature sense county, the basin is used for: at least one number of revolutions of the heating device that is disabled to be positively reflected; the semiconductor oscillation device The fresh output of the second parameter, plus the remaining value, is used to adjust the post-disabled device and the disabling device is stored in the storage test point, the storage function. The heating device corresponds to the first device comprising: === heater and the electric resistance heater, the first temperature is selected, the first temperature of the integrated circuit is stored; the correction parameter is stored; based on the device, At least one calibration parameter in Sfn; providing a semiconductor oscillation energy 疋 pre-temperature, and causing the heater to lose the ii:s: after the correction parameter is stored in the memory: to input thereto - Some temperature test points 'self-adaptation as a function of the external passive component package rate heating: selected from the group consisting of a transistor heater and a resistance heater, ',, Yi body coffee: ΐ ΐ rate; it contains - The semiconductor is interesting, the output of the semi-guided sheep is ^, sensing the first temperature of the integrated circuit; using the frequency of adding 13 200828780 ========_ to disable the heater.杈 Most of the 杈 is stored in the memory in other characteristic tissues, the financial method includes __product, the temperature of the integrated circuit of the stomach, and the number of mouthfeel based on the temperature, wherein the output signal of the semiconductor oscillator; The method includes a correction parameter based on some of the rows input thereto. Generate calibration parameters. The method includes a function of adjusting the correction method adaptively. The heater crystal is selected as a group consisting of an external passive component ^ i ~ and a resistance heater. And adjusting at least one position of at least one of the curvatures of the pair of curves to determine the two straight lines and the predetermined temperature characteristic curve, the neutral curve is less than a test temperature, the lungs are straight and the lungs are fixed When the method further comprises at least a predetermined temperature temperature; at least one of the test point composition curvatures is adjusted and the predetermined temperature characteristic curve and the predetermined temperature characteristic curve are at least two of the predetermined financial characteristic straightnesses The curvature of the characteristic curve = 3 - 2 includes the slope of the linear characteristic line and the predetermined temperature and temperature characteristics to hide from the county; the slave base _ occupation dragon to the first temperature of the integrated circuit. When the dish is sensed, the sensor selects at least the sensitization of the accommodating pin and the output signal of the scaly-temperature-selected amplitude, wherein the frequency is a body oscillator, which produces a frequency and a width with a predetermined decoration. , the vibration-bias ίίΪί^Ϊί^ The oscillating circuit 11 includes a spectral oscillator circuit. The semiconductor oscillator includes a biasing circuit. The positive circuit receives the control signal and generates a bias based on the control signal. The bias domain biases the resonant circuit to adjust the amplitude. Including the power 14 200828780 pressure bias signal. The bias signal includes a current bias signal (10) circuit; and the inductance-capacitor component of the 395 communication with the LC circuit, the ii hehe corpus passive element from the electric salty - Lei Xuan Qr, Gong Tang cries the induction operation. The semiconductor oscillator output capacitor (RC) _ and the ring _ constituting the mode circuit 'including the first temperature sensing device to sense the integrated package (four) - (five) degrees, the age device , _Wei temperature selects at least one of the correction parameters; based on the output signal of the frequency and amplitude of the brother, wherein the frequency is the ensemble, to generate a number with the amplitude adjustment device. The control signal conductor semiconductor resonator device that produces the amplitude adjustment based on the comparison includes a spectral device for reading the vibration. The semiconductor device includes bias adjustment means for receiving the coupling transistor. The crossover of the vibrating device communicates with the wiper, and the solution of the output signal scale is selected as the external passive yuan. The heating device adjusts the first temperature. The disabling device adjusts the moxibustion device to the first temperature. Sensing device operation. The method of the semi-"ring_capacity (10) button device and the circuit breaker simulator integrated circuit includes: sensing the integrated body - a parameter; and selecting at least a wheel based on the nano-temperature selection correction parameter For semiconductor oscillation 11, the semiconductor oscillator produces frequency and amplitude based on the correction parameters; the amplitude is compared to a predetermined amplitude; the ground produces a control signal that adjusts the amplitude. Letter! Lu, the semiconductor oscillation 11 includes a circuit. The method includes causing the resonant circuit to have a resolver amplitude based on the control of the private number. The bias signal 15 200828780 includes a voltage bias signal. The offset record includes a current bias signal. The method also includes providing an inductive-capacitive (LC) circuit' and providing a cross-linking transistor in communication with the LC circuit. The method includes selecting a function of the input rate _ rate as an external passive component. The wire includes a heating H that adjusts the temperature; and the money is lost after the age of the tilting heater. The method includes operating the heater in response to the first temperature sensor. The search also includes selecting the semiconductor oscillator from the capacitance (LC) «H, • residual (RC) suspension and lion reducer groups. The semiconductor oscillator can include an inductor comprising one of gold or copper. It will be clear from the following to provide a summary of the subordinates. It should be understood that the details of the present invention are set forth in the Detailed Description, and are not intended to limit the scope of the present invention.惶Used for cattle [Embodiment] Π) Crystal output reducer conductor (CMOS) of the output signal 12 of the correct frequency 12 jT蓺 can be utilized in the case of a complementary metal oxide layer-half body (CMOS) Any process, such as Gong Yun, is built on a single semiconductor die.

曰曰:體減器模擬器1G可以包括產生輸出錢12的半導體紐哭Μ。 可以使用任何_的半導體振魅,包括^振㈣、r J 盥器。該半導體振盪n 12包括改變輸出信號 二y t 6可以是任何電的輸人’其影響輸出信號頻率的受控^ ^ : 振《的電源電壓和到LC振盛器的變容二極體的電壓輸入良•成 非揮發性記憶體18包括校正信息2〇,以控制作為温度 頻率。可以採用任何類型的非揮發性記憶體 定 ^虎 也^是;鮮。缺故技辑财触歧變的函數, 溫度感應器22可以感應半導體營芯的⑶洚 置於半導體缝器14 _的半導體料上度,器被 器22 ’包括熱敏電阻和紅外探測器。該温 感應 基線温度或者當前温度酿纽^ 22可叫配置為測量從 16 200828780 ^圖=用於在非揮發性記憶體18中儲存校正信息2〇的儲存方式 表和ΪΪΪ 是任何形式的資料庫,包括CAM、索引方案、查找 因子轉晶體振盈器模擬器1〇的恒定輸出信號頻率的校正 Γ3Γ糸列示例圖32。用於產生該曲線的資料可以以任何方i# 侍,包括器件級測試和批量模式測試。 '獲 矛件級職μ __糾進行職,確紐顧於半導 來在温度改變的情况下維雜定的輸出鮮的校正因子。在曰曰: The body reducer simulator 1G may include a semiconductor neon that produces output money 12. Any _ semiconductor stun can be used, including ^ (4), r J 盥. The semiconductor oscillation n 12 includes changing the output signal two yt 6 can be any electrical input 'which affects the control of the output signal frequency ^ ^ : the vibration supply voltage and the voltage input of the varactor diode to the LC oscillator The good non-volatile memory 18 includes correction information 2〇 to control as a temperature frequency. Any type of non-volatile memory can be used. The temperature sensor 22 senses the semiconductor core (3) 上 placed on the semiconductor material of the semiconductor splicer 14 _, and the keeper 22 includes a thermistor and an infrared detector. The temperature-sensing baseline temperature or current temperature can be configured to measure from 16 200828780 ^ Figure = storage mode table for storing correction information in non-volatile memory 18 and ΪΪΪ is any form of database The correction of the constant output signal frequency including the CAM, the indexing scheme, and the lookup factor to the crystal oscillator simulator 1〇 is shown in FIG. 32. The data used to generate this curve can be tested in any way, including device level testing and batch mode testing. 'Getting a spear-level job μ __ correcting the job, and surely taking care of the semi-conductor to adjust the fresh correction factor in the case of temperature change. in

4:導體=:!:3器:基線值確梅-預先較的頻率和在該 = 定的溫度,如最低操作溫度。該基線值可以直接測 2器件特性的測量值插人得知。也可以針對每個μ喻 定的itiit 以例如透過朗已知的電路_從預先確 ίΙΐίΐΓ 對值,或者儲存為比率、頻率因子,以從單個 基線值计异多個基線值。 半導體管芯的温度隨後以離散轉從大約最低操作温度增加至大約最 ^呆作温度。離散步驟的數目最好限於約6個温度級以減少測試成本,但 =以使膝他目雜散步驟。更好地,使用晶片加熱器來加熱半導體 =,但是可以採用用於改變半導體管怎温度的任何裝置。在每一離散步 -可以對半導體官芯的温度和用於將輸出維持在恒定頻率的校正 行測量。 該校正因子最好是一使用於基線值的比例,以獲得控制輸入的經調整 ▲ 正因子可以從任何基線值變動,例如1。更好地,針對每個温度步 =冲异單她正因子,該校正肝被顧辭導體振盪來將輸出信號維 、在多個預定頻率中的任_處。例如,假如校正因子1218被確定為對應於 c的温度改,,然後可以調整該半導體振盪器的控制輸入以作為校正因 二的函數,如藉由改變正比於校正因子的控制輸入。在另一種替換中,該 ^正因子可細於與期望輸出頻率相對應的基線值,來產生控制輸入被調 =到的經权正值。在另一種替換中,可以在每個温度步驟中測量與每一個 若干輸出頻率相對應的校正因子。 17 200828780 知用對晶體紐II槪旨1G的抵量財職來 過減少畔輕管制量的數目,從崎觸降域本 $中,對於來自同-批半導體管芯的晶體振盪器模擬器ι〇的 緣可以用於離情所有ϋ件。被測試的晶舰細績子华 ^個^可比例的器,總量,。例如,可以對單個晶體振盡器模擬器 中I且所传到的批里权正信息被儲存到該批器件中的每一個之 10 9 所,正^息的子_如是在基線温度處的輸錢率。刻件子 聽息可以被用來對儲存在每個器件中的批量校正信息修正。 第4圖顯不晶體振I器模擬器4〇㈣另一個方面。該晶體振 與11G驗,並且脉峨4G_52 _D的類似°對 應讀’除了曰曰體振盈器模擬器40也可以包括分離的或者組合的一個 個以上加熱器54、控制器56、和選擇輸入58。 〆 該加熱器54可以位於半導體振盤器Μ附近的半導體管芯上,以提 的if埶:以使用任何類型的加熱器54 ’包括電晶體加熱器和電阻 H該加”、、杰54可以回應來自温度感應器52的輸人而操作,以 半導體管芯的温度。該加熱器54可以使半導體管芯的温度增加至一程^, 該程度回絲-舞定校正因子溫度程度的射_個。另外,古執1 抗的封裝可以包圍該晶體振盪器模擬器40。 回…、阻 在-種情形中,該加熱器54可以提升該半導體管芯的温度至最大操作 f。在此,在器件測試或批量測試期間,僅需確定與該最大工作温度 對應的校正因子,從而降低成本。 該加熱器54也可峨_轉半導鮮糾温度提升至針對其確 正因子的若干縱温度級之_。第二温度感絲可喊應外部温度,例如又, 環境温度雜件温度。該加熱器Μ暖可以使铸齡芯的温度增加 接近巧定,的程度,同時在温度轉變期間利用從校正因子計算出的外推 值連績改變控制輸入。 該控織56可賤·如回應辣温絲絲來控制加熱器% 刼縱該校正信息50以取得與中間温度相對應的控糖入的值,從而添加^ 18 200828780 器、邏輯電路和 該控制器56可以是任觸型的實體,包括處理 盘^^輸入58可以用於從—定範圍的輸出頻率中選擇特定的輸出頻 Hi頻率被選擇可以作誕翻選擇輸人的外部組件的阻抗=函 可以直接用作半導體振盪11的—部分以選擇_^ ϋ 例如縱範關的阻抗選擇值可輯應於預定的輸娜率。$ w件可以為任何組件’但是最好是被動元件,例如,電阻器或^容^。 1〇2 晶體減器模擬器100的一方面,其具有例如兩個選擇管脚 102和104連接到兩個外部阻抗1〇6 * 1〇8。一個 =脚 或多個)外部組件。該晶體振盪接於 ΐίΐΣΓ 的外部組件探查或得到信息。所得到的信息可^ 接至二二4寸性的選擇值相對應的三個或更多個預定級别範圍。例如,連 =2電阻器的電阻最好被選擇為16個預定標準值之一。這電 ,中的母一個對應於16個輸出頻率級别中的一個。另外 _ 最:用:外部組件以降低成本和庫存。每個外部組件可以具有二:) =的標雛,每傭雛職概歡雜的=如使 =則可以選擇N個不同卿别。如果使用兩二 =7=義_,卿目嶋麵韻L。 如性的麵包括輸出頻率、頻率耐受性和基線校正因子。例 模擬器1G()可以具有連接到—個外部電阻器的單個選擇 iT6 從職_n⑻廳的16 _定輸出辭級對應於可能 人,最好是電阻器、電容器或者電阻器和電容器的組 二部電感、電阻、電容或者它們的組合的任何組件。 ,可以直接或者間接從任何能量源例如Vdd和地面或任 到管脚1〇2和1〇4。例如’該外部阻抗可以透過電 =電sa_路被連制Vdd,並且透魏容鍵翻選擇管脚 19 2008287804: Conductor =:!: 3: The baseline value is mei - the pre-compared frequency and the temperature at which = the minimum operating temperature. This baseline value can be directly determined by measuring the measured value of the device characteristics. It is also possible to assign a plurality of baseline values from a single baseline value, for example, to a value known by a well-known circuit, from a predetermined circuit, or as a ratio, a frequency factor. The temperature of the semiconductor die is then increased by discrete rotation from about the lowest operating temperature to about the optimum temperature. The number of discrete steps is preferably limited to about 6 temperature levels to reduce the cost of the test, but = to make the knees spur steps. More preferably, a wafer heater is used to heat the semiconductor =, but any means for varying the temperature of the semiconductor tube can be employed. At each discrete step - the temperature of the semiconductor core and the calibration line used to maintain the output at a constant frequency can be measured. Preferably, the correction factor is a ratio used for the baseline value to obtain an adjustment of the control input. ▲ The positive factor can be varied from any baseline value, such as one. More preferably, for each temperature step = the single positive factor, the corrected liver is oscillated by the Guru conductor to dimension the output signal at any of a plurality of predetermined frequencies. For example, if the correction factor 1218 is determined to be a temperature change corresponding to c, then the control input of the semiconductor oscillator can be adjusted as a function of the correction factor 2, such as by changing the control input proportional to the correction factor. In another alternative, the ^ positive factor may be finer than the baseline value corresponding to the desired output frequency to produce a positive positive value to which the control input is adjusted. In another alternative, a correction factor corresponding to each of several output frequencies can be measured in each temperature step. 17 200828780 Knowing how to reduce the amount of light control by the amount of 1G in the Crystal New II, from the bottom of the map, for the crystal oscillator simulator from the same-batch semiconductor die The edge of the cockroach can be used to detach all the pieces. The crystal ship that was tested was fine-grained, and the total amount was . For example, it is possible to store the weight information of the batch in the single crystal oscillator simulator and to the 10 9 of each batch of the device, such as at the baseline temperature. Losing rate. The in-form listener can be used to correct the batch correction information stored in each device. Figure 4 shows another aspect of the crystal oscillator I simulator (4). The crystal oscillator is 11G-tested, and the similar phase of the pulse 4G_52_D corresponds to reading 'except for the body shaker simulator 40, which may also include separate or combined one or more heaters 54, controller 56, and select input. 58. The heater 54 can be located on the semiconductor die near the semiconductor disk Μ to raise the if: to use any type of heater 54 'including the transistor heater and the resistor H. Responding to the input from the temperature sensor 52 to operate at the temperature of the semiconductor die. The heater 54 can increase the temperature of the semiconductor die to a range of ^, which is a degree of returning to the temperature of the correction factor. In addition, the package of the Gushen 1 can surround the crystal oscillator simulator 40. In the case where the heater 54 can raise the temperature of the semiconductor die to the maximum operation f. Here, During the device test or batch test, only the correction factor corresponding to the maximum operating temperature needs to be determined, thereby reducing the cost. The heater 54 can also raise the 峨_turn semi-conductive fresh-correction temperature to several longitudinal temperatures for its positive factor. The second temperature sense wire can be called external temperature, for example, the ambient temperature miscellaneous temperature. The warmer of the heater can increase the temperature of the cast core to a close degree, while changing the temperature. The control input is changed by the extrapolation value calculated from the correction factor. The control fabric 56 can control the heater % in response to the hot temperature wire. The correction information 50 is escaped to obtain the control corresponding to the intermediate temperature. The value of the sugar, thereby adding ^ 18 200828780 , the logic circuit and the controller 56 can be any type of entity, including the processing disk ^ 58 can be used to select a specific output frequency from the range of output frequencies The Hi frequency is selected to be the flip-flop selection. The impedance of the external component of the input can be directly used as the part of the semiconductor oscillation 11 to select _^ ϋ For example, the impedance selection value of the vertical range can be matched to the predetermined rate. The $w piece can be any component 'but preferably a passive component, such as a resistor or a ^^^^1, an aspect of the crystal reducer simulator 100 having, for example, two select pins 102 and 104 connected To two external impedances 1〇6 * 1〇8. One = foot or more) external components. The crystal oscillator is connected to the external component of ΐίΐΣΓ to probe or get information. The obtained information can be connected to the 2nd and 4th. Corresponding value Three or more predetermined level ranges. For example, the resistance of the connected = 2 resistor is preferably selected to be one of 16 predetermined standard values. The one of the electric, one of the 16 output frequency levels One. In addition _ Most: Use: external components to reduce costs and inventory. Each external component can have two:) = the standard, each commission is very mixed = if you make = you can choose N different Qing If you use two two = 7 = meaning _, the face of the face is L. The face of the face includes the output frequency, frequency tolerance and baseline correction factor. Example simulator 1G () can have connected to an external resistor The single choice iT6 slave _n (8) hall 16 _ fixed output level corresponds to the possible person, preferably a resistor, capacitor or a combination of resistors and capacitors, two components of inductance, resistance, capacitance or a combination thereof. It can be directly or indirectly from any energy source such as Vdd and ground or any of the pins 1〇2 and 1〇4. For example, 'the external impedance can be connected to Vdd through the electric=electric sa_ way, and the Weirong key flip selects the pin 19 200828780

、、該晶體振盪器模擬器100可以確定一預定選擇值,該預定選擇值相對應 ^連接至選擇管脚的阻抗的被測值。更好地,該阻抗可以被選擇為具有標 準值’例如’與具有10%耐受性的電阻器相對應的標稱電阻值(例如,470、 >···),以降低為件和庫存成本。為了考慮到而f受性測量和外部阻 ^耐,性’阻抗值的顧可以對應於單個選擇值。選擇值最好為數位值, 旦疋也可以為類比值。例如,從24⑻歐姆到3〇〇〇歐姆的被測電阻值可以 被與對應於2的數位值相關聯。而從遞歐姆到侧歐姆的被測電阻值 2以與對應於3的數位值相關聯。被測電阻包括由於外部阻抗和内部測量 耐受性而導致的變動。在每個選擇管脚處測量的阻抗被用於確定相 數位值的範圍可以包括3個或更多健位值,最好對於每個 為從㈣16的數錄。對餘每個聊管_數健可以組合 二田心己憶體地址。例如,具有三個選擇管脚,每個用於接口連接到被 杳=位值之-的阻抗值的器件可以描述1_個記健地址或者 的ί記址相對應儲存健的内容被用於設置器件的輸出或 抑:_值。另—個_性餅可以包括兩傾擇管脚,每個配置 定範圍的10個值内的數位值的外部阻抗。這些數位 個讀、舰址或麵隸,馳記赌地址或杳找表 值母個都可以包含用於設置晶體㈣器模擬器1〇〇的特性的資料。-找表 擬器第 12==^模上器 ^ &脚122’該适擇官脚122用於接口連接到外部阻浐1?4, 二/阻抗124用於選擇晶體振^模擬器! 二 在功能和範圍上與外部阻抗和1〇8類似。^糾雜心以 連接到選擇管脚I22的測量電路⑶測量作為 特性。例如,電流可輯提供到 並 & ^的電 流。可以使用用於測量被動元件的任m 電 和静態手段。示例性_*梓6 木4里1特性,包括動態 和數位類轉鋪(DACs) 器(ADCs) 電_可以產生具有與外部阻抗圍。該測量 以是數位或類比。同樣的輸出值最好代表—錄_卜部=值該= 20 200828780The crystal oscillator simulator 100 can determine a predetermined selection value corresponding to the measured value of the impedance of the selection pin. More preferably, the impedance can be selected to have a standard value 'for example' a nominal resistance value (eg, 470, > ...) corresponding to a resistor having 10% tolerance to reduce the Inventory costs. In order to take account of the f-measurement and external resistance, the impedance of the impedance value may correspond to a single selection value. The selection value is preferably a digit value, and the value can also be an analog value. For example, a measured resistance value from 24 (8) ohms to 3 ohms may be associated with a digital value corresponding to 2. The measured resistance value 2 from ohms to side ohms is associated with a digital value corresponding to 3. The measured resistance includes variations due to external impedance and internal measurement tolerance. The impedance measured at each of the selection pins is used to determine the range of phase value values may include 3 or more position values, preferably for each of the numbers from (4) 16. For each of the remaining chats, the number of health can be combined with the address of the second person. For example, a device having three select pins, each for interfacing to an impedance value of the value of the bit = can be described as 1_record address or ί address corresponding to the stored content is used Set the output of the device or the :_ value. Another _-slice can include two declining pins, each configured with an external impedance of a digit value within a range of 10 values. These digital read, ship or face, gambling address or 杳 lookup value can contain information for setting the characteristics of the crystal simulator. - Find the table 12==^ 模器 ^ & foot 122' The optional official foot 122 is used to connect the interface to the external resistor 1?4, the second / impedance 124 is used to select the crystal oscillator ^ simulator! Second, it is similar in function and range to external impedance and 1〇8. The correction circuit is measured as a characteristic by the measuring circuit (3) connected to the selection pin I22. For example, current can be supplied to the current of & ^. Any electrical and static means for measuring passive components can be used. An exemplary _*梓6 wood 4 in 1 feature, including dynamic and digital class transfer (DACs) (ADCs), can be generated with an external impedance envelope. The measurement is in the form of a digit or analog. The same output value is best represented - record _ Bu = value = 20 200828780

償由於包括過程、温度和電源在内的因素所導致的諸如外部阻抗值的耐受 性、互連相耗和測置電路耐受性之類的值變動。例如,從大於22歐姆變動 直到32歐姆的所有測得的外部阻抗值可以與數位輸出值“〇1〇〇,,相關。而從 大於32歐姆變動直到54歐姆的所有測得的外部阻抗值可以與數位輸出值 “0101”相關。考慮到值變動,實際的外部阻抗值是測得的外部阻抗值的子 集。例如’在上面的情形中,實際的外部阻抗值可能是從24歐姆到3〇歐 姆’以及從36歐姆到50歐姆。在每種情形中,可以將便宜的低精度電阻 裔送擇為具有在該範圍内的中間的值,例如,27歐姆和43歐姆。如此,可 以使用便宜的低精度組件來在一定範圍的高精度輸出中進行選擇。該選擇 值可以直接用於用來控制晶體振靈器模擬器12〇的器件特性的變量值。該 變量值也可以從該選擇值間接確定。 儲存電路127可以包括可以作為選擇值的函數而被選擇的變量值。該儲 f電路127可以是任何類獅儲存結構,包括内容定址記憶體、靜態和動 態記憶體、以及查找表。 對於測量電S 126 |生具有與外部阻抗值一對一對應關係的輸出值的 月形’數位值確定器128隨後可以將輸出值設置為與一定範圍的外部阻抗 值相對應的選擇值。 ^ 7A B顯示阻抗值組15〇和關聯的選擇值154之間的關係。阻抗值組 2 輸出值組152可以具有一對一對應關係,其中,數位輸出值組 MU換成她抗做15G巾的每俯目_的選擇值154。細從最小阻 二1 if阻抗值的阻抗值被區分成3個或更多個組,每組具有-個標稱 ίϊ:rf的標稱阻抗值被選擇為在標稱阻抗值之間存在間隔。在此,阻 稱值27輯和43 _具有16歐姆關隔。阻抗雜之間的間 隔t 幾何遞獅,然柯以使贿何數學_鍵立組之間的間 二Γ/,ϊ數、線性和指數。阻抗組之間的間隔可以基於這些組的任何Value changes such as tolerance to external impedance values, interconnect phase loss, and sensing circuit tolerance due to factors including process, temperature, and power supply. For example, all measured external impedance values from greater than 22 ohms up to 32 ohms can be correlated with the digital output value "〇1〇〇,, and all measured external impedance values from greater than 32 ohms up to 54 ohms can be Associated with the digital output value “0101.” Considering the value change, the actual external impedance value is a subset of the measured external impedance value. For example, in the above case, the actual external impedance value may be from 24 ohms to 3 〇 ohm ' and from 36 ohms to 50 ohms. In each case, inexpensive low-precision resistors can be chosen to have intermediate values in the range, for example, 27 ohms and 43 ohms. Thus, can be used Cheap low-precision components to choose from a range of high-precision outputs that can be used directly to control the value of the device used to control the device characteristics of the crystal oscillator simulator 12. The value of this variable can also be selected from this The value is determined indirectly. The storage circuit 127 can include a variable value that can be selected as a function of the selected value. The memory circuit 127 can be any lion-like storage structure, including Addressing memory, static and dynamic memory, and lookup table. The month-shaped 'digit value determiner 128 for measuring the output value having a one-to-one correspondence with the external impedance value can then set the output value to A selection value corresponding to a range of external impedance values. ^ 7A B shows the relationship between the impedance value group 15 〇 and the associated selection value 154. The impedance value group 2 output value group 152 may have a one-to-one correspondence, wherein The digital output value group MU is replaced by a selection value 154 for each of the 15G towels. The impedance value from the minimum resistance of the 1 if impedance value is divided into 3 or more groups, each group having - The nominal impedance value of rf: rf is chosen to have an interval between the nominal impedance values. Here, the resistance value of 27 and 43 _ has a 16 ohm interval. The interval between impedance impurities is Lion, Ran Ke to make bribes mathematics _ key between groups of two Γ /, ϊ, linear and exponential. The interval between impedance groups can be based on any of these groups

Zt. tt ? ΪΓ ' (-age value) ^ (mean value) . ^ 性,例^束曰對組的阻抗細和間隔的選擇的因素包括各種耐受 路的耐t抗的财受性、内部電壓和電流源的耐受性、以及測量電 路的•性。這些辦性例如因過程、温度和電源變動所致。 第7B圖顯示阻抗值範圍156和相_擇值158之間的關係。阻抗值的 21 200828780 範圍156與選擇值158具有直接對應關係。從最小阻抗值變動至最大阻抗 值的阻抗值被區分成3個或更多個組,每組具有_個標稱阻抗。每組的標 稱阻抗值被選擇具有在標稱阻抗值之間存在間隔。在此,阻抗值組的標^ 值27歐姆和43歐姆具有16歐姆的間隔。阻抗值範目156和關聯的選擇值 158之間的這種直接對應關係可由例如非線性類比數位轉換器(未示出)實 現。 貝 再次參考第6圖,地址產生器13〇可以確定對應於與連接到選擇管脚的 外部阻抗相關聯的數字輸出值的記憶體位置,記憶體位置可以任何方式被 分組,例如,針對單個選擇管脚的列表、針對兩個選擇管脚的查找 對三個選擇管脚的三次表。 _ 控制器132可以將晶體振盡器模擬器12_器件特性設置為變量值的函 :數。該變量值可由錄產生,從聊值確定,贼從鱼連接 到選擇管脚的外部阻抗相對應的記憶體位置的内容確定。 選擇管脚124也可以用於實現額外的功能,例如功率降低⑽, d=wn^、開機(powerenable)、模式選擇、復位和同步操作。在這方面中, 選擇管脚I24成為多功能選擇管脚用於配置晶體振盈器模擬器12 及實現額外的功能。 在一個方面中,連接到多功能選擇管脚124阻抗值的第一範圍可以用於 配置該晶體振盪器模擬器120,而額外功能的操作可由施加到多功能選擇管 # 脚122上的電壓或電流、或者該阻抗值第一範圍外的阻抗值控制。 & 第8圖顯示用於產生具有週期波形的輸出的振盡器組件2〇〇的一個方 面。振盡器組件200包括驅動鎖相迴路(PLL)2〇4的晶體振盪器模擬器2〇2。 ^晶體振盪器模擬器202在功能和結構上可以與上述晶體振盪器模擬器的 夕個方面類似。該振盪器組件2〇0可以包括任何類型的ριχ 2〇4,例如, 位PLL和類比pll。 多功能選擇管脚206和208可以用來為PLL 204選擇工作參數,例如, 除法器因子。該多功能選擇管脚2〇6和施射以用於晶體振蘯器模擬哭 =2的控制和操作,例如,輸出頻率選擇和接收麟校正的參考時脈。外; 電阻器210和212可以被連接到多功能選擇管脚2〇6和2〇8來選擇工作^ 22 200828780 率。該外部電阻器210和212的值的範圍對應於對不同工作頻率的選擇。 每個外部電阻器210和212都可以用於選擇16個預定工作頻率之一外部 電阻器210和鼠组合起來可以從256個工作頻率選擇。為了控制多個功 能,多功能選擇管脚206和208中的每個可以接收不同電壓範圍内的信號。 例如,一個多功能選擇管脚206可以連接到外部電阻器21〇,可以在外部恭 阻器210的兩端產生〇到2伏特範圍内的電壓來確定電阻,並且多功^ % 擇管脚2〇6還可以接收在2到3伏特範圍内工作的參考時脈信號。解^ 214可以檢測多功能選擇管脚206和208上的信號。 ° 第9圖顯示用於產生具有可變頻率的輸出信號的展頻振盈器綱。該层Zt. tt ? ΪΓ ' (-age value) ^ (mean value) . ^ Sex, case ^ 曰 曰 曰 曰 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗 阻抗Resistance to voltage and current sources, and the reliability of the measurement circuit. These practices are due to, for example, process, temperature, and power supply variations. Figure 7B shows the relationship between the impedance value range 156 and the phase value 158. The impedance value of 21 200828780 range 156 has a direct correspondence with the selected value 158. The impedance value that varies from the minimum impedance value to the maximum impedance value is divided into three or more groups, each group having _ nominal impedance. The nominal impedance value for each group is selected to have an interval between the nominal impedance values. Here, the values of the impedance value group of 27 ohms and 43 ohms have an interval of 16 ohms. This direct correspondence between the impedance value specification 156 and the associated selection value 158 can be achieved, for example, by a non-linear analog digital converter (not shown). Referring again to Figure 6, the address generator 13A can determine the memory locations corresponding to the digital output values associated with the external impedances connected to the select pins, which can be grouped in any manner, for example, for a single selection. A list of pins, a lookup for two select pins, and a cubic table of three select pins. The controller 132 can set the crystal oscillator simulator 12_ device characteristics as a function of the variable value: number. The value of the variable can be generated by recording, and the content of the memory location corresponding to the external impedance of the thief from the fish connection to the selection pin is determined from the chat value. Select pin 124 can also be used to implement additional functions such as power reduction (10), d=wn^, powerenable, mode selection, reset, and synchronization operations. In this aspect, select pin I24 becomes the multi-function select pin for configuring crystal oscillator simulator 12 and for additional functionality. In one aspect, a first range of impedance values connected to the multi-function select pin 124 can be used to configure the crystal oscillator simulator 120, while the operation of the additional function can be applied to the voltage on the multi-function select transistor #foot 122 or The current, or the impedance value outside the first range of the impedance value, is controlled. & Figure 8 shows an aspect of a sequencer assembly 2A for generating an output having a periodic waveform. The vibrator assembly 200 includes a crystal oscillator simulator 2〇2 that drives a phase locked loop (PLL) 2〇4. The crystal oscillator simulator 202 can be similar in function and structure to the evening aspect of the crystal oscillator simulator described above. The oscillator component 2〇0 can include any type of ριχ 2〇4, such as a bit PLL and an analog pll. Multi-function select pins 206 and 208 can be used to select operating parameters for PLL 204, such as a divider factor. The multi-function select pin 2〇6 and the emitter are used for the crystal oscillator to simulate the control and operation of crying = 2, for example, the output frequency selection and the reference clock for receiving the lining correction. Outside; resistors 210 and 212 can be connected to multi-function selection pins 2〇6 and 2〇8 to select the operation ^ 22 200828780 rate. The range of values of the external resistors 210 and 212 corresponds to the selection of different operating frequencies. Each of the external resistors 210 and 212 can be used to select one of the 16 predetermined operating frequencies. The external resistor 210 and the mouse can be combined to select from 256 operating frequencies. To control multiple functions, each of the multi-function select pins 206 and 208 can receive signals in different voltage ranges. For example, a multi-function selection pin 206 can be connected to the external resistor 21A, and a voltage within the range of 2 volts can be generated at both ends of the external circuit breaker 210 to determine the resistance, and the multi-function selects the pin 2 The 〇6 can also receive reference clock signals operating in the range of 2 to 3 volts. The 214 can detect the signals on the multi-function selection pins 206 and 208. ° Figure 9 shows the spread-spectrum oscillator for generating an output signal with a variable frequency. This layer

親盡器獅包括連制PLL304的晶體缝器模擬器3〇2。連接到振 盈器模擬器3G2的頻率控制器件可以動態控制晶體振魅模擬器搬的輸 出頻率。該頻率控制器件可以是包括變容二極體在内的任何科或裝置, 用於控制半導體振盪器的偏置電流源,並且控制被施 ^哭 驗電容器的控制輸入電壓。 卞夺腿L的 、第10圖顯示晶體振靈器模擬器的一個方面的操作。在框4〇 半導,振盪裔用於產生具有週期波形的輸出信號。繼續至框搬, & 振盪可以被校正以在預定的温度細内產生恒定的解。在—個方 正可以包括使半導體管芯的温度在預定範_變動,以及測量校正 ^:來維持恒定的輸出頻率。可以在半導體振魅附近測量管芯的温产。 該校正信息可以包括用於維持恒定輸出頻率的控制輸人值對管芯温产^談 校正信息可以被儲存在半導體管紅的轉發性記憶體中。在框4^ 了 可以透過探查外部組件來確定工作頻率。繼續到框概 1 =工作頻率的輸出信號。在框4〇8處,在半導體戀 =㈣温度。、_到框姻,可以加熱或冷却半導體管芯來將管芯的温度^ 痒到-個或多個預定温度級别。在框412處,可以將控制輸入作為管兒二曰工 度的函數進行控娜對由温度改變解致 的= 以直接被祕無齡的温度姉觸管芯温度。騎其他轉温产 以從所儲存的校正信息外推出控制輸人值。繼_框41 ^ 率可以被祕改_作為鮮控制钱祕數。 的頻 23 200828780 I二^® ^用於產生週期信號的低功率振盪器320的一個方面。低功 主動石夕振盈器324進行校正的晶體缝器模擬器奶。 器模擬器322通常處於關斷狀態以減少雜。在魷的間隔, ^曰^振盛器模擬器322被切換到開啟狀縣對主動雜魅324進行校 、以主動石夕振盪益324與晶體振盪器模擬器322相比消耗較少的功 魏盪器324連續工作而晶體振龜模擬器322僅間歇性地工作 紐器32G的總體祕。可以使用任何類型的主動矽振盡器, =^振贴和RC振絲。可以雜在本制書帽抽示$的本發明 的任何方面對主動;5夕振堡器324進行配置。 的顏m32ir^定主動石夕振盡器輸出和曰曰曰體振盤器模擬器輸出之間 查哭' 324 制☆ 328可以基於該頻率誤差產生控制信號來對主動石夕振 322°的曰^自行控制。控制器328還可以接收來自晶體振盪器模擬器 i t 信4可以包括下述温度,例如,半導度和環境 二田ΐ !3以包括用於主動石夕振盥器324的校正信息,該校正信 於晶體振盪器模擬器322的校正信息類似。該頻率誤差可以被用來 設ΐ控號的初始值,然後與主動魏魅校正信息組合的温度作自可 來在晶體振盈器模擬器322功率降低的期間更新控制信號。在二個 模擬器322的温度感應電路可以鋪連續被供電,從 =传y以向控制器328提供連續的温度信息。控制信號334可以是數位 n以疋類比。如果該控制信號是數位,則數位類比 可以將該控制信號轉換成類比。 ^AC)330 控制信號334,對主動石夕振盈器324的電源提供進 ===_器324的電壓和/或電流的提供可以 被控制。例如,整流15 332可以控制電源電壓的電壓電平。 曰骑t操Λ中,主動雜盪器324通常處於產生週期輸出信號的導通狀態。 通轉於晴雜。在糊斷狀齡,晶體滅器 杈擬„ 322的王孩者一部分可以被關機(p〇wer〇ff)以節省功 2二功树提供到晶體缝器模擬器322。然後利用所儲存的校正信息 上體振盟讀擬器322的半導體振盪器進行校正。該晶體振靈哭模 益322的輸出信號的頻率被與主動石夕振盪器似的輪出信號的頻率^行比 24 200828780 較,以確定主動石夕振盪H 324的頻率誤差。該控制信?兔334減該頻率誤 差而改變’導致來自電壓整流器332的電源電壓漂移,從而使主動矽振盪 器324的輸出頻率改變,來減少頻率誤差。 弟12圖痛示用於產生週期性信號的另一個低功率振盪器Mg的一個方 面。該低功率振盪器350包括與電荷泵浦振盪器通信的晶體哭 擬請。該晶雛細細松通讀於低雜狀財赠 在低功耗顧,該晶體紐器模㈣352的全部或者―部分可以被降低功 耗。在預定間隔,該晶體振盪器模擬器352被升高功率(p〇werup),並且 用來對電荷泵浦振盪器354進行校正。該預定間隔可以被確定為任何電路 參數的函數,所述電路參數例如為工作時間、半導體的温度改變、環境温 度改變、半導體的温度和電源電壓改變。 該電躲浦振盡器354可以包括電躲浦356、迴路渡波器现、麗控 振盈器(VCO) 360和相位檢測器362。該電荷泵浦缝器354在操作上與 傳統的電荷栗浦振靈器類似’除相位檢測器362的參考輸入接收來自晶體 振盪器模擬器352的參考時脈信號之外。 多工器364接收來自晶體缝器模擬器352和電荷系浦缝器说的輪 出錢。這些輸出信號之-被選擇並且經過多工器、364傳遞到鎖相迴路 3=。,鎖相迴路366產生輸出信號以作為來自晶體振盈器模擬器拉和電 何泵浦振盪器354的輸出信號的函數。 狀浦雜器354通常處於產生週期性輸出信號的導通 狀〜、。4日日體振盪态杈擬器352通常處於關斷狀 振盪器模擬器352的全部或者一部分可以被關機以降低功耗初定3^, 擬器352。輸,_儲存的校正信息對晶體振 ^拉擬„ 352的+¥體振靈器進行校正。該曰曰曰體振蘯器模擬器松 出^虎被與電荷泵浦振盈器354的輸出信號相比較,以確定 盡 1 VC_隨後被控制來減少相位誤差,從而使得i電 的輪出信號被校正到晶體振盪器模擬器352的輸出作 號。然後這些輸出信號之—可以被選擇並且被施加到ριχ施。》 現在參考第⑽圖,積體電路5⑽包括產生時脈信號的晶體振盡器模 25 200828780 ,器502。積體電路500中的一個或多個電路504接收時脈信號。該晶體振 盪斋核擬斋502可以如上結合圖M2所述的實現。該電路可以包括如 圖14所示的處理器512或其他電路。外部組件5〇6可以如圖13和15所示 可選地用來選擇晶體振盪器模擬器502的時脈頻率。 ’、The pro- lion includes the crystal splicer simulator 3〇2 of the PLL304. The frequency control device connected to the vibrator simulator 3G2 can dynamically control the output frequency of the crystal vibrating simulator. The frequency control device can be any device or device including a varactor diode for controlling a bias current source of the semiconductor oscillator and controlling the control input voltage of the cries capacitor. Figure 10 shows the operation of one aspect of the crystal oscillator simulator. At block 4 〇 semi-conducting, the oscillating person is used to generate an output signal with a periodic waveform. Continuing to the frame shift, the & oscillation can be corrected to produce a constant solution within a predetermined temperature. The method may include causing the temperature of the semiconductor die to vary at a predetermined norm, and measuring the correction to maintain a constant output frequency. The temperature of the die can be measured near the semiconductor vibrating. The correction information may include a control input value for maintaining a constant output frequency to the die temperature. The correction information may be stored in the transmissive memory of the semiconductor tube red. In block 4^, the operating frequency can be determined by probing external components. Continue to the frame outline 1 = output signal of the operating frequency. At block 4〇8, at the semiconductor love = (four) temperature. , _ to the frame, the semiconductor die can be heated or cooled to itch the temperature of the die to one or more predetermined temperature levels. At block 412, the control input can be manipulated as a function of the temperature of the tube to control the temperature of the die. Riding other thermostats to control the input value from the stored calibration information. Following the _ box 41 ^ rate can be secretly modified _ as a fresh control money secret number. Frequency 23 200828780 I II ^ ^ ^ One aspect of the low power oscillator 320 used to generate periodic signals. The low-power active Shishi Zhenying 324 performs a corrected crystal slitter simulator milk. The simulator 322 is typically in an off state to reduce noise. At the interval of the 鱿, the ^ 曰 振 振 振 simulator 322 is switched to the open county to the active miscellaneous 324, and the active shi yi yi 324 consumes less work than the crystal oscillator simulator 322. The 324 is continuously operated and the crystal vibrating simulator 322 only intermittently operates the overall secret of the button 32G. Any type of active 矽 vibrator, =^ vibrating and RC vibrating wire can be used. The active; 5 epoch 324 can be configured in any aspect of the invention in which the book cap is shown. The color m32ir^ is determined to be between the active Shishi vibrator output and the body vibrator simulator output. 324 ☆ 328 can generate control signals based on the frequency error to the active Shi Xizhen 322° ^ Self control. The controller 328 can also receive from the crystal oscillator simulator. The signal 4 can include the following temperatures, for example, semi-conductivity and environmental conditions, to include correction information for the active arc oscillator 324, the correction The correction information believed to be similar to the crystal oscillator simulator 322. The frequency error can be used to set the initial value of the control number and then the temperature combined with the active distortion correction information can be updated to update the control signal during the decrease in power of the crystal oscillator simulator 322. The temperature sensing circuits of the two simulators 322 can be continuously powered, from y to provide continuous temperature information to the controller 328. Control signal 334 can be digital to n. If the control signal is digital, the digital analog can convert the control signal into an analogy. The ^AC) 330 control signal 334 provides for the supply of voltage and/or current to the power supply of the active Shihua vibrator 324. For example, the rectification 15 332 can control the voltage level of the supply voltage. In the 曰 ride, the active worm 324 is typically in a conducting state that produces a periodic output signal. Passed to the sunny. At the battered age, a portion of the king of the crystal killer can be turned off (p〇wer〇ff) to save the work 2 binary tree to the crystallizer simulator 322. Then use the stored correction The information is corrected by the semiconductor oscillator of the body vibrating reader 322. The frequency of the output signal of the crystal ringing mode 322 is compared with the frequency of the wheel signal of the active Shixi oscillator, which is 24 200828780. The frequency error of the active sway oscillation H 324 is determined. The control signal rabbit 334 subtracts the frequency error and changes 'resulting in a power supply voltage drift from the voltage rectifier 332, thereby changing the output frequency of the active 矽 oscillator 324 to reduce the frequency. Error 12. An aspect of another low power oscillator Mg for generating a periodic signal is included. The low power oscillator 350 includes a crystal crying request to communicate with the charge pump oscillator. In the low-power consumption, the whole or part of the crystal modulo (4) 352 can be reduced in power consumption. At a predetermined interval, the crystal oscillator simulator 352 is boosted (p〇wer Up) and used to correct the charge pump oscillator 354. The predetermined interval can be determined as a function of any circuit parameter such as operating time, temperature change of the semiconductor, ambient temperature change, temperature of the semiconductor The power supply voltage changer 354 can include an electric rush 356, a circuit pulsator, a VCO 360, and a phase detector 362. The charge pump 354 is operationally Similar to the conventional charge pump oscillator, the reference input of the phase detector 362 receives the reference clock signal from the crystal oscillator simulator 352. The multiplexer 364 receives the crystal stitcher simulator 352 and the charge system slit. The output of the output is selected and passed through the multiplexer 364 to the phase-locked loop 3=. The phase-locked loop 366 produces the output signal as a pull from the crystal oscillator simulator and The function of the output signal of the pump oscillator 354. The pulsator 354 is typically in a conducting state that produces a periodic output signal. The 4th day oscillating state simulator 352 is normally turned off. All or part of the oscillator simulator 352 can be turned off to reduce the power consumption initial setting, and the correction information stored in the _ 352 is corrected for the crystal oscillator. . The body vibrator simulator is released and compared with the output signal of the charge pump oscillator 354 to determine that the VC_ is subsequently controlled to reduce the phase error, thereby causing the wheel to exit. The signal is corrected to the output of the crystal oscillator simulator 352. These output signals can then be selected and applied to the ρι. Referring now to the figure (10), the integrated circuit 5 (10) includes a crystal resonator mode 25 200828780 which generates a clock signal, and a device 502. One or more of the circuits 504 in the integrated circuit 500 receive the clock signal. The crystal oscillation can be implemented as described above in connection with Figure M2. The circuit can include a processor 512 or other circuitry as shown in FIG. External component 5〇6 can optionally be used to select the clock frequency of crystal oscillator simulator 502 as shown in Figures 13 and 15. ’,

現在參考第16-18圖,積體電路518包括用於電路522_卜522-2、.、 和522-N (總稱為電路522)產生在一個或多個其他時脈頻率的時脈信號的 日守脈除法态520。該電路522可以以任何方式被彼此互連。對於1/χ、γ和 /或Υ/Χ調整,時脈除法器520將時脈除以一個整數(例如,X')和/或將時 脈信號乘以Υ。該時脈除法器52〇還可以使用一個或多個額外的比率和域 除數來產生用於其他電路522㈤不同時脈信號。時脈除法旨52〇如圖所示 輸出N_1個時脈信號到積體電路518中的個電路。 在第胃17圖中,這些電路之一包括處理器53〇。該處理器5兕可以替代 晶體振盪器模擬器502而被連接到時脈除法器52〇,和/或除晶體振盪哭模 擬器502之外也被連接到時脈除法器52〇。附加電路532-卜532_2和532_以 都與時脈除法器520通信。 f第18圖中,該晶體振盪器模擬器5〇2提供時脈信號,用於積體電路 518中,處理器so、圖形處理器爾〜記憶體⑷和/或一個或多個電路 還了以長1供日守脈除法态(未示出)。處理器%〇、圖形處理器、 憶體542和/或其他電路544可以以任何適當的方式被互連。w η 現在參考第19圖,積體電路_包括一個或多個電路602小6〇2_2、··、 口 602-Ν (總稱為電路6〇2)和低功率振盈器32〇,該低功率振遷器伽如 =合圖11所述操作。這些電路之一可以包括㈣處示出的處理器。還 供如上所述的時脈除法器(未示出)。 積體電路(1C) -般裝入封裝材料中。該封裝材料可以包括塑膠。Ic 以包括塾片,該塾片由結合線連制引線框的引線。該IC基底、結 的f個部分可以被裝人至娜中。在封裝1C時通常使用的封i 時門、、^可能隨時間而變。雜改變可能導致晶片振I器的振麵率隨 致:封ί中的這種改變可能是由於封裝材料的介電損耗的改變所 、衣的這種改變也可能是由於封裝材料在不同的潮濕程度中吸水所 26 200828780 導致。結果,缝材料可能關了可_的校正精度。 中。第被封裝在她^技術的封裝材料⑽ 損耗可能&門3 ’ ΐΐίΓ7()4包括塑膠材料時’塑膠材料的介電 能對校正精度有負面影響。如在此所使用的,Referring now to Figures 16-18, integrated circuit 518 includes clock signals for circuits 522_b 522-2, ., and 522-N (collectively referred to as circuit 522) that are generated at one or more other clock frequencies. The Japanese Guardian divides the 520. The circuits 522 can be interconnected to one another in any manner. For 1/χ, γ, and/or Υ/Χ adjustments, clock divider 520 divides the clock by an integer (e.g., X') and/or multiplies the clock signal by Υ. The clock divider 52A can also use one or more additional ratios and domain divisors to generate different clock signals for the other circuits 522(5). The clock division method 52 outputs a circuit of N_1 clock signals to the integrated circuit 518 as shown. In the stomach map 17, one of these circuits includes a processor 53A. The processor 5A can be coupled to the clock divider 52A instead of the crystal oscillator simulator 502, and/or connected to the clock divider 52A in addition to the crystal oscillation crying simulator 502. Additional circuitry 532-Bu 532_2 and 532_ are both in communication with clock divider 520. In Fig. 18, the crystal oscillator simulator 5〇2 provides a clock signal for use in the integrated circuit 518, the processor so, the graphics processor, the memory (4) and/or one or more circuits are also In addition to the length of 1 for the day and the pulse to divide the law (not shown). Processor %, graphics processor, memory 542, and/or other circuitry 544 may be interconnected in any suitable manner. w η Referring now to Fig. 19, the integrated circuit _ includes one or more circuits 602 small 6〇2_2, ··, port 602-Ν (collectively referred to as circuit 6〇2) and low power oscillator 32〇, which is low The power regenerator gamma = operation as shown in Figure 11. One of these circuits may include the processor shown at (d). A clock divider (not shown) as described above is also provided. The integrated circuit (1C) is generally packaged in the package material. The encapsulating material can include plastic. Ic includes a cymbal which is connected by a bonding wire to the lead of the lead frame. The IC substrate, the f-portions of the knot can be loaded into the middle. The gates, which are commonly used when packaging 1C, may change over time. Miscellaneous changes may cause the vibration rate of the wafer oscillator to follow: this change in the seal may be due to a change in the dielectric loss of the package material, and this change in the package may also be due to the different moisture in the package material. The degree of water absorption is caused by 26 200828780. As a result, the seam material may be off the correction accuracy. in. The encapsulation material (10) that is encapsulated in her technology is likely to have a negative effect on the accuracy of the correction when the door 3' ΐΐίΓ7()4 includes a plastic material. As used herein,

場重定化‘、、、疋因為在材料内的偶極試圖隨入射波的振盡(電) 士身時,該材料内的偶極的“分子摩擦”所致。例如,當在微 1 麫之;二箪:好與食物中的水份相關的偶極振動並且被加熱。例如某迪塑 且有ΐΐΐΐΐΐΐ對水份的吸收也可能對校正精度有不利的影響。因為水 裝材料中增多的水傾向於增大封裝材料的介電損 t在,他碰中’該封騎料也可以是低應力材料。高應力材料於 =田化可能例如由於改變通路長度而影響相鄰電路的電路特性。如在此 術語低應力指封裝材料趨向於穩定並且不會由於應力改變而改 電路的,性。在-些實現方式中,封裝材料的介電損耗因子(DLF) 在相關工作鮮處(例如,大於1GHZ)擔等於鐵峨Tefl吵 現在爹考第21圖,該圖顯示根據本發日月被封裝在具有低介電損耗的封 裝材料7M中的積體電路710,該積體電路71〇具有採用温度補償的晶片半 導體振盪器7H。該封裝材料m可岐具有低介電娜的塑膠封裝材料。 如在此所使肖的術。。低介電損耗”指在IC的相關操作頻率處介電損耗小 於等於Teflon材料。1C的操作頻率可以是大於1(5112和/或2 4GHz。封裝 材料 714 射以包括 Teflon® ’ Tefl_ p〇lyChl〇r〇TriFlu〇r〇Ethylene (PCTFE)、Teflon® Teflon®氯化乙烯丙烯共聚物(FEp)、全氟化合物 (PFA)、Tefzel®和乙烯和四氟乙烯的Tefl(m⑧共聚物(ΕτρΕ)、低介電損 耗塑膠、南品質玻璃、空氣和/或其他材料。可以設想具有小於等於Tefl〇n 的介電損耗雜何其他封裝材料。封裝材觸可以具有械較低的吸水性。 27 200828780 杏C地顯示第21圖的積體電路封裝的示例性 只現方式積體电路封衣718包括積體電路似,該積體電路乃4包括塾片 ϋ。 33的引線732由結合線734連接到該積體電路的塾片。可以 =識到,f誠電純杨上職具核度娜的 片哭 個部分:結合線734 *積體電路724被封裝在封裝材t J。 料736可以疋具有低介電損耗的塑膠雖。可以意識到,在前面或 本實補和/或其他實施财可以採麟如 ==晶封裝(Mp)之類的其他類型的封裝和/或任適合Field renormalization ‘, 、, 疋 Because the dipole in the material attempts to vibrate with the incident wave (electricity), the “molecular friction” of the dipole in the material. For example, when it is in the micro; 箪: the dipole vibration associated with the moisture in the food is heated and heated. For example, the absorption of water by a certain type of plastic may also adversely affect the accuracy of the correction. Because the increased water in the water-containing material tends to increase the dielectric loss of the encapsulating material, he may also be a low-stress material. High stress materials may affect the circuit characteristics of adjacent circuits, for example, by changing the length of the via. As used herein, the term low stress means that the encapsulating material tends to be stable and does not change the circuit due to stress changes. In some implementations, the dielectric loss factor (DLF) of the encapsulating material is equivalent to the shovel Tefl in the relevant work (eg, greater than 1 GHz). Figure 21 shows the The integrated circuit 710 is packaged in a package material 7M having a low dielectric loss, and the integrated circuit 71 has a wafer semiconductor oscillator 7H using temperature compensation. The encapsulating material m can be a plastic encapsulating material having a low dielectric nano. As shown here, Xiao's surgery. . Low dielectric loss means that the dielectric loss is less than or equal to the Teflon material at the relevant operating frequency of the IC. The operating frequency of 1C can be greater than 1 (5112 and / or 24 GHz. Package material 714 is shot to include Teflon® ' Tefl_ p〇lyChl 〇r〇TriFlu〇r〇Ethylene (PCTFE), Teflon® Teflon® chlorinated ethylene propylene copolymer (FEp), perfluorochemical (PFA), Tefzel® and Tefl (m8 copolymer (ΕτρΕ) of ethylene and tetrafluoroethylene) Low dielectric loss plastic, south quality glass, air and/or other materials. It is conceivable to have a dielectric loss of less than or equal to Tefl〇n, and other packaging materials. The package material can have a lower water absorption. 27 200828780 An exemplary C-shaped circuit package 718 of the integrated circuit package of Figure 21 includes an integrated circuit, and the integrated circuit 4 includes a chip ϋ. The lead 732 of the 33 is connected by a bonding wire 734. To the slab of the integrated circuit. Can be = know, f Cheng electric pure Yang on the job of the nuclear degree Na's piece crying part: the bond line 734 * integrated circuit 724 is packaged in the package material t J. Material 736 can塑胶Plastic with low dielectric loss, although Realize that other types of packages and/or any suitable products such as == crystal package (Mp) may be used in the front or in this implementation and/or other implementations.

補償翻,替換積體電路封裝™包括晶片温度 貝+ ¥體振U1。在本貫施例中,半導體振盪器加包括積體電路電 非常薄的環氧材料層™被結合到積體電路基底 該%讀制7料以具有低介f損耗。 750和碰電路基底74G被職在封裝材料中。在這婦形 介3耗亚不重要,這是因為電感器742和封裝材料76G之間的距The compensation turns over and replaces the integrated circuit package TM including the wafer temperature ** + ¥ body vibration U1. In the present embodiment, the semiconductor oscillator plus a layer of epoxy material TM comprising a very thin integrated circuit is bonded to the integrated circuit substrate. The material is read to have a low dielectric loss. The 750 and the touch circuit substrate 74G are employed in the packaging material. In this case, the consumption is not important because of the distance between the inductor 742 and the encapsulating material 76G.

St f封裝材料的介電損耗和/或其他特性的改變作為時間的 無,封裝材料可以是低介電損耗材料。儘管玻璃層被 =區i中ί電路上’但是_層也可以被限於與半導體振盪器緊鄰的 严24圖和第25圖’顯示根據本發明所示,包括晶片半導體振 ir。:、積體電路封裝。該實施例與上面結合圖23示出被描述的實施例 T以,。/、^而/玻璃層744定義一個空腔746。該空腔746與電感 器742相鄰, f,敎延伸過該電感器742。在電感器742和玻璃層w之間形成了 752。在除空腔746之外的區域中,薄環氧材料層750碱在玻璃 =44 ,體電路基底74G之間。玻璃層744可以被侧來定義該空腔, 並且被次在環氧材料中。該玻璃層可以相鄰地包括多個玻璃層,並且至少 一個層在其中形成有空腔。 ,、:t考第Μ圖’晶片半導體振盤器的電容器可基於如前所述的温度補 二。然而,可以意識到,存在獨立於調整半導體振盈器的電容器和/ 或电感益之外的調整震盪頻率的其他方式。 28 200828780 路5在tf/7圖,積體電路’包括具有温度補償輸入的分數鎖相迴 分數鎖相迴路咖包括接收如上操作的積體電路振堡哭832 836。相位頻率探測器836基於參考頻率和vco頻2 ϊϋί刀信號。該差分信號被輸出到電縣浦_。該電荷840 的輸出被輸人浙迴路濾波器844。該迴路 ^认倉 ,該彻產_與被 =的vco輸出。vco 846的輪出被反饋到縮放 ‘二 ===!叫則_職 :ί ™ ;---- 度信號,該温度信號用來定址儲存秘驗856中的校=^858。 職魏85G。所驗正料驗錢ϋ所使 用的除數Ν和Ν+1的比例進行調整。 仙現在/考第28圖’顯示包括溫度補償輸人的積體電路_.Σ分數 ^自目迴路858。所選校正信息、被用來調整Σ_δ調製器87〇的輸出。所|校正 。心可以對縮放電路850所使用的除數Ν和N+1之間的調制進行調整。 現在參料29 ®,流_ __聽職採馳正職且利用線性 和算絲產生校正倾的轉。控侧贿轉·。在㈣卿1'中, ^Ϊ多個温度處測量採樣校正點。在步驟9%中,線性曲線擬和算法被 “產生嫌點之間的其他温度闕曲線^在轉_巾,控制結束。 現在芩考第30圖’流程圖92〇顯示用於測量採樣校正點並且利用高階 法來產^校正㈣的步驟。第3G圖所示的步驟可以利用包括處 夕益和德體的计异機實現。控制開始於步驟奶。在步驟似中中制在 :個温度處測量採樣校正點。在步驟926中’高階曲線擬和算法被用工來產 生用於採樣點之間的其他溫度點的曲線。在步驟928中,控制結束。 現在參考第31A-31G圖’顯示本發明的各種示例性實現方式。現在參 者弟31A圖,本發明可以被實現在硬式磁碟機邱輝麵中。本發明可以 只現任何積體電路’例如,在第31A圖中被總地標作臟的信號處理電路 29 200828780 和/或控制電路之一或二者。在—此者 電路和/或控制電路臟和見方式中,耶0 1000中的信號處理 碼和/或加密、執行巧知^:电路(未示出)可以處理資料、執行編 磁性儲存親1嶋^皆=彳=^舰麵輸_料和/或從 ^ 1008 電話、媒體或MP3播放機ΐ之未不出),諸如個人數字助理、行動 可以被物鄉飾懈身㈣絲i。腦麵 (RAM)' 的電子資料儲存裝置。 〜_ )唯項°己怳體(ROM)和/或其他適當 動器月圖可3=_在數位多功能光碟_)驅 標作職的域處理碰電路,例如,在第31B W中被總地 1〇1〇的大容量次電路之一或二者’以及DVD驅動器 1012和/或苴他^路幻咖1010中的信號處理電路和/或控制電路 二:他電路(未不出)可以處理 舰1G16讀㈣資胸或鶴人総魏體ι= =ίί現謝,dvd麵嫩麟理和/或 二社’、=非揮祕方式儲存貧料的大容量資料齡裝置1G18通信。大容量 =料儲存裝置刪可以包括硬式磁碟機(娜)。獅可以具有如 的配置。HDD可以是包括一個或多個直徑小於約18,,的盤片的迷你 士。DVD 1010可以被連接到記憶體刪,例如,請^、r〇m 吩間心體(例如快閃記憶體)和,或其他適當的電子資料儲存裝置。、 現在參考第sic圖,本發明可啸實現在高晝質電視⑽τν)刪 :本發明可以實現任何積體電路,例如,在第批圖巾被總地標作職 ’遽處理電路和/或控制電路之_或二者,贼腦的無線區域網 路(WLAN)接π和/或大容量資_魏置。顧^漏接收有線或無線格 30 200828780 ί===用於顯示器1026的職¥輸出信號。在-歧 路(未不出)可以處理資料、執行編碼和/或加密、執夂3 和/或執行可能需要_何無類酬^^處理。π t式化貝料 HDTV 1〇2〇可以與以非揮發性方式儲存冑料的大容量資 裝置騰例如辦/或磁儲存裝置、The change in dielectric loss and/or other characteristics of the St f package material is not a matter of time, and the encapsulation material may be a low dielectric loss material. Although the glass layer is on the circuit \\ on the circuit i', the _ layer can also be limited to the close proximity to the semiconductor oscillator. Figure 24 and Figure 25 show the wafer semiconductor ir according to the present invention. :, integrated circuit package. This embodiment and the embodiment T described above are shown in conjunction with FIG. /, / / glass layer 744 defines a cavity 746. The cavity 746 is adjacent to the inductor 742, and f, 敎 extends through the inductor 742. A 752 is formed between the inductor 742 and the glass layer w. In areas other than the cavity 746, the thin layer of epoxy material 750 is between the glass = 44 and the bulk circuit substrate 74G. The glass layer 744 can be side defined to define the cavity and be secondarily in the epoxy material. The glass layer may adjacently comprise a plurality of glass layers, and at least one of the layers has a cavity formed therein. ,,: t test, the capacitor of the wafer semiconductor disk can be supplemented by the temperature as described above. However, it will be appreciated that there are other ways of adjusting the oscillation frequency independent of adjusting the capacitor and/or inductance of the semiconductor oscillator. 28 200828780 Road 5 is in the tf/7 diagram, and the integrated circuit 'includes a fractional lock phase with a temperature compensated input. The fractional phase lock loop includes the integrated circuit that receives the above operation. The phase frequency detector 836 is based on the reference frequency and the vco frequency 2 刀 刀 knife signal. The differential signal is output to the electric county _. The output of this charge 840 is input to the Zen loop filter 844. The loop ^ clerk, the _ _ with the vco output = being. The turn of vco 846 is fed back to the zoom ‘two ===! call _ job: ί TM ;---- degree signal, which is used to address the store in the secret 856 = ^ 858. Job Wei 85G. The ratio of the divisor and Ν+1 used by the money test is adjusted. Xian now / test 28th diagram ‘ shows the integrated circuit including temperature compensation input _. Σ score ^ self-loop 858. The selected correction information is used to adjust the output of the Σ_δ modulator 87〇. | Correction. The heart can adjust the modulation between the divisor N and N+1 used by the scaling circuit 850. Now with the reference of 29 ® , the flow _ __ listens to the position and uses the linear and the calculated wire to produce a corrected tilt. Controlled bribery. In (4) Qing 1', the sampling calibration point is measured at multiple temperatures. In step 9%, the linear curve fitting algorithm is "generated by the other temperature 阙 curve between the suspect points ^ in the turn, the control ends. Now refer to the 30th figure 'flowchart 92 〇 display for measuring the sampling correction point And the high-order method is used to produce the step of correcting (4). The step shown in Fig. 3G can be realized by using a differentiator including Xiyi and German. The control starts from the step milk. In the step like: at a temperature The sampled calibration point is measured. In step 926, the 'high order curve fitting algorithm is used to generate a curve for other temperature points between the sample points. In step 928, the control ends. Referring now to Figure 31A-31G' display Various exemplary implementations of the present invention. Referring now to Figure 31A, the present invention can be implemented in a hard disk drive. The present invention can be used only in any integrated circuit 'e.g., in Figure 31A. The landmark is a dirty signal processing circuit 29 200828780 and/or one or both of the control circuits. In this case, the circuit and/or the control circuit are dirty and see, the signal processing code and/or encryption, execution in the yoke 1000 Cleverly know ^: circuit ( Not shown) can process data, perform magnetic storage, pro- 嶋 ^ all = 彳 = ^ shipboard data and / or from ^ 1008 telephone, media or MP3 player, such as personal digital assistant The action can be decorated by the hometown (four) silk i. brain surface (RAM) ' electronic data storage device. ~ _) only ° 恍 恍 body (ROM) and / or other appropriate actuator monthly map can be 3 = _ A domain processing touch circuit in a digital versatile disc _), for example, one or both of the large-capacity sub-circuits that are collectively 〇1〇 in the 31B W and the DVD drive 1012 and/or 苴He ^ Road Magic Coffee 1010 signal processing circuit and / or control circuit 2: his circuit (not out) can handle the ship 1G16 read (four) chest or crane man Wei body ι = = ίί Thanks, dvd face tender The 1G18 communication of the large-capacity data age device that stores the poor materials in the non-smart way. The large capacity=material storage device can include the hard disk drive (Na). The lion can have the configuration as the HDD. It may be a mini-roller comprising one or more discs having a diameter of less than about 18. The DVD 1010 may be connected to a memory delete, for example Please ^, r〇m interpret (such as flash memory) and or other appropriate electronic data storage device. Now refer to the sic diagram, the present invention can be achieved in high-quality TV (10) τν) delete: this The invention can implement any integrated circuit, for example, in the first batch of the towel is used as the general landmark 'processing circuit and / or control circuit _ or both, the thief brain wireless local area network (WLAN) connected π and / or Large capacity _Wei set. Gu leaks receive wired or wireless grid 30 200828780 ί=== for the output of the display 1026 ¥ signal. In the ambiguity (not out) can process data, perform coding and / or encryption, Execution 3 and / or execution may require _ no class compensation ^ ^ processing. π t-style bedding HDTV 1〇2〇 can be used with large-capacity equipment that stores materials in a non-volatile manner, such as magnetic storage devices,

具有第31B圖所示的配置。hJd=是配包置括!個DVD可以 盤片的迷你娜。膽刪可峨連接到記====’的 =、低等待時間記憶體(例如快閃記憶體)和 = ^置。HDTV腦細姚_ 祕接晴9與的== 現在參考第31D圖,本發明實現車輛刪的控制系財的任 路’車輛控儀統的WLAN^和/狀容量倾贿裝置。在—㈣方 式中’本發明實現傳動控齡統1032,傳動控制系統1G32接收來二個赤 多個感應H的輸人’所述錢H例如是溫度感應器、壓力感應* 5 應器、氣流感應器和/或任何其他合適的感應器,並且/或者產個3^ 輸出信號’例如’引擎工作參數、發送工作參數和/或其他控制信號。 本發明也可峨實現在車輛刪的其健制純_巾。 1040可以類似地接絲自輸4應器職的信號和/或輸出控制^麥至卜 個或多個輸出裝置1G44。在-些實現方式中’控制祕购可以是^鎖死 刹車系統(ABS)、導航祕、遠距舰纽、車輛雜軌_、車道偏 離系統、自適應巡航控制系統、車輛娛樂系統(例如,立體聲音響、dvd、 CD等)的一部分。也可以設想其他實現方式。 傳動控織統觀可賴轉揮發性方續存㈣的大容量資料儲 裝置1046通信。大容量資料儲存裝置1046可以包括光和/或磁儲存裝置, 例如,硬式磁碟機HDD和/或DVD。至少一個hdd可以具有第31人圖所 示的配置,並且/或者至少一個DVD可以具有第31B圖所示的配置。^ 可以是包括一個或多個直徑小於約1.8”的盤片的迷你hdd。傳動控制系統 1032可以被連接到記憶體1047 ’例如,ram、ROM、低等待時間"記情體 31 200828780 (例如快閃記憶體)和/或其他適當的電子龍儲存裝置 1〇32還可以支持經由WLAN網路接0 1〇48與1必的連接。工H 1 出〇4)〇。還可以包括大容量資料儲存裝置1憶體和/或m顧接口 動考ί31E圖,本發日柯以被實現在可以包括通訊天線酿的行 Γ 發明可以實現任何積體電路,例如,在第31E圖中被她 地&作1052齡魏理電路和/输魏狀—或二者,行二 2接π和/或大容«縣置。在—些實财式 _ 包括麥克風觀、音頻輸出1G58 (例如,揚聲 電孔顯0 示器獅和/或輸入裝置驗(例如,鍵盤、點選裝置、^出 輸繼)。行動彻㈣巾的魏㈣物或^^和/ =其他電路(林出)可轉理_、執行編碼蝴加密 、 袼式化資料和/或執行其他行動電話功能。 丁 AtThere is a configuration shown in Fig. 31B. hJd= is a package included! A DVD can be a mini-pan of the disc. You can connect to =====', low latency memory (such as flash memory), and =^. HDTV brain fine Yao _ 秘 晴 9 9 = = = ==================================================================================== In the - (4) mode, the invention realizes the transmission age control system 1032, and the transmission control system 1G32 receives the input of two red multiple inductions H. The money H is, for example, a temperature sensor, a pressure sensing device, a gas flow, and an air flow. An inductor and/or any other suitable sensor, and/or a 3^ output signal 'eg' engine operating parameters, transmit operating parameters, and/or other control signals. The invention can also realize the health of the vehicle. The 1040 can similarly connect the signal and/or output control of the device to the one or more output devices 1G44. In some implementations, 'control secrets can be ^Blocking Brake System (ABS), navigation secrets, long-range ships, vehicle miscellaneous tracks _, lane departure systems, adaptive cruise control systems, vehicle entertainment systems (eg, Part of stereo, dvd, CD, etc.) Other implementations are also contemplated. The transmission control system can communicate with the large-capacity data storage device 1046 that transfers the volatile side (4). The mass data storage device 1046 can include optical and/or magnetic storage devices, such as a hard disk drive HDD and/or DVD. At least one hdd may have the configuration shown in the 31st figure, and/or at least one DVD may have the configuration shown in Fig. 31B. ^ may be a mini hdd comprising one or more discs having a diameter less than about 1.8". The transmission control system 1032 may be connected to the memory 1047 'eg, ram, ROM, low latency", quotation 31 200828780 (eg The flash memory) and/or other suitable electronic dragon storage devices 1 〇 32 can also support the connection of 0 1 〇 48 and 1 via the WLAN network. The work H 1 is 4) 〇. It can also include a large capacity. The data storage device 1 recalls the body and/or the m interface, and the present invention can be implemented in a circuit that can include a communication antenna. The invention can implement any integrated circuit, for example, by her in FIG. 31E. Ground & for 1052 inferior Wei Li circuit and / / Wei Wei - or both, line 2 2 connected π and / or large capacity « county. In the form of some real money _ including microphone view, audio output 1G58 (for example, The speaker hole shows 0 lion and / or input device test (for example, keyboard, point selection device, ^ output). Action (four) towel Wei (four) or ^ ^ and / = other circuits (forest out) It can be transferred _, perform code encryption, simplify data and / or perform other mobile phone functions. At

Jt動電話麵可以與以非揮發性方式儲存資料 =通信,大容量資料儲存裝置編例如是光和/或貝^^置 硬式磁碟機HDD和/或DVD。至少—個可以 隨 ^並且/或者至少-個DVD可以具有第31B圖卿的配置。 ^括-個或多個直徑小_ U”的盤片的迷你。行動電話觸 = 記髓1G66,例如,職、R〇M、低特時間記憶體(例如快閃纪 ^體)和/或其⑽當的電子將_裝置。行_話刪 j WLAN網路接口 1068與WLAN的連接。 叉符、、二甶 現在參考第31F圖,本發日月可以被實現在機上盒1〇8〇中。本發明可以 =任何積體電路,例如,在第31F圖中被總地標作麵 ^或控織狀-或二者,機以娜的儲 哭和/$盆Γ二二」頁仏5虎’所述顯不器1088例如是電視機和/或監視 機上盒1080的信號處理電路和/或控 機上盒1080可以與以非揮發性方式儲存資料的大容量資料储存裝置 32 200828780 腦通信。大容量資料儲存裝置1〇9〇可以包括光和/或磁儲存裝置,例如, 硬式磁碟機HDD和/或DVD。至少—個腿^可略謂3]a圖所示的配 置,並且/或者至少一個DVD可以具有第31B圖所示的配置。HDD可以是 包括-個或多個直徑小於約u,,的盤片的迷你。機上盒麵可以被連 接到記憶體1G94,例如,麵、R〇M、低等待時間記憶體(例如快閃記情 體)和/或其他適當的電子資料儲存裝置。機上盒1〇8〇射以支持經由 WLAN網路接口 1〇96與WLAN的連接。The Jt mobile phone surface can store data in a non-volatile manner = communication, and the large-capacity data storage device is, for example, a light and/or a hard disk drive HDD and/or DVD. At least one may be accompanied by ^ and / or at least - a DVD may have the configuration of the 31st. ^ Mini-single discs with one or more small diameter _U". Mobile phone touch = 1G66, for example, R, M, low-time memory (such as flash memory) and / or The (10) when the electronic device _ device. _ _ delete j WLAN network interface 1068 and WLAN connection. Fork, 甶, now refer to the 31F map, the current day and month can be implemented in the set-top box 1 〇 8本中。 The invention can be = any integrated circuit, for example, in the 31F picture is marked as a total surface or control texture - or both, machine to Na's cry and / / potted two two" page 仏The display device 1088 is, for example, a signal processing circuit of the television set and/or the monitor box 1080 and/or the control box 1080 can be stored with a large-capacity data storage device 32 that stores data in a non-volatile manner. Brain communication. The mass data storage device 1 may include optical and/or magnetic storage devices such as a hard disk drive HDD and/or DVD. At least one leg can be slightly configured as shown in Figure 3, and/or at least one DVD can have the configuration shown in Figure 31B. The HDD may be a mini that includes one or more discs having a diameter less than about u,. The onboard surface can be connected to a memory 1G94, such as a face, R〇M, low latency memory (e.g., flash memory), and/or other suitable electronic data storage device. The set-top box 1〇8 is launched to support the connection to the WLAN via the WLAN network interface 1〇96.

^在參考第31G圖,本發日月可以被實現在媒體播放機謂中。本發明 可以實現任何積體電路,例如’在第31G圖中被總地標作的信號處理 電路和/或控制之-或二者,舰赋機蘭的脱續 量資繼存裝置。在-些實财式中,媒體播放機議包括顯示^1〇7今 2諸如鍵盤、觸控板之類_户輸人謂。在_些實現方式中,媒體播 以採用圖形,用者介面(叫該⑽一般利用顯示器窗 5 /入1108只現菜單、下拉菜單、圖標和/或指點介面。媒體播放 音頻輸出,娜,揚聲器和/或音頻輸出插孔。媒體播 放機100的4號處理電路和/或控制電路蘭和/或其他電路(未 可 输觸和/或域、撕計m储柿行其他媒 媒體播放機1100可以與以非揮發性方式儲存資料的大容量資料儲縣 ^ 1110通信,所述資料例如是經壓縮音頻和/或視頻内容。在—些& :善=缩音頻文件括與刚格式或其他適當的經壓縮音頻和-/或視頻2 j谷的文件。大容量貧料儲存裝置可以包括光和/或磁 ;式磁=二和/或卿。至少一個卿可以具有第31A圖所示j的配 亚,/或者至^ -個DVD可以具有第31B圖所示的配置。麵 ΐΐϋ或ίΪ姻、_ W隨片的迷你咖。媒體播放機_可以 ΪΪ 114 ’例如,罐、R〇M、低特咖記_ (例如快閃 ΐΐΐ或其他適當的電子資料儲存裝置。媒體播放機_還可以支持 之外的其他實動^彳“社:^現方式 現在參考第32A-32D圖,顯示 種積體電路封褒,該積體電路封裝結 33 200828780 二。材料作為與砍晶片的一個或多個所選結構相鄰的層 二二b —或多個退火玻璃漿或環氧材料層的“島,,可以被製作在石夕晶 杯切曰=削則的夕個部分上。在第32A圖中,替換積體電路封裝1200包 括石夕曰日片1204。退火玻璃漿層或部分娜被 __或者—部分。i玻璃i層= ,降低應力㈣間的改變。退火玻璃漿層1施趨向於將砍晶片i綱的全 刀與”包屬性的變動隔離’所述介電屬性例如是鑄模材料1208 的介電損耗。 且女石H 1204可以包括上述半導體振盪器。退火玻璃漿層1206可以包括 3=^?敎溫度驗轉。雜倾鈥温度可崎於損壞石夕晶 璃聚層1206可以包括玻璃熔聚(glassfritPaste)。可以 應用玻璃漿層。可以利用以下方法和/或利用任何其他適 虽的方法來細玻璃漿層:網版_法、浸潰法、遮罩法。 料:L圖二’替換積體電路封裝1210包括被應用至玻璃漿或環氧材 特·或者紐1212。該料㈣層1212可吨括傳導 3可以=值t材^層1212可以被應㈣液體或者凝固體。傳導材料層 用勺°站1日¥魏漆。傳導材料層1212可以以任何適當的方式被應 llj 片1204浸潰聽含該料材料的諸如盤之類的容器中。傳 ¥材料層1212趨向於減少來自外部設備的電磁干擾。 用至,lt々第曰Ιϋ中’積體電路封裝1220包括退火玻璃漿層1206,該層被應 Η 一的所選部分。在第32D圖中,積體電路封裝1230包括退 火,璃水或魏材料部分和傳導材料層1212。該傳導材料層m2可 以覆蓋退火玻璃聚層薦,同時接觸或者不接财晶片12〇4。 現在參考第33A-33D ® ’顯示替換積體電路封裝。在第徽圖中,替 ,積體電賴裝1·包括敎玻雜層聰和料材料層咖,這些層 =為鄰近梦晶片12〇4的電路組件1242。在第33B圖中,替換積體電路曰 =250包括退火玻層·和傳導材料層1212,這些層定位為鄰近 石夕日日片1204的振盪器1252。 在第33C圖中’替換積體電路封裝126〇包括退火玻璃漿層⑽6和傳導 34 200828780 f料f 1212恭這些層定位為鄰近石夕晶片1204的電感器1262。電感器1262 可以是晶片電感n ’例如,職電感器。在第33D圖中,雜積體電路封 裝1270包括退火破璃漿層1206和傳導材料層m2,這些層定位為鄰近具 有電感器1274的振盪器電路1272。 、 退火玻璃漿層也趨向於減少可能發生的應力隨時間的改變。退火玻璃漿 晶㈣全部或者-部分齡電屬性賴細離,職介電屬性例如 疋鑄板材料的介電損耗。這在如上所述試圖利用温度進行校正時尤其有利。^ Referring to Figure 31G, this day and month can be implemented in the media player. The present invention can implement any integrated circuit, such as the signal processing circuit and/or control that is generally designated in Figure 31G, or both, and the continuation of the device. In some real-life styles, the media player includes the display of ^1〇7 today 2 such as keyboard, trackpad and the like. In some implementations, the media broadcast uses graphics, the user interface (called the (10) generally uses the display window 5 / into 1108 only menus, drop-down menus, icons and / or pointing interface. Media playback audio output, Na, speaker And/or an audio output jack. The No. 4 processing circuit of the media player 100 and/or the control circuit Lan and/or other circuits (not touchable and/or domain, tear meter m other perch media other media player 1100) It can communicate with a large-capacity data storage county 1110 that stores data in a non-volatile manner, such as compressed audio and/or video content. In some &: good = reduced audio files include just format or other Appropriate compressed audio and/or video 2j valley files. Large capacity lean storage devices may include light and / or magnetic; magnetic = two and / or Qing. At least one can have the same as shown in Figure 31A The match, / or to ^ - DVD can have the configuration shown in Figure 31B. Face or Ϊ 、, _ W with the mini-coffee. Media player _ can be ' 114 'for example, can, R 〇 M , low special coffee _ (such as flashing ΐΐΐ or other appropriate electricity Data storage device. Media player _ can also support other real-actions. "Society: ^ now mode now refer to Figure 32A-32D, showing the seed circuit circuit package, the integrated circuit package junction 33 200828780 II The material acts as an "island" adjacent to one or more selected structures of the chopped wafer, or a plurality of layers of annealed glass or epoxy material, which can be made in a stone cup. In the case of Fig. 32A, the replacement integrated circuit package 1200 includes a stone slab 1204. The annealed glass layer or portion is __ or - part. i glass i layer = , stress reduction (four) The change of the annealed glass paste layer 1 tends to isolate the full knife of the chopped wafer from the "variation of the package properties". The dielectric property is, for example, the dielectric loss of the mold material 1208. And the female stone H 1204 may include the above. The semiconductor oscillator. The annealed glass layer 1206 may include a temperature verification of 3 = ^ 敎 。 杂 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 损坏 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 Can use the following methods and / or Use any other suitable method to fine the glass layer: screen _ method, dipping method, mask method. Material: L Figure 2 'Replacement integrated circuit package 1210 includes applied to glass paste or epoxy material · Or New 1212. The material (4) layer 1212 can be accommodating conduction 3 can be = value t material layer 1212 can be (iv) liquid or solidified body. The conductive material layer is scooped with the scoring station for 1 day. The conductive material layer 1212 can be Any suitable means is to be immersed in a container, such as a disk, containing the material of the material, and the layer of material 1212 tends to reduce electromagnetic interference from external devices. Up to now, the integrated circuit package 1220 includes an annealed glass paste layer 1206 which is selected for a selected portion of the layer. In Fig. 32D, the integrated circuit package 1230 includes an anneal, a glass water or a material portion and a conductive material layer 1212. The conductive material layer m2 may cover the annealed glass polylayer while contacting or not dicing the wafer 12〇4. Refer to Section 33A-33D ® ' to display the replacement integrated circuit package now. In the map, the integrated body is included in the circuit, and the layers are the circuit components 1242 adjacent to the dream wafer 12〇4. In Fig. 33B, the replacement integrated circuit 曰 = 250 includes an annealed glass layer and a conductive material layer 1212 which are positioned adjacent to the oscillator 1252 of the Asahi Day 1204. In Fig. 33C, the replacement integrated circuit package 126 includes an annealed glass paste layer (10) 6 and a conductive layer. The layers are positioned adjacent to the inductor 1262 of the Shihua wafer 1204. Inductor 1262 can be a wafer inductor n', such as a vocational inductor. In Fig. 33D, the hybrid circuit package 1270 includes an annealed glass layer 1206 and a layer of conductive material m2 positioned adjacent to an oscillator circuit 1272 having an inductor 1274. The annealed glass paste layer also tends to reduce the change in stress that may occur over time. Annealed glass slabs (4) All or - part of the age electrical properties depend on fine, dielectric properties such as the dielectric loss of 疋 cast sheet material. This is especially advantageous when attempting to correct with temperature as described above.

現在 > 考第3仏-34〇目’顯示替換積體電路封裝,該替換積體電路封 =包括退火賴細域環紐料部分和切;社述部分巾產生空氣間 P,的玻璃或韻。在第34A_34B圖中,積體電路封裝丨雙和G如包括石夕 j 1綱退火玻璃漿部们规按照間隔的關係形成在石夕晶片」綱上。 J ft1306可以t上所述被形成。可以使用鑄模材料1308。可以執行 邛刀1306的後續工藝,例如拋光或其他步驟來提供平坦的外表面。 玻璃或矽層1310被AGP部分13〇6支撑 g =他黏性結合材料可以被用來將玻璃或· i3ig黏合到AGp部 和玻璃或石夕層1310在第風圖中的減器1320上 ===路1322上方形成空氣間隙1324。空氣間 障324&供了具有取低可此介電損耗的材料(空 曰 =盈科,_驗得__振,齡之,线被絲^^ 在第34C-34D圖中,積體電路封裝134 可以如上所述被形成。可以執行環氧材 蓺^ ⑽支撑在石夕晶片測上方。^面材^璃^層1綱觀 玻璃或铺131G黏合到環氧材料部分^、=生=合材料可以被用來將 34C 11 1320 34D t 空氣間隙1324。 他電路1322上方形成 現在參考第35A-35B圖,顯 示包括產生空氣間隙的玻璃或矽部分的替 35 200828780 麵體電路封裝。在第3SA圖中,積體電路封裝削包括限 刪的“c,,开她璃或石夕部分聰。該“c”形玻璃或石夕部分1382可=^、 ^到-起的多個部分。空氣間隙1384被定位為位於振絲132〇上方 第35B圖中’積體電路封裝1390也包括限定空氣間隙1384的 矽層1382。空氣間隙1384被定位為位於電路1322上方。 5 現在參考第36A-36C圖,顯示用於製造上述積體電路封裝的 體電路結構I4⑻包紗晶14〇4、多個__ AGp和 ^ 和議B(總稱為141G)、以及玻璃翁層譲。積體電路 被城多個部絲生產多個韻祕,额電路可以 如上所述被封裝在鑄模材料(未示出)中。 在第36Β圖中,矽晶片14〇4可以包括一個或多個結合墊片142〇。 14Μ-!和⑷4_2雜層刚的切割可以從在⑷4_3處對石夕晶片的切判偏 ,開來,以提供用於將結合線(未示出)附接到結合藝片购的餘隙Ί 第36C圖中,顯示在從積體電路結構1400分開後的積體電路145〇之一。 現在參考第37Α·37Β ®,顯示積體電路封裝145G包括⑪晶片,石夕晶片 ’、有間IW的退火玻璃鮮3/或環氧材料部分⑷〇,退火玻璃聚和/或環氧 部分H10塗覆有傳導材料層觸,。在第PA圖中,部分wi〇被浸潰到包 =導材料觸的容器難中,晶片刚可以沿一條或多條切割線1462 被男切,並且可以包括結合墊片146〇,如圖所示。 現在參考第38目,齡麟製造f 32A_32D圖的雜封裝的方法 1·的步驟。控綱始於步驟蘭。在步驟腦巾,玻璃漿層腿被應 用於石夕晶丨副的-個❹個表面和/或⑨晶#⑽的麵區域上。在步 驟1篇中’透過將石夕晶片胸矛口玻璃篥層麗放入爐子中使玻璃裝層⑽ 退火。爐子的温度可以被設定為足以使玻璃漿層12〇6溶化的温度。例如, 於預定期間_ 4GG°C的温度足以使玻雜漿退火而不損耗㈣片12〇4。 在步驟1规中,傳導材料層⑽被應帛至退火後的玻璃漿層薦。在步 驟1510中’石夕晶片12〇4的全部或者一部分被裝入諸如塑膠、在此所述的 其他材料之類的鑄模材料12〇8和/或其他適當的鑄模材料中 。在步驟1520 中,控制結束。 36 200828780 在前姐述每個實施例中,可以以其他晶片或者其他基底替 可以用環氧材料替換經退火的玻璃漿。 ^ 亚且 現在參考第39圖,顯示-個晶體振盪器模擬器積體 晶體振盪器模擬器1C 1550可以是孤立的積體電直)。 述電路^的蝴”4味着該龍電料包括除下 出的輸出電路和/或一般支持晶體缝器模擬器 = 桑Now > test No. 3仏-34〇' shows the replacement integrated circuit package, the replacement integrated circuit package = including the annealing of the fine-grained ring material part and the cut; the social part of the towel produces the air between the P, the glass or rhyme. In the 34A-34B diagram, the integrated circuit package 丨 bis and G are formed on the Shi Xi wafer according to the interval relationship between the anneal and the glass slabs. J ft 1306 can be formed as described above. Mold material 1308 can be used. Subsequent processes such as polishing or other steps of the file 1306 can be performed to provide a flat outer surface. The glass or ruthenium layer 1310 is supported by the AGP portion 13 〇 6 g = the viscous bonding material can be used to bond the glass or i3ig to the AGp portion and the glass or sap layer 1310 on the reducer 1320 in the first wind pattern = == An air gap 1324 is formed above the road 1322. Air barrier 324 & for materials with low dielectric loss (empty = Yingke, _ __ vibration, age, wire is ^^ in Figure 34C-34D, integrated circuit package 134 can be formed as described above. It can be performed on the epoxy material 蓺 ^ (10) supported on the Shi Xi wafer measurement. ^ Surface material ^ glass ^ layer 1 view glass or tile 131G bonded to the epoxy material part ^, = raw = combined The material can be used to place the 34C 11 1320 34D t air gap 1324. The other circuit 1322 is formed above with reference to Figures 35A-35B, showing the 35 200828780 planar circuit package including the glass or germanium portion that creates the air gap. In the 3SA In the figure, the integrated circuit package is cut to include the limited "c, open her glass or Shi Xi part Cong. The "c" shaped glass or Shixia part 1382 can be ^^, ^ to - part of the air. The gap 1384 is positioned above the vibrating wire 132A in Figure 35B. The integrated circuit package 1390 also includes a germanium layer 1382 defining an air gap 1384. The air gap 1384 is positioned above the circuit 1322. 5 Reference is now made to 36A-36C Figure shows the bulk circuit structure I used to manufacture the above integrated circuit package 4 (8) wrapped yarn crystal 14〇4, multiple __ AGp and ^ and B (collectively referred to as 141G), and glass layer 譲. The integrated circuit is produced by the city's multiple parts of the silk, the amount of circuit can be as described above It is encapsulated in a mold material (not shown). In Figure 36, the tantalum wafer 14〇4 may include one or more bond pads 142〇. The cuts of the 14Μ-! and (4)4_2 hybrid layers can be from (4)4_3 The slanting of the slab wafer is opened to provide a clearance for attaching the bonding wire (not shown) to the photographic film Ί 36C, which is shown after being separated from the integrated circuit structure 1400. One of the integrated circuits 145. Referring now to the 37th, 37th, the integrated circuit package 145G includes 11 wafers, a stone wafer, an IW annealed glass, or an epoxy material portion (4), annealed. The glass poly and/or epoxy portion H10 is coated with a layer of conductive material. In the PA diagram, a portion of the wi〇 is impregnated into the container of the package = conductive material, and the wafer can be cut along one or more strips. Line 1462 is cut by a male and may include a combination of spacers 146, as shown. Referring now to item 38, age The steps of the method 1 of manufacturing the mis-encapsulation of the f 32A_32D diagram. The control begins with the step blue. In the step brains, the glass paste layer legs are applied to the surface of the stone lining, and/or the 9 crystals. In the surface area of (10), in the first step, 'the glass layer (10) is annealed by placing the stone plaque in the furnace, and the temperature of the furnace can be set to be sufficient for the glass layer 12〇6. The temperature of the melting. For example, the temperature of _ 4 GG ° C for a predetermined period is sufficient to anneal the glass paste without loss of the (four) sheet 12 〇 4 . In the step 1 specification, the conductive material layer (10) is recommended to be laminated to the annealed glass paste layer. In step 1510, all or a portion of the stone wafer 12〇4 is loaded into a molding material 12〇8 and/or other suitable molding material such as plastic, other materials described herein. In step 1520, control ends. 36 200828780 In each of the foregoing embodiments, the annealed glass paste may be replaced with an epoxy material on other wafers or other substrates. ^ Yahe Now refer to Figure 39, showing a crystal oscillator simulator integrated crystal oscillator simulator 1C 1550 can be isolated integrated body straight). The circuit of the circuit ^4 tastes that the dragon material includes the output circuit and/or the general support crystallizer simulator = mulberry

湯…二他電路。透過提供該晶體振盛器模擬器以作為孤立電路,該晶體振 模擬器在不要求集成的情况下提供用於任何其他電路的參考頻 。。晶體振遺器模擬器ic⑽產生穩定的參考頻率,如以上和以下所述。 晶體振盪器模擬器1C 1550包括非揮發性記憶體1552,該非揮發性記憶 體I552儲存在此所述基於温度的校正資料。該半導體振盪器出4提供經 温度補償的參考頻率。該温度感應器1556感應積體電路1550的温度了並 且將感應出的温度輸出到非揮發性_)記憶體1552。該加熱器1558可以在 校正期間可選擇地被用來將IC 1550加熱至預定温度。可以設置失能電路 1560在校正後使該加熱器1558失去能力。例如,失能電路156〇可以為諸 如溶絲或防熔絲(anti-fuse)之類的一次使用電路。 在製造後於工廠的測試期間,加熱器1558可以用來將晶體振|器模擬 斋1C 1550的温度加熱到一個或多個期望的温度,例如在一般環境的操作溫 度。在該温度處收集資料之後,該加熱器1558可以用來將晶體振盪器模擬 益1C 1550的温度調整至一個或多個另外的温度以進一步測試和校正。 在完成測試之後,失能電路1560可以用來使加熱器1558失去能力。使 該加熱器1558失去能力可以在工廠中執行。該晶體振盪器模擬器IC 155〇 的最終使用者不可能具有適當的高精度參考頻率,因此可能將不能執行精 確的測試和校正。此外,在操作期間也不可能使用該加熱器1558,因為這 趨向於降低1C 1550的效率。可以意識到,儘管前面的描述與晶體振盪器模 擬器1C 1550相關,但是類似的方法可以用於在此所述的任何其他晶體振盪 器模擬器。 37 200828780 在步驟刪巾,具有加熱器的積體電路被 二後爾進到步驟16〇4。 後的校正測試期間在工廠中使用加熱器來將積在===製造 熱器失去能力。該方法在後,在步驟刪中使該加Soup... two of his circuits. By providing the crystal oscillator simulator as an isolated circuit, the crystal oscillator simulator provides a reference frequency for any other circuit without requiring integration. . The crystal oscillator simulator ic (10) produces a stable reference frequency as described above and below. The crystal oscillator simulator 1C 1550 includes a non-volatile memory 1552 that stores the temperature-based calibration data described herein. The semiconductor oscillator output 4 provides a temperature compensated reference frequency. The temperature sensor 1556 senses the temperature of the integrated circuit 1550 and outputs the sensed temperature to the non-volatile memory 1552. The heater 1558 can optionally be used to heat the IC 1550 to a predetermined temperature during calibration. The disabling circuit 1560 can be set to disable the heater 1558 after calibration. For example, the disabling circuit 156A can be a single use circuit such as a dissolved wire or an anti-fuse. During testing at the factory after manufacture, the heater 1558 can be used to heat the temperature of the crystal oscillator 1C 1550 to one or more desired temperatures, such as operating temperatures in a typical environment. After collecting data at this temperature, the heater 1558 can be used to adjust the temperature of the crystal oscillator analog 1C 1550 to one or more additional temperatures for further testing and calibration. The disabling circuit 1560 can be used to disable the heater 1558 after the test is completed. Disabling the heater 1558 can be performed in the factory. The end user of the crystal oscillator simulator IC 155〇 may not have the proper high-precision reference frequency and therefore may not be able to perform accurate testing and calibration. Moreover, it is also not possible to use the heater 1558 during operation as this tends to reduce the efficiency of the 1C 1550. It will be appreciated that although the foregoing description relates to crystal oscillator simulator 1C 1550, a similar method can be used with any of the other crystal oscillator simulators described herein. 37 200828780 In the step of deleting the towel, the integrated circuit with the heater is sent to step 16〇4. A heater is used in the factory during the subsequent calibration test to disable the build-up heater at ===. After the method is added, the step is deleted to make the addition

⑹括自適應校正電路 器刪(其巾以大於晴1)^2有二擇地校正晶舰盪器模擬 的非揮發性記憶體!632、半導體振盪器⑹4二:^如上= 乍 校正電路1638可以基於—些採樣測試點有選擇地使^^636 °。自適應 校正電路1638儲存與在校正期間二胜二:k應 法或者,該校正一包括基二=二\線 現在參考第42-43圖 们岡由〜〜『 頁示利用單個温度校正點的校正。在第 在利用早個温度校正·點進行校正期間執行的步驟1640。這些 3= t驟1642 ’然後前進到步驟—,在該步驟中-般的線性和「 或非線性温度__存_體中。僅是舉例,可以倾錄 亚且可以使賴職點來確定未知一截距。或者,可以齡 可以確定y截距。 干业且 在乂驟祕中,在製造之後,在-個温度下測試積體電路(例如僅在 室温和/或預期的環境工作温度下)。在步驟购中,校正電路利用單個測 忒點定位預定直線或其他曲線的y截距。該方法在步驟165〇中結束。 自適應校正電路1638可以允許輸入一個或多個温度值。自適應校正電 路1638可以有選擇地基於所輸入的採樣點數使所執行的曲線擬和的類型相 適應。例如,當輸入了一個值時,可以確定直線或曲線的y截距。當輸入 兩個值時,可以確定直線或曲線的y截距,並且/或者可以確定曲線^率、 曲率或其他特性。當輸入三個或更多個值時,可以確定直線或曲線的又截 距’並且可以更高精度地確定曲線的斜率、曲率或其他特性。 38 200828780 自適應校正電路1638可能尤J:右用 擬器的積體電路的温度穩定的^§程可能需^相、使f括晶體振盪器模 包括晶體振盪器模擬it的積體電路的溫声從間。換言之,將 個穩定狀態温射能需要若干天^度攸―個键狀態温度改變到另— 言之歌的總體成本極大。換 基於採樣闕數目自誠變雜 雜正電路咖 同的精度級别。 往衣以商可以利用相同的ic提供不 在第43圖中,頻率被示作温度的函 齋(6) Including the adaptive correction circuit breaker (the towel is larger than the clear 1) ^ 2 to selectively correct the non-volatile memory of the crystal oscillator simulation! 632, semiconductor oscillator (6) 4 2: ^ above = 乍 correction circuit 1638 You can selectively make ^^636 ° based on some sampling test points. The adaptive correction circuit 1638 stores two wins during the correction period: k, or the correction one includes the base two = two lines. Now refer to the 42-43 figure from the ~~" page using a single temperature correction point Correction. Step 1640 is performed during the correction using the earlier temperature correction point. These 3 = t steps 1642 'and then proceed to step - in this step - general linear and "or non-linear temperature __ stored in the body. Just for example, you can dump the sub and can make the Lai position to determine An intercept is unknown. Alternatively, the y-intercept can be determined by age. In the industry, after the manufacture, the integrated circuit is tested at a temperature (for example, only at room temperature and/or expected ambient operating temperature). In the step of purchase, the correction circuit uses a single measurement point to locate the y-intercept of the predetermined line or other curve. The method ends in step 165. The adaptive correction circuit 1638 may allow one or more temperature values to be input. The adaptive correction circuit 1638 can selectively adapt the type of curve to be performed based on the number of sample points input. For example, when a value is input, the y-intercept of the line or curve can be determined. For each value, you can determine the y-intercept of the line or curve, and/or you can determine the curve rate, curvature, or other characteristics. When you enter three or more values, you can determine the intercept of the line or curve' and The slope, curvature or other characteristics of the curve can be determined with higher precision. 38 200828780 The adaptive correction circuit 1638 may be particularly stable. The temperature of the integrated circuit of the right-handed circuit may be required to be phased. The oscillator mode includes the crystal oscillator to simulate the warm sound of the integrated circuit. In other words, it takes several days for a steady state temperature to be radiated, and the temperature of the key state is changed to another. Change the accuracy level based on the number of sampling 自 诚 变 正 正 正 正 。 。 。 。 。 。 。 。 。 往 往 往 往 往 往 往 往 往 往 往 往 往 往 往 往 往 往 往 往

和測試頻率1654的單個職點定位 ^ 包括戦温度1652 測試温度1652可由温度感應器1636測量他曲線(未示出)。 1654可由外部電路測量並被輸入到ic里盆被監控。測試頻率 考頻率。由於在該補巾僅使t^電f提供了高精度的參 利用該單個測試點自動定位預ϋ 6 校正電路1638 温度測試結果,絲或曲線的位置。如圖可見,對於其他 現在參考第㈣圖,其詳細 咖或更低的刪。 圖中,顯示在利用兩個温度測試點的校正^度的貝,=的校正。在第44 於步驟膽,然後過程前進到步驟脱4,在曰該^的/驟獅。控制開始 線和/或曲線可以可選地被儲存到積體由二,中’―般的温度特性直 後,在兩個温度測試點處對&中。在步驟1666中,在製造之 «... , 於兩個測試點調整絲或曲線的位置祕中,基 他特性。 也』以凋整直線的斜率或曲線的其 在第45圖中,曲線圖顯示作為溫度函數 利用兩個測試點(測試溫度^724、丨 ^/員辜。自適應杈正電路1638 定位桃蚊減或鱗祕。自^^^職解1674_1、1764-2) 知值的第三温度點之類的信息。例如,可^^也可以使用例如已 處交叉的4鱗。 咖鱗可叹總是在已知_率/温度 在弟46圖 現在參考第46.47圖,其顯示_三個錢多個點的校正 39 200828780 始於步驟And a single job location for test frequency 1654 ^ including 戦 temperature 1652 test temperature 1652 can be measured by temperature sensor 1636 (not shown). The 1654 can be measured by an external circuit and input to the ic basin for monitoring. Test frequency Test frequency. Since the wiper only provides a high-precision reference to the t-meter, the position of the wire or curve is automatically positioned using the single test point to automatically position the pre-ϋ 6 correction circuit 1638. As can be seen from the figure, for other reference now, refer to the figure (4), which is detailed or lower. In the figure, the correction of the correction, which is corrected by using two temperature test points, is shown. In the 44th step of the gall, then the process proceeds to the step off 4, in the ^ 的 / 狮 狮. The control start line and/or curve can optionally be stored until the temperature characteristic of the integrated body is normal, at the two temperature test points in & In step 1666, in the manufacturing «..., adjust the position of the wire or curve at the two test points, the basic characteristics. Also in the 45th figure, the slope of the straight line is shown in the graph, the graph shows the use of two test points as a function of temperature (test temperature ^724, 丨^/辜辜. Adaptive 杈正电路1638 locating the peaches Decrease or scale secret. Information from the ^^^ job solution 1674_1, 1764-2) The third temperature point of the value. For example, it is also possible to use, for example, 4 scales that have been crossed. The sigh of the coffee is always known at the rate _ rate / temperature in the 46th picture now refer to the figure 46.47, which shows the correction of _ three money multiple points 39 200828780 starting from the steps

1686 t^Z^T cl ,t „)和/或_加熱!I使温度穩定。在步驟議巾,基於三 個測試點調整直線或鱗的位置和其他·。該方法在轉169^中結y 置和數,增加’校正電路可執行對温度曲線的位 置和曲羊的更精確估十細,隨着採樣點數目的增加,IC成本趨於增大。 在第47圖中,曲線圖顯示作為温度的函數。1686 t^Z^T cl ,t „) and/or _heating!I stabilizes the temperature. In the step of the towel, adjust the position of the line or scale based on the three test points and other. The method is in the turn 169^ y Set the number and increase the 'correction circuit to perform a more accurate estimation of the position of the temperature curve and the curve of the sheep. As the number of sampling points increases, the IC cost tends to increase. In Figure 47, the graph shows As a function of temperature.

i iU .·.、1794_τ)雜和/或限定直線或曲線脱6。在該 不=中,自賴校正電路1638 _戦點定位已㈣錄或树 温度測試點限定直線或曲線。 飞』用 /現在參考帛48A圖,積體電路i包括具核度補償輸人和由微機電 糸統(MEMS)諧振器電路1732產生的參考鮮的分數鎖相迴路㈣。 MEMS諧振器電路1732包括MEMS諧振器1733,該娜譜振哭1733 是在積體電路中形成的機械諧振組件。 °° 該分數鎖相迴路1731包括接收從如以上和以下所述操作的mems諧振 器電路1732的參考頻率輸出的相位頻率探測器1736。該相位頻率探測器 1736基於MEMS諧振器電路1732產生的參考頻率和VC〇頻率之間的^显 產生差分信號。 /' 差分信號被輸出至電荷泵浦1740。該電荷泵浦174〇的輸出被輸入到可 選的迴路濾波器1744。該迴路濾波器1744的輸出被輸入至壓控振盘器 (VCO) 1746,該VCO 1746產生具有與被輸入到其中的電壓輸入相關的 頻率的VCO輸出。該VCO 1746的輸出被反饋到縮放電路175〇。該縮放電 路1750有選擇地將該VCO頻率除以N或N+1。儘管採用除數N ^ N+1$ 但是也可以採用其他值的除數。該縮放電路1750的輸出被反饋到相位頻率 探測器1736。 ' 温度感應^§ 1754在接近1C振盈裔1732的區域中測量積體電路1730的 200828780 温度。温度感應器1754輸出温度信號,該温度信號用來定址儲存在記憶體 1756中的校正信息1758。所選校正信息被用於調整縮放電路175〇。所選校 正信息對縮放電路1750所使用的除數N和N+1的比例進行調整。 現在麥考第48B圖,積體電路1830包括具有温度補償輸入的&:分數 鎖相迴路1831。該積體電路1830包括具有微機電系統(MEMS)諧振器 1833的MEMS諧振器電路1832。δ-Σ分數鎖相迴路1831包括接收產生參 考^率的應MS諧振器電路1832的輸入的相位頻率探測器1836。相位頻 率捸測器1836基於參考頻率和VCO頻率之間的差異產生差分信號。i iU .., 1794_τ) Miscellaneous and / or defined straight line or curve off 6. In this no =, the self-resolving circuit 1638 _ 戦 point positioning has a (four) recording or tree temperature test point to define a straight line or a curve. Fly / Now with reference to Figure 48A, the integrated circuit i includes a fractional phase-locked loop (4) with a nuclear offset compensation input and a reference generated by a microelectromechanical system (MEMS) resonator circuit 1732. The MEMS resonator circuit 1732 includes a MEMS resonator 1733, which is a mechanical resonance component formed in an integrated circuit. The fractional phase locked loop 1731 includes a phase frequency detector 1736 that receives a reference frequency output from a MEMS resonator circuit 1732 as described above and below. The phase frequency detector 1736 generates a differential signal based on the difference between the reference frequency generated by the MEMS resonator circuit 1732 and the VC〇 frequency. /' The differential signal is output to the charge pump 1740. The output of the charge pump 174A is input to an optional loop filter 1744. The output of the loop filter 1744 is input to a Voltage Controlled Disc (VCO) 1746 which produces a VCO output having a frequency associated with the voltage input input thereto. The output of the VCO 1746 is fed back to the scaling circuit 175A. The scaling circuit 1750 selectively divides the VCO frequency by N or N+1. Divisors of other values can be used, although the divisor N^N+1$ is used. The output of the scaling circuit 1750 is fed back to the phase frequency detector 1736. The temperature sensing ^ 1754 measures the 200828780 temperature of the integrated circuit 1730 in an area close to the 1C vibrating 1732. Temperature sensor 1754 outputs a temperature signal that is used to address correction information 1758 stored in memory 1756. The selected correction information is used to adjust the scaling circuit 175A. The selected correction information adjusts the ratio of the divisors N and N+1 used by the scaling circuit 1750. Referring now to McCaw 48B, integrated circuit 1830 includes &: fractional phase locked loop 1831 with temperature compensated input. The integrated circuit 1830 includes a MEMS resonator circuit 1832 having a microelectromechanical system (MEMS) resonator 1833. The delta-sigma fractional phase locked loop 1831 includes a phase frequency detector 1836 that receives the input of the MS resonator circuit 1832 that produces the reference rate. The phase frequency detector 1836 generates a differential signal based on the difference between the reference frequency and the VCO frequency.

差分#唬被輸出到電荷泵浦1840。該電荷泵浦184〇的輸出被輸入到可 選的迴路濾波器1844。該迴路濾波器1844的輸出被輸入到壓控振盪器 ' (VCO ) 1846 ’ VCO 1846產生具有與被輸入到其的電壓輸入相鼸的頻率的 co輸出。vco觸的輸出被反饋到縮放電路185〇縮 擇地將該彻頻猶錢或N+1。鮮制了除數N和日是 以採用其他值的除數。縮放電路的輸出被反饋到相位頻率探觀。 =度_龍54糧親魏卿的温度。該温賴魅.輸出 號,温度信號聽定址儲存在記憶體1856中的校正信息1858。所 Γϊΐϊ ^麟赃微€路185G。所職正信息對驗電路185〇所使 用的除數N和N+1的比例進行調整。 戶^選校正信息被用來調整Σ_δ調繼㈣的輸出嘯選校正信息可 縮放视刪所使關除數^Ν+1之間的期進行調整。 ΜΕίίί考第49圖,積體電路1900包括諸振器電路1902。該 雜器電路脆包括·MS諧振器19()〇該廳㈣ 他0電例如,輸轉路可咕括並行腿電^阻或其 器i動信號^ _咖胸可以用來產生驅動脑8譜振器1904的諧振 所^揮田t性記龍1912可以用來配置半導體振魅卿,並且可以如前 _的溫償。温麟應1咖可以麟錢積體電路 所感應^_^出4^2的4^料可以基於温度編_ …、1924可^用於在製造之後加熱積體電路 41 200828780 1900。失能電路1928可以用於在利用加熱器1924用於校正之後使該加熱 器1924失去能力。例如,NV記憶體1912可以是一次可編程(OTP)記憶 體,並且失能電路1928可以包括一次可斷開電路,例如熔絲或防熔絲。 現在參考第50A圖,顯示包括具有薄膜體聲波諧振器(FBAR)電路1876 的分數鎖相迴路1874的積體電路1872的功能框圖。在此適當地使用第48A 圖的杯號。FBAR電路1876包括FBAR 1878。FBAR 1878可以是利用體聲 波的薄膜裝置,體聲波在壓電材料層内部傳播。FBAR透過改變壓電材料的 厚度改變諧振頻率。FBAR電路1876可以用來產生參考頻率。如上在第48A 圖中所述地執行基於温度對分數鎖相迴路的補償。 現在麥考第通圖,其顯示包括具有薄膜體聲波諧振器(FBAR)電路 18=的&[分數鎖相迴路1882的積體電路1880的功能框圖。在此適當地使 用第48A ®和第48B _標號。FBAR電路1876包括阳从顧。fbar 電路I876可以用於產生參考頻率。如上在第備目中所述地執行基於温度 對δ-Σ分數鎖相迴路1882的補償。 現在參考第霞圖’㉘示示例性FBAR電路is%和pBAR 1878(?FBAR 電 =1876可以包括魅為與FBAR 1878 _的聲鏡(ae。論mirr〇r) 2,用於提供結構和基底職之間的聲隔離。fbar㈣可以包括諸如 二ZnO、PZT之類的屢電材料或任何其他壓電材料。fbar 1878還可以 和1890。聲鏡1892可以包括在電極1890 *基底1898之間 細充層1894和低聲阻抗層1896〇F職1878的譜振頻率可以 1898 ^ 其他FBAR結^僅出於不例目的顯示示例性观欣結構,然而也可以設想 的梦考: ^示根據現有技術㈤包括半導體振盪器電路2010 盪态電路2010包括與交又耦合電晶體2016通信的 合電電路2018偏置交叉輛合電晶體娜。交叉搞 置電:2018提二電路2014讀振來產生振靈輸出信號V°ut。電流偏 置私路2〇18 k供驅動交又輕合電晶體娜的偏置信號。 :考第 圖顯示作為時間函數的振幅漂移。隨着時間流逝,包 42 200828780 括LC儲能器電路遍的半導體振盪器電路細 幅包絡’例如,振幅包絡增大(未示 认向於,、有味移的振 收vout的其他電路帶來問題。也可以利用上述方法處理頻率漂移。“接 M,2020 〇 2〇2°ϋΐ=整模、组2021和具有振幅調整輸入的半導體紐器 敕模组2〇2αΓί,2〇2〇J以包括在此所述的任何半導體振盪器。振幅調 ㈣/半導體振盛器2022的輪出的振幅進行監控。以所監控的振 ίίί制ΓΓΓ歡2021對被輸出到半導體振盪器輸出的控制信號進 L = 歡2021可以將所監控的振幅無定的閾值進行The differential #唬 is output to the charge pump 1840. The output of the charge pump 184A is input to an optional loop filter 1844. The output of the loop filter 1844 is input to a voltage controlled oscillator ' (VCO) 1846 'VCO 1846 to generate a co output having a frequency that is opposite to the voltage input input thereto. The output of the vco touch is fed back to the scaling circuit 185 to squash the money or N+1. The divisor N and the day are freshly divisible to take other values. The output of the scaling circuit is fed back to the phase frequency lookup. = Degree _ Long 54 grain pro-Wei Qing's temperature. The temperature signal is output and the temperature signal is addressed to the correction information 1858 stored in the memory 1856. Γϊΐϊ 赃 赃 赃 赃 € 185 185G. The ratio of the divisors N and N+1 used by the verification circuit 185 is adjusted. The household selection correction information is used to adjust the output of the 啸 δ δ (4) output tuned correction information can be scaled to reduce the period between the closing and dividing numbers ^ Ν +1.第 ίίί, in Fig. 49, the integrated circuit 1900 includes vibrator circuits 1902. The noise circuit is fragile including · MS resonator 19 () 〇 the hall (four), he 0 electric, for example, the transmission path can include parallel leg electric resistance or its device i signal ^ _ can be used to generate the driving brain 8 The resonance of the spectral oscillator 1904 can be used to configure the semiconductor vibration and can be compensated as before. Wen Lin Ying 1 coffee can be Lin Qian integrated circuit The ^^^ 4^2 4^ material can be based on temperature _ ..., 1924 can be used to heat the integrated circuit after manufacturing 41 200828780 1900. The disabling circuit 1928 can be used to disable the heater 1924 after being utilized by the heater 1924 for calibration. For example, NV memory 1912 can be one time programmable (OTP) memory, and disable circuit 1928 can include a single breakable circuit, such as a fuse or anti-fuse. Referring now to Figure 50A, a functional block diagram of an integrated circuit 1872 including a fractional phase locked loop 1874 having a film bulk acoustic resonator (FBAR) circuit 1876 is shown. The cup number of Figure 48A is used here as appropriate. The FBAR circuit 1876 includes FBAR 1878. The FBAR 1878 may be a thin film device using bulk acoustic waves, and bulk acoustic waves propagate inside the piezoelectric material layer. FBAR changes the resonant frequency by changing the thickness of the piezoelectric material. The FBAR circuit 1876 can be used to generate a reference frequency. Compensation for the fractional phase-locked loop based on temperature is performed as described above in Figure 48A. The McCormick diagram now shows a functional block diagram comprising an integrated circuit 1880 having a film bulk acoustic resonator (FBAR) circuit 18 = & [fractional phase locked loop 1882]. The 48A ® and 48B _ labels are used here as appropriate. The FBAR circuit 1876 includes a male slave. The fbar circuit I876 can be used to generate a reference frequency. Compensation for the delta-sigma fractional phase locked loop 1882 based on temperature is performed as described above in the first item. Referring now to Figure 28, an exemplary FBAR circuit is% and pBAR 1878 (? FBAR power = 1876 may include an acoustic mirror with FBAR 1878 _ (ae. on mirr〇r) 2 for providing structure and substrate Acoustic isolation between jobs. fbar (4) may include an electrical or other piezoelectric material such as two ZnO, PZT. fbar 1878 may also be used with 1890. Acoustic mirror 1892 may include a fine charge between electrode 1890 * substrate 1898 The spectral frequency of the layer 1894 and the low acoustic impedance layer 1896〇F1878 can be 1898^ Other FBAR junctions ^ show the exemplary Guanxin structure only for the purposeless, but it is also conceivable dream test: ^ according to the prior art (five) The semiconductor oscillator circuit 2010 includes a power circuit 2018 that communicates with the AC-coupled transistor 2016 to bias the cross-connected transistor. The cross-over power: 2018, the second circuit, 2014, reads the vibration to generate the vibration output. Signal V°ut. Current biased private circuit 2〇18 k for driving and re-lighting the signal of the crystal nano. The test chart shows the amplitude drift as a function of time. Over time, package 42 200828780 includes LC Semiconductor oscillation of the energy storage circuit The fine envelope of the circuit 'for example, the amplitude envelope is increased (the other circuit that does not indicate direction, the tuned shift vout causes problems. The frequency drift can also be handled by the above method. "Connect M, 2020 〇 2 〇 2° ϋΐ = integer mode, group 2021 and semiconductor 敕 module with amplitude adjustment input 2 〇 2α Γ , 2 〇 2 〇 J to include any of the semiconductor oscillators described herein. Amplitude modulation (four) / semiconductor oscillator The amplitude of the rounding of the 2022 is monitored. The monitored signal output to the output of the semiconductor oscillator is input to the monitored signal by the monitored voltage 2021. The alarm amplitude can be set to an undetermined threshold.

於該她調整控制信號。控繼號我包括電韻置信號、Here she adjusts the control signal. Control the serial number, I include the signal,

二扁置域、被改變的阻抗值和/或任何其他控制信號。結果,可 或者防止振幅漂移。 U 現在參考第53Α圖,顯示示例性半導體振盪器胸。該半導體振盡器 =020包括谐振電路2〇23和可調整偏置模組2〇24。振幅調整獅搬1對嘈 振^路2023的V〇ut或其他參數進行監控,並且產生對可調整偏置模組搬4 的巧出進行調整的控制信號。可調整偏置模組2024的輸出使諧振電路期 的操作改變來調整半導體振盪器2022的振幅。 、,…現在參考第53B圖,顯示根據目前揭露的半導體振盪器電路2020。該 半&體振益态電路2020執行振幅校正,並且包括LC儲能電路2025和交叉 輕合電晶體2026。半導體振盪器電路2020包括振幅調整模組2021。半導 體振盪器電路2020包括可調整電流源2024-1,該可調整電流源2024-1向 父又輕合電晶體2026提供電流偏置信號。振幅調整模塊2021監控〜⑽並 且有選擇地調整控制信號。控制信號對可調整電流源20244輸出的偏置信 號進行調整。如此,依次調整了 V〇ut的振幅包絡。 振幅調整模組2034可以感應VQUt的振幅包絡,並且將該振幅包絡與閾 值化號Vth相比較。基於所比較的信號之間的差異,振幅調整模組可以透過 調整至可調整電流源2024-1的控制信號來調整V^t的振幅。 現在參考第54-56圖,顯示根據目前揭露的示例性半導體振盪器電路的 電路示意圖。在第54圖中,半導體振盪器電路包括電感L、電容C、第一 43 200828780 和第二電晶體T1和Τ2、可調整振幅模組2〇2卜 叉麵合電晶體2026,它們被示出為連接的。 1正_源2024-1和交 在第55圖中,顯示LC錯能電路的替換佈置 電容C被並聯在和Τ2 端子間 置。 電感L1和L2被設置,並且分别與電晶體T1和T2的=子=和^ 與電壓源vdd通信。第一和第二電容C1^r 弟鳊子通佗亚且 在使用中,電壓源Vdd向LC電路提供電壓,這導致L 六 叉耦合電晶體基於偏置信號機L的振幅包絡 ^Two flat fields, changed impedance values and/or any other control signals. As a result, amplitude drift can be prevented or prevented. U Referring now to Figure 53, an exemplary semiconductor oscillator chest is shown. The semiconductor resonator =020 includes a resonant circuit 2〇23 and an adjustable biasing module 2〇24. The amplitude adjustment lion moves a pair of 〇 ^ 路 2023 V 〇 ut or other parameters to monitor, and generates a control signal to adjust the adjustable offset module 4 smart. The output of the adjustable bias module 2024 changes the operation of the resonant circuit period to adjust the amplitude of the semiconductor oscillator 2022. Referring now to Figure 53B, a semiconductor oscillator circuit 2020 in accordance with the present disclosure is shown. The half & body vibration circuit 2020 performs amplitude correction and includes an LC tank circuit 2025 and a cross-link transistor 2026. The semiconductor oscillator circuit 2020 includes an amplitude adjustment module 2021. The semiconductor oscillator circuit 2020 includes an adjustable current source 2024-1 that provides a current bias signal to the parent and light transistor 2026. The amplitude adjustment module 2021 monitors ~(10) and selectively adjusts the control signals. The control signal adjusts the bias signal output by the adjustable current source 20244. In this way, the amplitude envelope of V〇ut is adjusted in turn. The amplitude adjustment module 2034 can sense the amplitude envelope of VQUt and compare the amplitude envelope to the threshold number Vth. Based on the difference between the compared signals, the amplitude adjustment module can adjust the amplitude of V^t by adjusting the control signal to the adjustable current source 2024-1. Referring now to Figures 54-56, there is shown a circuit schematic of an exemplary semiconductor oscillator circuit in accordance with the present disclosure. In Fig. 54, the semiconductor oscillator circuit includes an inductor L, a capacitor C, a first 43 200828780 and a second transistor T1 and Τ2, an adjustable amplitude module 2〇2, a forked face transistor 2026, which are shown For the connection. 1 positive_source 2024-1 and intersection In Fig. 55, an alternative arrangement of the LC fault circuit is shown. Capacitor C is placed in parallel with the Τ2 terminal. Inductors L1 and L2 are set and communicate with voltage source vdd, respectively, with === and ^ of transistors T1 and T2. The first and second capacitors C1^r are in turn and in use, the voltage source Vdd supplies a voltage to the LC circuit, which causes the L-hexa-coupled transistor to be based on the amplitude envelope of the bias signal L.

«,並且雜包絡細值包絡概較。振贼雜组可缝生差^出。 ΪΪίΪ=基於驗分信軸整至可調整钱賴㈣佩。控制信^ 現在參考第57圖’顯示具有温度和振幅補償的铸體振魅。換 可以將温度和振幅補償|且合到單個晶體振I器模擬器中。 杆^ 體振盪器驗幅補償和温度補償,從而提高了辩和振幅^的精度。、 、。當利用上述晶體振盪器模擬器實現的半導體振盪器包括一個或多 感裔時’ 4些電«最好包括具有低電子遷移特性的材料。例如,該材料 可以包括銅(Cu)或金(Au)e諸純⑽之類的材料趨向於電子遷移太 局。換言之,Cu和Μ與A1相比具有相對較低的電子遷移。cu和Au 低的電子遷移特性趨向於降低作為時間函數的頻率漂移。 在利用外部晶體振盪器來產生參考頻率的系統中,也可以用Μ來實現 電感^在這些系統中對在職器中使用的材料_«與在不使用外ΐ晶 酿盥益來產生參考頻率的諸如上述系統之類的晶體振I器模擬器系統相 比並不重要。換言之,這些系統中的外部晶體振盪器校正由於遷暮 致的頻率漂移。 —已描述了許多本發明的實施例。但是,將理解,在不脱離本發明的精神 和範圍的情况下,可以仙各種佩。因此,其他實關也摘 皇 利範圍的範圍内。 44 200828780 【圖式簡單說明】 $ 1圖顯示晶體振盪器模擬器的一個方面的框圖; 第2圖顯示温度和校正因子之間關係的表; 第3圖顯示温度和校正因子之間關係的圖; $4圖顯示晶體振盪器模擬器的一個方面的框圖; =接到外雜抗的晶體振盪器模擬器的—個方面的二維視圖; ΐ 7Α ϋ_外部阻抗的晶體振魅模擬器的—個方面的詳細框圖; 圖和弟7B w係為外部阻抗值和數位值之間關係的圖; 圖圖係為用於產生具有週期性波形的輸出的振盪器組件的—個方面的框 =9圖係為展頻產生器的一個方面的框圖; ,10圖係為用於模擬晶體振盪器的操作流程圖; 第11圖係為低功率振盡器的一個方面的框圖; ,12圖係為低功率振盪器的另一個方面的框圖; 個電路和產生麟騎—贼乡織路的時脈信 就的曰曰體振盟益杈擬器的積體電路的功能框圖; 跑嶋4辦物雜麵器模擬 mm包々t處理器和產生用於該處理器的時脈信餘且採用了用於設 黛二二二植件的晶體紐器模擬器的積體電路的功能框圖; 為;:個積體電路的功能框圖,該積體電路包括-個或多個電路、 曰器日;振蠢拉挺益和產生一個或多個其他時脈頻率的時脈信號的時脈除法 々圖係t個積體電路的功能框圖’該積體電路包括處理器、一個或多 第油、二ίτ:模擬器和產生其他時脈頻料時脈信號的時脈除法器; 哭二te二固積體電路的功能框圖,該積體電路包括處理器、圖形處理 i二或/個電路、記紐和產生時脈錢的晶體振盪11模擬器; to 域理11和第11 ®的低轉顧⑽_電_功能框圖; ^ ;20圖係為_根據财技撇封裝在封裝材料巾的積體電路的功能框 * 度補彳貞晶片半導體振盡器的積體電路的功能框圖,該半 45 200828780 細本發_包㈣彻_嘯積趙=1’的側 =係為娜侧包㈣彻__換賴路封裝的侧 ,25 _较詳細地_第Μ _賴電路難醉 第27圖係為&amp;括温度樹n# 為包括温度補償輪入 梅崎㈣喻生採樣校 來梅樣校 第31A圖係為硬式磁碟機的功能框圖; 功― f31D圖係為車輛控制系統的功能框圖; ,31E圖辆行動雜的功驗圖; 第31F圖係為機上盒的功能框圖; ^ 31G圖係、為媒體播放機的功能框圖; 蝴樹伽__ ㈣觸部分上碱喃空退火麵_的_ #圖係為包括在石夕晶片的所選部分上形成的架空退火玻填製和/或環氣 46 200828780 樹脂層和傳導材料層的替換積體電路封裝_剖視圖; 的電路相鄰的退火玻璃衆和/或環氧樹脂層和傳 導材料層的替換積體電路封裝的側剖視圖; ' 第33Β圖係為包括與石夕晶片的振盈器相鄰的退火玻璃聚和 傳導材料層的替換積體電路封裝的侧剖視圖; 成樣《月曰層和 f 33C圖係為包括與矽晶片的電感器相鄰的退火 傳導材料層的替換積體電路封裝的側剖視圖; 和次衣乳树月曰層和 係為包括與㈣片的振i器電路中的電感器 或桃碰層和解㈣層_換频電路 ^玻璃水和/ 第34A-34D圖係為包括產生空氣間 和圖, 璃或矽層的替換積體電路封裝的側剖視圖f玻离漿和/或料樹脂部分和玻 第36A-36C ®係為包括多個積體電路封 :封裝都総產仏«隙触«魏和 第38圖顯示用於製造第32A_32D圖的積 第39圖係為晶趙振盡器模擬器積雜電路的的方法的示例性步鄉。 笋圖顯示在製造包細咖模擬器的频‘路輸行的步称的流 第42圖顯示在利用單個温度测 第43圖顯示作為温度的函數率^個月=行的步驟的流程圖; 線的位置的圖; 用早個温度測試點的直線或其他曲 f 44 _示在利用兩個温度魏點進行校正 弟45圖顯示作為温度的函數的頻率和 彻、=仃的步驟的流程圖; 位置和/或分辩度(definition)的圖. ^度測試點的直線或曲線的 第46圖顯蝴細㈣㈣咖物爛軸步驟的流 47 200828780 程圖; 第47圖顯示作為温度的函數的頻率和利用三個或更多個 广 txo / «、 - 溫度測試點的曲線«, and the inclusion of fine-envelope fine-value envelopes. The vibrating thief group can be sewn. ΪΪίΪ=Based on the score axis, it can be adjusted to Qian Lai (four). The control letter ^ now refers to Fig. 57' showing the charm of the cast body with temperature and amplitude compensation. The temperature and amplitude compensation can be combined and combined into a single crystal oscillator simulator. The rod oscillator is used for amplitude compensation and temperature compensation, which improves the accuracy of the resolution and amplitude. , , . When the semiconductor oscillator implemented by the above crystal oscillator simulator includes one or more senses, it is preferable to include a material having low electron mobility characteristics. For example, the material may include copper (Cu) or gold (Au) e pure (10) materials tending to electron migration transients. In other words, Cu and bismuth have relatively low electron mobility compared to A1. The low electron mobility of cu and Au tends to reduce the frequency drift as a function of time. In systems that use an external crystal oscillator to generate the reference frequency, it is also possible to use Μ to achieve the inductance ^ in these systems for the material used in the in-service device _« and the use of external crystals to generate reference frequency A crystal oscillator simulator system such as the one described above is not important. In other words, the external crystal oscillator in these systems corrects for frequency drift due to migration. - A number of embodiments of the invention have been described. However, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Therefore, other realities are also within the scope of the royal rights. 44 200828780 [Simple diagram of the diagram] $1 shows a block diagram of one aspect of the crystal oscillator simulator; Figure 2 shows a table of the relationship between temperature and correction factor; Figure 3 shows the relationship between temperature and correction factor Figure; $4 shows a block diagram of one aspect of the crystal oscillator simulator; = two-dimensional view of the crystal oscillator simulator connected to the external hybrid; ΐ 7Α ϋ_ external impedance crystal enchant simulator A detailed block diagram of the aspect; Figure 7 and Figure 7B are diagrams showing the relationship between the external impedance value and the digit value; the graph is an aspect of the oscillator component for generating an output having a periodic waveform. Box = 9 is a block diagram of one aspect of the spread spectrum generator; 10 is a flow chart for the operation of the analog crystal oscillator; Figure 11 is a block diagram of an aspect of the low power resonator; The 12-picture is a block diagram of another aspect of the low-power oscillator; the circuit and the function block of the integrated circuit of the 曰曰 振 — — 产生 产生 产生 贼Figure; running 嶋 4 office dough mixer simulation mm package 々 t processing And a functional block diagram of an integrated circuit for generating a clock signal for the processor and using a crystal button simulator for setting up the 222 implant; for: a functional block diagram of the integrated circuit The integrated circuit includes one or more circuits, a day of the device, a clock-pulse of the clock signal that generates one or more other clock frequencies, and a function of the t-integrated circuit. Block diagram 'The integrated circuit includes a processor, one or more oils, two ττ: simulators, and a clock divider that generates clock signals of other clock frequencies; a functional block diagram of the crying two-two-bulk circuit The integrated circuit includes a processor, a graphics processing i or a circuit, a note, and a crystal oscillator 11 simulator that generates clock money; to the domain 11 and the 11th low pass (10)_electric_function box Figure; ^ ; 20 Figure is a functional block diagram of the integrated circuit of the semiconductor circuit in accordance with the financial technology packaged in the package circuit of the package material towel, the half 45 200828780 _包(四)彻_啸积赵=1' side = is the side of the package (four) __ for the side of the package, 25 _ more detailed _ Μ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Function - f31D is the functional block diagram of the vehicle control system; 31E is the functional diagram of the mobile phone; 31F is the functional block diagram of the set-top box; ^ 31G system, the function box for the media player Figure </ br> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ A replacement integrated circuit package of a conductive material layer _ cross-sectional view; a side cross-sectional view of a circuit of an adjacent annealed glass and/or an epoxy resin layer and a conductive material layer; 'Figure 33 is included with stone A side cross-sectional view of a replacement integrated circuit package of an adjacent annealed glass poly and conductive material layer of a vibrator of a wafer; a sample of the Moone layer and the f 33C pattern including annealed conduction adjacent to the inductor of the tantalum wafer Side cross-sectional view of a replacement integrated circuit package of material layers; The tree layer and the layer are included in the (4) piece of the oscillator circuit or the inductor layer or the solution layer (four) layer _ frequency conversion circuit ^ glass water and / / 34A-34D diagrams including the generation of air between the map, Side cross-sectional view of the replacement integrated circuit package of glass or enamel layer f-glass and/or resin part and glass 36A-36C ® series include multiple integrated circuit seals: package is produced 仏 隙 隙 隙And Fig. 38 shows an exemplary step of the method for fabricating the product of Fig. 32A-32D, Fig. 39, which is a crystal oscillator simulator integrated circuit. The bottom view shows the flow of the step number in the frequency of the manufacturing of the fine coffee simulator. Fig. 42 shows a flow chart showing the steps of the function of the temperature as a function of temperature ^ month = line using a single temperature measurement Fig. 43; A diagram of the position of the line; a straight line or other curve f 44 with the previous temperature test point is shown in the flow chart using two temperature Wei points to correct the brother 45 diagram showing the frequency as a function of temperature and the step of 彻, =仃; position and / or resolution of the figure. ^ degree test point of the line or curve of the 46th picture show fine (four) (four) coffee object rotten axis step flow 47 200828780 process chart; figure 47 shows as a function of temperature Frequency and curve using three or more wide txo / «, - temperature test points

能框圖; 第48B圖係為包括MEMS諧振器電路的δ_Ε鎖相迴路的功能框圖; 第49圖係為具有温度補償的示例性mems諧振器電路的功能框圖; 框圖; 第50Α ®係為包括賴體聲波諧振器(FBAR)電路的分數鎖相迴路的功能 第50B圖係為包括FBAR諧振器電路的δ_Σ鎖相迴路的功能框圖; 第50C圖顯示示例性FBAR電路和FBAR ; 第51A圖係為根據現有技術的半導體LC振盪器的功能框圖; 弟51B圖藏不作為時間的函數的振幅漂移; 能框圖; 第52圖、第53A圖和第53B圖係為根據本公開的示例性半導體振盪器的功 第54-56圖係為根據本公開的示例性半導體LC振盪器的電路示意圖;以及 第57圖係為具有温度和振幅補償的半導體振盪器的功能框圖。 在各附圖中,類似的標號指示類似的元素。 【主要元件符號說明】 10、40、100、120、202、302、 322、352、502、1630晶體振盪器模擬器 12輸出信號 14、44、1554、1634、1910 半導體振盪器 16控制輸入 18、1632、1912非揮發性記憶體 20、50、858、1758、1858 校正信息 22、52、854、1636、1754、1854、1920 温度感應器 30儲存方式 32示例圖 54、1924加熱器 48 200828780 56控制器 58選擇輸入 102、104、122選擇管脚 106、108、124外部阻抗 126测量電路 127儲存電路 128數位值確定器 130地址產生器 132控制器 150阻抗值組Energy Block Diagram; Figure 48B is a functional block diagram of a δ_Ε phase-locked loop including a MEMS resonator circuit; Figure 49 is a functional block diagram of an exemplary MEMS resonator circuit with temperature compensation; Block Diagram; 50thΑ ® The function of the fractional phase-locked loop including the FBAR circuit is a functional block diagram of a δ_Σ phase-locked loop including the FBAR resonator circuit; and FIG. 50C shows an exemplary FBAR circuit and FBAR; 51A is a functional block diagram of a semiconductor LC oscillator according to the prior art; the amplitude shift of the semiconductor 51B is not a function of time; the energy block diagram; the 52nd, 53A, and 53B are according to the present disclosure. Figure 54-56 of an exemplary semiconductor oscillator is a circuit schematic of an exemplary semiconductor LC oscillator in accordance with the present disclosure; and Figure 57 is a functional block diagram of a semiconductor oscillator with temperature and amplitude compensation. Like reference numerals indicate like elements in the drawings. [Major component symbol description] 10, 40, 100, 120, 202, 302, 322, 352, 502, 1630 crystal oscillator simulator 12 output signals 14, 44, 1554, 1634, 1910 semiconductor oscillator 16 control input 18, 1632, 1912 non-volatile memory 20, 50, 858, 1758, 1858 correction information 22, 52, 854, 1636, 1754, 1854, 1920 temperature sensor 30 storage mode 32 example Figure 54, 1924 heater 48 200828780 56 control The device 58 selects the input 102, 104, 122 select pin 106, 108, 124 external impedance 126 measurement circuit 127 storage circuit 128 digital value determiner 130 address generator 132 controller 150 impedance value group

152數位輸出值組 154、158選擇值 156阻抗值範圍 200振盪器組件 204驅動鎖相迴路(PLL) 206、208多功能選擇管脚 210、212外部電阻器 214解碼器 300展頻振盪器 320低功率振盪器 324主動矽振盪器 326加法器 328控制器 330數位類比轉換器(DAC) 332整流器 334控制信號 350低功率振盪器 354電荷泵浦振盪器 356、840、1740、1840 電荷泵浦 358、1744、1844迴路濾波器 360、846、1746、1846 壓控振盪器(VCO) 49 200828780 362相位檢測器 364多工器 366鎖相迴路 400、402、404、406、408、412、414 框 500、518、600、700、710、724、 830、860、1730、1830、1880、1900 積體電路 504、544 電路 506外部組件 520時脈除法器 512、530、610 處理器152 digital output value set 154, 158 select value 156 impedance value range 200 oscillator component 204 drive phase locked loop (PLL) 206, 208 multi-function select pin 210, 212 external resistor 214 decoder 300 spread frequency oscillator 320 low Power oscillator 324 active 矽 oscillator 326 adder 328 controller 330 digital analog converter (DAC) 332 rectifier 334 control signal 350 low power oscillator 354 charge pump oscillator 356, 840, 1740, 1840 charge pump 358, 1744, 1844 loop filter 360, 846, 1746, 1846 voltage controlled oscillator (VCO) 49 200828780 362 phase detector 364 multiplexer 366 phase locked loop 400, 402, 404, 406, 408, 412, 414 block 500, 518, 600, 700, 710, 724, 830, 860, 1730, 1830, 1880, 1900 integrated circuit 504, 544 circuit 506 external component 520 clock divider 512, 530, 610 processor

522-1 〜522-N 電路 532-1 〜532-N 電路 540圖形處理器 542、856、1009、1019、1028、1066、 1094、1114、1047、1756、1856 記憶體 602-1 〜602-N 電路 7〇4、714、736封裝材料 711晶片半導體振盪器 718積體電路封裝 728墊片 732引線 733引線框 734結合線 738替換積體電路封裝 740積體電路基底 741晶片温度補償半導體振盪器 742電感器 744玻璃層 746空腔 750環氧材料層 752空氣空腔 50 200828780 760封裝材料 831、1731、1874分數鎖相迴路 832積體電路振盪器 836相位頻率探測器 844迴路濾波器 850、1750、1850 縮放電路 858、1831、1882 δ-Σ分數鎖相迴路 870、1870 Σ_δ 調制器 900流程圖522-1 ~ 522-N Circuit 532-1 ~ 532-N Circuit 540 Graphics Processor 542, 856, 1009, 1019, 1028, 1066, 1094, 1114, 1047, 1756, 1856 Memory 602-1 ~ 602-N Circuit 7〇4, 714, 736 Package Material 711 Chip Semiconductor Oscillator 718 Integrated Circuit Package 728 Shim 732 Lead 733 Lead Frame 734 Bond Line 738 Replace Integrated Circuit Package 740 Integrated Circuit Substrate 741 Wafer Temperature Compensated Semiconductor Oscillator 742 Inductor 744 glass layer 746 cavity 750 epoxy material layer 752 air cavity 50 200828780 760 package material 831, 1731, 1874 fractional phase-locked loop 832 integrated circuit oscillator 836 phase frequency detector 844 loop filter 850, 1750, 1850 scaling circuit 858, 1831, 1882 δ-Σ fractional phase-locked loop 870, 1870 Σ_δ modulator 900 flowchart

902、904、906、908 步驟 920流程圖 922、924、926、928 步驟 1000硬式磁碟機 1002、1012、1022信號處理電路和/或控制電路 1006磁性儲存媒體 1008無線通訊連線 1010數位多功能光碟(DVD)驅動器 1016光儲存媒體 1017無線通訊連線 1018、1027、1046、1064、1090、1110 大容量資料儲存裝置 1020高畫質電視(HDTV) 1026顯示器 1029、1048、1068、1096、1116 WLAN 網路接口 1030車輛 1032傳動控制系統 1040控制系統 1042輸入感應器 1044輸出裝置 1050行動電話 1051通訊天線 1052、1084、1104信號處理電路和/或控制電路 51 200828780 1056麥克風 1058音頻輸出 1060、1088、1107 顯示器 1062輸入裝置 1080機上盒 1100媒體播放機 1108用户輸入 1109音頻輸出 1204、1304、1404 矽晶片 1206、1306退火玻璃漿層902, 904, 906, 908 Step 920 Flowchart 922, 924, 926, 928 Step 1000 Hard Disk Drive 1002, 1012, 1022 Signal Processing Circuit and/or Control Circuit 1006 Magnetic Storage Media 1008 Wireless Communication Connection 1010 Digital Multifunction Optical Disc (DVD) Drive 1016 Optical Storage Media 1017 Wireless Communication Connections 1018, 1027, 1046, 1064, 1090, 1110 Large Capacity Data Storage Device 1020 High Definition Television (HDTV) 1026 Display 1029, 1048, 1068, 1096, 1116 WLAN Network interface 1030 vehicle 1032 transmission control system 1040 control system 1042 input sensor 1044 output device 1050 mobile telephone 1051 communication antenna 1052, 1084, 1104 signal processing circuit and / or control circuit 51 200828780 1056 microphone 1058 audio output 1060, 1088, 1107 Display 1062 input device 1080 on-board 1100 media player 1108 user input 1109 audio output 1204, 1304, 1404 矽 wafer 1206, 1306 annealed glass layer

1208、1308鑄模材料 1200、1210、1240、1250、1260、1270 替換積體電路封裝 1212傳導材料層或者塗覆 1220、1230、1300、1330、1340、1360、 1380、1390、1400、1450 積體電路封裝 1242電路組件 1252、1320振盪器 1262、1274電感器 1272振盪器電路 1322電路 1324、1384空氣間隙 1342環氧材料部分 1382玻璃或矽部分 1410A、1410B多個間隔開的AGP和/或環氧材料部分 1310、1408玻璃或矽層 1410退火玻璃漿/環氧材料部分 1414虛線切線 1420墊片 14144、1414-2、1414-3 處 1454容器 1456、1456’傳導材料層 52 200828780 1460墊片 1462切割線 1500方法 1502、1506、1508、1510、1520 步驟 1550晶體振盪器模擬器積體電路(IC) 1552非揮發性記憶體 1554半導體振盪器 1556温度感應器 1558加熱器 1560、1928失能電路1208, 1308 mold material 1200, 1210, 1240, 1250, 1260, 1270 replace integrated circuit package 1212 conductive material layer or coating 1220, 1230, 1300, 1330, 1340, 1360, 1380, 1390, 1400, 1450 integrated circuit Package 1242 circuit components 1252, 1320 oscillator 1262, 1274 inductor 1272 oscillator circuit 1322 circuit 1324, 1384 air gap 1342 epoxy material portion 1382 glass or germanium portion 1410A, 1410B a plurality of spaced apart AGP and / or epoxy materials Portion 1310, 1408 glass or tantalum layer 1410 annealed glass paste/epoxy material portion 1414 dashed line tangent 1420 spacer 14144, 1414-2, 1414-3 at 1454 container 1456, 1456' conductive material layer 52 200828780 1460 gasket 1462 cutting line 1500 Method 1502, 1506, 1508, 1510, 1520 Step 1550 Crystal Oscillator Simulator Integrated Circuit (IC) 1552 Non-volatile Memory 1554 Semiconductor Oscillator 1556 Temperature Sensor 1558 Heater 1560, 1928 Disabling Circuit

1600、1602、1604、1606、1608、1610、 1624、1640、1642、1644、1646、1648、1650 步驟 1638自適應校正電路 1652測試温度 1654測試頻率 1656單個測試點自動定位預定的直線或曲線 1657更高的單個測試點自動定位的直線或曲線 1658更低的單個測試點自動定位的直線或曲線 1660、1662、1664、1666、1668 步驟 1676兩個測試點(測試温度1672小1672-2和測試頻率1674-1、1764-2) 定位和/或限定直線或曲線 1680、1682、1684、1686、1688、1690 步驟 1696三個或更多個測試點(測試温度^924、1692_2、...、1692_丁和 測試頻率1694-1、1694-2、…、1794-T)定位和/或限定直線或 曲線 Π32、1832、1902微機電系統(MEMS)諧振器電路 1733、1833、1904 MEMS 諧振器 1736、1836相位頻率探測器 1876薄膜體聲波諧振器(FBAR)電路 1878薄膜體聲波諧振器 53 200828780 1892聲鏡 1898基底 1888、1890 電極 1894高聲阻抗層 1896低聲阻抗層 2010半導體振盪器電路 2014 LC儲能電路 2016交叉耦合電晶體 2017偏置 2018電流偏置電路1600, 1602, 1604, 1606, 1608, 1610, 1624, 1640, 1642, 1644, 1646, 1648, 1650 Step 1638 Adaptive Correction Circuit 1652 Test Temperature 1654 Test Frequency 1656 Single Test Point Automatically Positioning a Predetermined Line or Curve 1657 High single test point automatically positioned straight line or curve 1658 lower single test point automatically positioned straight line or curve 1660, 1662, 1664, 1666, 1668 Step 1676 Two test points (test temperature 1672 small 1672-2 and test frequency 1674-1, 1764-2) Positioning and/or defining straight lines or curves 1680, 1682, 1684, 1686, 1688, 1690 Step 1696 Three or more test points (test temperature ^924, 1692_2, ..., 1692 _ Ding and test frequency 1694-1, 1694-2, ..., 1794-T) Positioning and / or defining a straight line or curve Π 32, 1832, 1902 microelectromechanical system (MEMS) resonator circuit 1733, 1833, 1904 MEMS resonator 1736 1836 phase frequency detector 1876 film bulk acoustic resonator (FBAR) circuit 1878 film bulk acoustic resonator 53 200828780 1892 acoustic mirror 1898 substrate 1888, 1890 electrode 1894 high acoustic impedance layer 1896 low acoustic impedance layer 2010 semiconductor oscillation Circuit 2014 LC tank circuit 2016 cross-coupled transistor 2017 bias 2018 current bias circuit

2020具有振幅補償的半導體振盪器 2021振幅調整模組 2022具有振幅調整輸入的半導體振盪器 2023諧振電路 2024可調整偏置模組 2025 LC儲能電路 2024-1可調整電流源 2026交叉耦合電晶體 2034振幅調整模組 542020 semiconductor oscillator 2021 with amplitude compensation amplitude adjustment module 2022 semiconductor oscillator 2023 with amplitude adjustment input resonant circuit 2024 adjustable bias module 2025 LC energy storage circuit 2024-1 adjustable current source 2026 cross-coupled transistor 2034 Amplitude adjustment module 54

Claims (1)

200828780 十、申請專利範圍: 1 ·一種晶體振盪器模擬器積體電路,包括: -第-温絲應n,賊觸述積體電路一· 記數並且基於所述第-温度;㈣數中 一=;述振幅相比較,並且基於所· 2 3 ·如申4專伽職2項所述之晶體賴 二ί==條驗钱置錢,該辟魏韻述驗ΐίϊ置 4 之晶體振峨擬_電路,… 嶋細晴細,其中,所述 6 ϋΐίϊί _項所述之晶體振細_碰,其中,所述 一電感·電容(LC)電路;以及 父叉耦合電晶體,其與所述Lc電路通信。 7 項戶f述之晶體振盪器模擬_體電路,進-步包括 的函數。'^擇輪人縣崎細健崎賴轉為外部被動元件 ㈣刪料―步包括: 9 .校正參數被儲存後使所述加熱器失去能力。 明乾圍弟8項所述之晶體振盪器模擬器積體電路,其中,所述 55 200828780 加熱器回應所述第一温度感應器而操作。 10 ·如申請專利範圍第1項所述之晶體振盪器模擬器積體電路,其中,所 述半導體振盪器從包括電感-電容(LC)振盪器、電阻-電容(RC)振 盪器和環形振盪器組成的組中選出。 11 ·如申請專利範圍第1項所述之晶體振盪器模擬器積體電路,其中,所 述半導體振盪器包括包含金或銅之一的電感。200828780 X. Patent application scope: 1 · A crystal oscillator simulator integrated circuit, including: - the first temperature wire should be n, the thief touches the integrated circuit one count and based on the first temperature; (four) number One =; the amplitude is compared, and based on the 2 2 · The crystal according to the 2nd article of the application of the 2nd singer 2, the test of the money, the Wei Zhen rhyme test ΐ ϊ ϊ 4 _ circuit, ... 嶋 fine fine, wherein the 6 ϋΐ ϊ ϊ 之 之 晶体 , , , , , , , , , , , , , , , , , 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体Lc circuit communication. The 7-item crystal oscillator simulation _ body circuit, the function included in the step-by-step. '^ 轮 轮 轮 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县The crystal oscillator simulator integrated circuit of the eighth aspect of the present invention, wherein the 55 200828780 heater operates in response to the first temperature sensor. 10. The crystal oscillator simulator integrated circuit of claim 1, wherein the semiconductor oscillator comprises an inductor-capacitor (LC) oscillator, a resistor-capacitor (RC) oscillator, and a ring oscillator. Selected from the group consisting of. The crystal oscillator simulator integrated circuit of claim 1, wherein the semiconductor oscillator comprises an inductor comprising one of gold or copper. 5656
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI457270B (en) * 2009-02-13 2014-10-21 Wolfson Microelectronics Plc Mems device and process
TWI509978B (en) * 2011-08-01 2015-11-21 Nihon Dempa Kogyo Co Crystal controlled oscillator and oscillator apparatus
CN113258877A (en) * 2020-02-10 2021-08-13 精工爱普生株式会社 Oscillator

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US5309090A (en) * 1990-09-06 1994-05-03 Lipp Robert J Apparatus for heating and controlling temperature in an integrated circuit chip
US6680655B2 (en) * 2001-08-01 2004-01-20 Sige Semiconductor Inc. Automatic gain control for a voltage controlled oscillator
US20060113639A1 (en) * 2002-10-15 2006-06-01 Sehat Sutardja Integrated circuit including silicon wafer with annealed glass paste
DE102004015539A1 (en) * 2004-03-30 2005-10-20 Infineon Technologies Ag Semiconductor device with self-heating

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI457270B (en) * 2009-02-13 2014-10-21 Wolfson Microelectronics Plc Mems device and process
TWI509978B (en) * 2011-08-01 2015-11-21 Nihon Dempa Kogyo Co Crystal controlled oscillator and oscillator apparatus
CN113258877A (en) * 2020-02-10 2021-08-13 精工爱普生株式会社 Oscillator
CN113258877B (en) * 2020-02-10 2023-06-13 精工爱普生株式会社 Oscillator

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