200828753 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電源轉拖备 y锝換糸統，特別是指一種直 流至直流電源轉換系統。 【先前技術】 直SlL至直流電源轉換系統用於將 ，、 凡⑺W將—輸入直流電壓做電 壓位準的調節，使其輸出直流電壓 电& 疋在所設定的電壓值 〇 參閱圖1與圖2，該直流至直户雪 直/爪電源轉換系統是一閉迴 路系統，且包含一具有一電感丨丨和一 也谷12的切換轉換皁 元、一具有一放大器13的補償單开爲 ^ _ 貝早70及一脈衝寬度調變單元 。該電感11及該電容12會在放痛-a 曰隹Λ(1)所不的頻率處產生二極 點（pole )，該電容12及苴箄埼虫磁兩 / 汉八寺效串聯電阻（Equivalent200828753 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a power conversion device, and more particularly to a DC to DC power conversion system. [Prior Art] Straight SlL to DC power conversion system is used to adjust the input DC voltage to the voltage level of (7)W, so that it outputs DC voltage & 疋 at the set voltage value 〇 see Figure 1 and 2, the DC to direct snow straight/claw power conversion system is a closed loop system, and includes a switching conversion soap element having an inductance 一 and a 谷谷12, and a compensation single opening with an amplifier 13 ^ _ Bei early 70 and a pulse width modulation unit. The inductor 11 and the capacitor 12 generate a pole at a frequency at which the pain-a 曰隹Λ(1) does not occur. The capacitor 12 and the worm magnetic two / Hanba Temple series resistance (Equivalent
Series Resist·，ESR )會在式（2)所示的頻率處產生一零 點Uer。），而該放大器13會在低頻處產生一極點（因杉 最大增益很大，通常落在70分貝UB)至8q》貝的範圍 内）。一般來說，該放大器13所產生之極點的頻率最低， §亥電感11及該電容12所產生之極點的頻率次之，該電容 12及其等效串聯電阻所產生之零點的頻率再次之。 2n4Uc 式（1)Series Resist·, ESR) produces a zero Uer at the frequency shown in equation (2). ), and the amplifier 13 will generate a pole at a low frequency (since the maximum gain of the fir, usually falling within 70 dB UB) to 8q". Generally, the frequency of the pole generated by the amplifier 13 is the lowest, and the frequency of the pole generated by the capacitor 11 and the capacitor 12 is second, and the frequency of the zero point generated by the capacitor 12 and its equivalent series resistance is again. 2n4Uc type (1)
FesrFesr
Ίτι · Resr · C 式（2) 200828753 J中，是該電感u及該電容12所產生之極點的頻 :，&疋該電容12及其等效串聯電阻所產 率乂是該電感u的值，c是該電容12的值 電容12之等效串聯電阻的值。 疋 由於閉坦路系統本身就有穩定度的問題，如果沒有把 頻率補償做好，該閉迴路系統將會不穩定。使該閉迴路系 統穩定的條件是：纟開迴路下，當該系統的轉換函數的增 益為〇分貝時，該增益的斜率落在-20分貝/十倍頻（ dB/decade)至-40分貝/十倍頻的範圍内，且該轉換函數的 相位邊限（Phase Margin )大於〇度。 在該直流至直流電源轉換系統中，由於有三個極點相 鄰，如果沒有在低於該電感Η及該電容12所產生之極點的 頻率處產生一零點，該系統將會不穩定。習知的頻率補償 方法有三種，分別是類型一（Type I )、類型二（Type π ) 及類型三（Type III )。以下分別說明此三種頻率補償方法。 (1)類型一頻率補償方法 此方法利用在該放大器13的反向輸入端及輸出端之間 串聯的一第一電容14及一第一電阻15來產生一第一零點 。該第一零點的頻率如式（3)所示，且被設為低於該電感i i 及該電容12所產生之極點的頻率，以使該直流至直流電源 轉換系統穩定。Ίτι · Resr · C (2) 200828753 J, is the frequency of the inductor u and the pole generated by the capacitor 12: & 疋 the capacitance 12 and its equivalent series resistance yield 乂 is the inductance u The value, c is the value of the equivalent series resistance of the value capacitor 12 of the capacitor 12.疋 Since the closed circuit system itself has a problem of stability, if the frequency compensation is not done well, the closed circuit system will be unstable. The condition for stabilizing the closed-loop system is that, under the open circuit, when the gain of the transfer function of the system is 〇 decibel, the slope of the gain falls between -20 dB/decade (dB/decade) to -40 dB. /10 times the frequency range, and the phase margin (Phase Margin) of the conversion function is greater than the 〇 degree. In the DC to DC power conversion system, since three poles are adjacent, if a zero is generated at a frequency lower than the inductance Η and the pole generated by the capacitor 12, the system will be unstable. There are three conventional frequency compensation methods, namely Type I, Type π, and Type III. The three frequency compensation methods are described separately below. (1) Type-Frequency Compensation Method This method generates a first zero point by using a first capacitor 14 and a first resistor 15 connected in series between the inverting input terminal and the output terminal of the amplifier 13. The frequency of the first zero point is as shown in equation (3) and is set to be lower than the frequency of the inductor i i and the pole generated by the capacitor 12 to stabilize the DC to DC power conversion system.
Fzi " Ιπ-R^C, 式（3) 其中，Fz/是該第一零點的頻率，G是該第一電容14 6 200828753 的值，而A是該第一電阻15的值。 (2)類型二頻率補償方法 除了利用該第一電容14及該第一電阻15來產生該第 一零點，此方法更利用電連接在該放大器13的反向輸入端 及輸出端之間的一第二電容16來產生一第一極點。該第一 極點的頻率如式（4)所示。 Ρ1 式(4) c1+c2 其中，尸/>/是該第一極點的頻率，C/是該第一電容i4 的值，A是該第一電阻15的值，而q是該第二電容16的 值。 (3)類型三頻率補償方法 除了利用該第一電容14、該第一電阻15及該第二電容 16來產生該第一零點及該第一極點，此方法更利用一第三 電容17、一第二電阻18及一第三電阻19來產生一第二零 ^ 一第二極點及一第三極點。該第三電容17及該第二電 阻18在該輸出直流電壓及該放大器13的反向輸入端之間 串聯，而該第三電阻19電連接在該輸出直流電壓及該放大 =13的反向輸入端之間。該第二零點及該第二極點的頻率 刀別如式（5)及式（6)所示，而該第三極點的頻率為〇。 F = 1____ Ζ1 式(5) 7 200828753 tP2 =---— 2π · R2，C3 式（6) 其中，是該第二零點的頻率，是該第二極點的 頻率，q是該第三電容17的值，A是該第二電阻18的值 ，而A是該第三電阻19的值。 藉由適當調整該第一零點、該第二零點、該第—極點 及該第二極點的頻率，可使該直流至直流電源轉換系統穩 定，例如：將該第一零點的頻率設為該電感u及該電容^ 所產生之極點的頻率的1/2，將該第二零點的頻率設為與該 電感11及该電容12所產生之極點的頻率相同，將該第_極 點的頻率設為該系統頻率的1/2，而將該第二極點的頻率設 為與該電容12及其等效串聯電阻所產生之零點的頻率相同 〇 當该電容12是一多層陶瓷電容（MultMayer Ceraniic Capacitor ’ MLCC )時，由於其等效串聯電阻很小（通常是 其匕種類電谷之等效串聯電阻的1/1〇〇以下），該電容12及 其等效串聯電阻所產生之零點的頻率將遠大於該電感u及 該電谷12所產生之極點的頻率，使得該類型一及該類型二 頻率補彳貝方法無法讓該直流至直流電源轉換系統穩定。該 類型二頻率補償方法則可以解決此問題。 忒類型二頻率補償方法除了產生該第一零點還會產生 °亥第一極點’容易使其無法讓該直流至直流電源轉換系統 穩定’因此通常不被使用。 然而，在該類型一至該類型三頻率補償方法中，該第 8 200828753 一至該第三電容14、16、17的值要很大才能將該第一零點 、該第二零點、該第一極點及該第二極點的頻率調整到所 設定的值，但在積體電路内直接做大電容是很困難的（因 為面積大），習知是使用一些電路技巧來放大電容的值以實 現大電容。 ' 習知的頻率補償方法都是在該放大器13的最大增益很 大但其產生之極點的頻率很低的情況下進行，而本發明則 提出一種可以減少電容數目的頻率補償方法，藉由降低該 放大13的隶大增盈以提南其產生之極點的頻率來進行頻 率補償，以使該直流至直流電源轉換系統穩定。 【發明内容】 因此，本發明之目的即在提供一種可以減少電容數目 的直流至直流電源轉換系統。 於是，本發明直流至直流電源轉換系統包含一切換轉 換單元、一補償單元及一脈衝寬度調變單元。 該切換轉換單元包括一電感及一電容，且受一脈衝俨 號控制，以將一輸入直流電壓轉換成一輸出直流電壓。該 電感及該電容產生頻率相同的兩極點，而該電容及其等饮 串聯電阻產生一零點。 、> 該補償單元包括-放大單元。該放大單元比較 直流電壓及一參考電壓。 ’ 該脈衝寬度調變單元基於一系統頻率進行操作，並產 生該脈衝信號，且根據該放大單元的比較結果以電壓模 調變該脈衝信號的寬度。 ' 200828753 其中’該放大單元的最大增益被設定，使其產生之極 點的頻率落在該電容及其等效串聯電阻所產生之零點的頻 率及該系統頻率之間。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配a參考圖式之一個較佳實施例的詳細說明中，將可 清楚地呈現。 參閱圖3,本發明直流至直流電源轉換系統之較佳實施 例包含一切換轉換單元2、一補償單元3及一脈衝寬度調變 單元4。 參閱圖3與圖4，該切換轉換單元2包括一開關21、 -個二極體22、-電感23及-電容24。該開關21的-端 接收一輸入直流電壓，而另一端電連接到該二極體22的陰 極及該電感23的-端，且受—脈衝信號控制是否導通。該 二極體22的陽極接地。該電感23的另一端電連接到該電 容24的一端，且輸出一輸出直流電壓以驅動一負載5。該 電容24的另一端接地。 當該開關21導通時，該二極體22不導通，且該輸入 直流電μ產n經該電感23的電流’使該電感23儲存 能量。當該開關21不導捅日卑，& 7格# 等逋柃為了維持電流連續，該二極 體導通，使該電感釋放所儲存的能量。 該電感23及該電容24會在式⑴所示的頻率處產生二 而該電容24及其等效串聯電阻會在式⑺所示的頻率 處產生-零點，且該電感23及該電容以所產生之極點的 10 200828753 之零點的頻率 頻率低於該電容24及其等效串聯電阻所產生 參閱圖3與圖5，該補償單元3包括一分壓單元η及 一放大單元32。該分壓單元31包括一第一電阻3 二電阻312。該第—電阻311的—端接收該輸出直流電壓， 而另一端透過該第二電& 312電連接到地，且輸出一分壓 "亥放大單元32比較該分壓與一參考電塵。 該脈衝寬度調變單元4基於一系統頻率進行操作，並 產生該脈衝信號，且根據該放大單元32的比較結果以電壓 模式調變㈣衝信號的寬度，當該分料元3ι輸出的分壓 大於該參考電壓時，減少該脈衝信號的寬度，以降低該輸 出直流電壓’而當該分壓單元31輸出的分壓小於該參考電 壓時，增加該脈衝信號的寬度，以提高該輸出直流電壓。 該系統頻率高於該電容24及其等效串聯電阻所產生之零點 的頻率。藉由改變該第-電阻311及該第二電阻312的比例 ’可以改變該輸出直流電壓。 以下說明該補償單元3如何進行頻率補償。 參閱圖5與圖6,該放大單元32包括一放大器321、 -第三電阻322、一第四電阻323、一第五電阻324、一第 -緩衝器325及-第二缓衝器326。該放大器321包括一正 向輸入端、-反向輸入端及-輸出端。該第三電阻322電 連接於該放大器的反向輸人端及輪出端之間，該第四電阻 323電連接於該放大器321的正向輪人端及地之間，且盆值 是設為與該第三電⑯322的值相同，而該第五電？且似電 11 200828753 連接於该放大器321的反向輸入端及地之間，且其值是設 為該第三電阻322的值的κ倍。該第一緩衝器325接收該 分壓單兀31所產生的分壓，並輸出該分壓到該放大器321 的反向輸入端，而該第二緩衝器326接收該參考電壓，並 輸出4參考電壓到遺放大II 321㈤正向輸人端。目7顯示 該放大器321的一種實施方式，而圖8顯示該放大單元32 的頻率響應。 為了使該直流至直流電源轉換系統穩定，該放大單元 32的最大增益為K，並藉由該第三至該第五電阻322、323 、324使其小於該放大器321的最大增益，進而使其產生之 極點的頻率（即_3分貝頻率）落在該電容24及其等效串聯 電阻所產生之零點的頻率及該系統頻率之間，以形成如圖9 所示的開迴路頻率響應（即在開迴路下，當該直流至直流 電源轉換系統的轉換函數的增益為〇分貝時，該增益的斜 率落在-20分貝/十倍頻至_4〇分貝/十倍頻的範圍内，且該轉 換函數的相位邊限大於〇度）。較佳地，該放大單元W的 最大增益落在30分貝1 50 Α貝的範圍内，而其產生之極 點的頻率落在該系統頻率的1/5〜1/2的範圍内。 多閱圖3、圖4與圖5，當該電容24是一多層陶瓷電 ，時’由於其等效串聯電阻很小（通常是其它種類電容之 等效串如電阻的1/1〇〇以下），該電容24及其等效串聯電阻 所產生之零點的頻率將遠大於該電感23及該電容24所產 生之極點的頻率，肖習知相同，會造成該直流至直流電源 轉換系統不穩定。此時，可以在該分壓單^ 31的第一電阻 12 200828753 311旁並聯一個電容（圖5中未示），以產生一零點，且該 零點的頻率被設為落在該電感23及該電容24所產生之極 點的頻率及該電容24與其等效串聯電阻所產生之零點的頻 率之間。較佳地，該零點的頻率被設為與該電感23及該電 容24所產生之極點的頻率相同。 值得注意的是，在本實施例中，該直流至直流電源轉 換系統是一降壓（Buck )轉換系統，但也可以是一升壓（ Boost)轉換系統、一反相（Inverting )轉換系統、一升降 壓（Buck-Boost)轉換系統、一邱克（Cuk)轉換系統、一 單 ^ 初級電感轉換糸統（Single-Ended Primary Inductance Converter，SEPIC)、一則它（Zeta)轉換系統、一返馳式 (Flyback )轉換糸統或一順向式（Forward )轉換系統，且 不以此為限’只要是該切換轉換單元2包括至少一電感及 至少一電容即可。 在本實施例中，該補償單元3的放大單元32是以電導 放大器的方式來實現，但也可以其它方式來實現。該補償 單元3也可以不包括該分壓單元31，此時，該輸出直流電 壓與該參考電壓相同。 歸納上述，本發明是藉由降低該補償單元3的放大單 元32的最大增益以提高其產生之極點的頻率來進行頻率補 倡’不需使用額外的電容，而習知的類型一頻率補償方法 則需使用該第一電容14，且當該電容24是一多層陶究電容 時，本發明只需在該分壓單元31的第一電阻311旁並聯一 個電容即可，而習知的類型三頻率補償方法則需使用該第 13 200828753 一至該第三電容14、16、17。mLL 丄々 ’因此，本發明確實可以達到 減少電容數目的目的。 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明内容所作之簡單的等效變化與修m 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1疋種習知的直流至直流電源轉換系統的電路方 塊圖； ^圖2是一電路圖，說明該習知的直流至直流電源轉換 系統的一補償單元所使用的頻率補償方法； 圖3是本發明直流至直流電源轉換系統之較佳實施例 的電路方塊圖； 圖4是该較佳實施例的一切換轉換單元的電路圖； 图疋β亥較佳實施例的一補償單元的電路圖； 圖6疋該補償單元的一放大單元的電路圖； 圖7疋該放大單元的電路圖； 圖8疋该放大單元的頻率響應圖；及 圖9是該較佳實施例的開迴路頻率響應圖。 14 200828753 【主要元件符號說明】 1…、 切換轉換單元 321 21 · · · 開關 322 22· * · 二極體 323 23« * * 電感 324 24 ♦… 電容 325 3 補償單元 326 31…· 分壓單元 4 · 311，· 第一電阻 元 312 · · 第二電阻 5 · 32· · · 放大單元 放大器 第三電阻 第四電阻 第五電阻 第一緩衝器 第二緩衝器 脈衝寬度調變單 負載 15Fzi " Ιπ-R^C, Equation (3) where Fz/ is the frequency of the first zero point, G is the value of the first capacitor 14 6 200828753, and A is the value of the first resistor 15. (2) Type 2 Frequency Compensation Method In addition to using the first capacitor 14 and the first resistor 15 to generate the first zero point, the method is further electrically connected between the inverting input terminal and the output terminal of the amplifier 13. A second capacitor 16 produces a first pole. The frequency of the first pole is as shown in equation (4). Ρ1 Equation (4) c1+c2 where corpse/>/ is the frequency of the first pole, C/ is the value of the first capacitor i4, A is the value of the first resistor 15, and q is the second The value of capacitor 16. (3) Type 3 frequency compensation method, in addition to using the first capacitor 14, the first resistor 15 and the second capacitor 16 to generate the first zero point and the first pole, the method further utilizes a third capacitor 17, A second resistor 18 and a third resistor 19 generate a second zero and a third pole. The third capacitor 17 and the second resistor 18 are connected in series between the output DC voltage and the inverting input terminal of the amplifier 13, and the third resistor 19 is electrically connected to the output DC voltage and the reversal of the amplification=13 Between the inputs. The frequency of the second zero point and the second pole is as shown in equations (5) and (6), and the frequency of the third pole is 〇. F = 1____ Ζ1 Equation (5) 7 200828753 tP2 =---- 2π · R2,C3 Equation (6) where is the frequency of the second zero point, the frequency of the second pole, q is the third capacitor A value of 17, A is the value of the second resistor 18, and A is the value of the third resistor 19. The DC to DC power conversion system can be stabilized by appropriately adjusting the frequencies of the first zero point, the second zero point, the first pole point and the second pole point, for example, setting the frequency of the first zero point For the inductance u and the frequency of the pole generated by the capacitor ^, the frequency of the second zero point is set to be the same as the frequency of the pole generated by the inductor 11 and the capacitor 12, and the first pole is used. The frequency is set to 1/2 of the frequency of the system, and the frequency of the second pole is set to be the same as the frequency of the zero point generated by the capacitor 12 and its equivalent series resistance. When the capacitor 12 is a multilayer ceramic capacitor (MultMayer Ceraniic Capacitor ' MLCC ), due to its small equivalent series resistance (usually less than 1/1〇〇 of the equivalent series resistance of its 匕 type electric valley), the capacitor 12 and its equivalent series resistance are generated. The frequency of the zero point will be much larger than the frequency of the inductor u and the pole generated by the valley 12, so that the type one and the type two frequency complement mussel method cannot stabilize the DC to DC power conversion system. This type of two-frequency compensation method can solve this problem. The 忒 type two frequency compensation method, in addition to generating the first zero point, also produces a first pole of 'have' which makes it impossible for the DC to DC power conversion system to be stable' and therefore is generally not used. However, in the type 1 to the type three frequency compensation method, the value of the eighth 200828753 one to the third capacitors 14, 16, 17 is large to be the first zero point, the second zero point, the first The frequency of the pole and the second pole is adjusted to the set value, but it is difficult to directly make a large capacitance in the integrated circuit (because of the large area), it is conventional to use some circuit techniques to amplify the value of the capacitor to achieve a large capacitance. The conventional frequency compensation method is performed under the condition that the maximum gain of the amplifier 13 is large but the frequency of the generated pole is very low, and the present invention proposes a frequency compensation method capable of reducing the number of capacitors by reducing The amplification of the amplification 13 is frequency compensated by the frequency of the poles generated by the south to stabilize the DC to DC power conversion system. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a DC to DC power conversion system that can reduce the number of capacitors. Therefore, the DC to DC power conversion system of the present invention comprises a switching conversion unit, a compensation unit and a pulse width modulation unit. The switching conversion unit includes an inductor and a capacitor and is controlled by a pulse sigma to convert an input DC voltage into an output DC voltage. The inductor and the capacitor produce two poles of the same frequency, and the capacitor and its series resistance generate a zero. , > The compensation unit includes an amplifying unit. The amplifying unit compares the DC voltage with a reference voltage. The pulse width modulation unit operates based on a system frequency and generates the pulse signal, and the width of the pulse signal is modulated by voltage according to the comparison result of the amplification unit. ' 200828753 where the maximum gain of the amplifying unit is set such that the frequency of the pole it produces falls between the frequency of the zero generated by the capacitor and its equivalent series resistance and the system frequency. The above and other technical contents, features and effects of the present invention will be apparent from the following detailed description of a preferred embodiment of the invention. Referring to Figure 3, a preferred embodiment of the DC to DC power conversion system of the present invention includes a switching conversion unit 2, a compensation unit 3, and a pulse width modulation unit 4. Referring to FIG. 3 and FIG. 4, the switching conversion unit 2 includes a switch 21, a diode 22, an inductor 23 and a capacitor 24. The switch terminal 21 receives an input DC voltage, and the other end is electrically connected to the cathode of the diode 22 and the - terminal of the inductor 23, and is controlled by the -pulse signal. The anode of the diode 22 is grounded. The other end of the inductor 23 is electrically connected to one end of the capacitor 24, and outputs an output DC voltage to drive a load 5. The other end of the capacitor 24 is grounded. When the switch 21 is turned on, the diode 22 is not turned on, and the input direct current generates a current 'passed by the inductor 23' to cause the inductor 23 to store energy. When the switch 21 is not illuminating, the & 7 grid # is equal to 维持 to maintain current continuity, the diode is turned on, causing the inductor to release the stored energy. The inductor 23 and the capacitor 24 generate two at a frequency represented by the equation (1), and the capacitor 24 and its equivalent series resistance generate a -zero point at a frequency represented by the equation (7), and the inductor 23 and the capacitor are The frequency of the zero point of the generated 10 200828753 is lower than that of the capacitor 24 and its equivalent series resistance. Referring to FIG. 3 and FIG. 5 , the compensation unit 3 includes a voltage dividing unit η and an amplifying unit 32 . The voltage dividing unit 31 includes a first resistor 3 and a second resistor 312. The first end of the first resistor 311 receives the output DC voltage, and the other end is electrically connected to the ground through the second electric & 312, and outputs a partial pressure " Hai amplification unit 32 compares the divided voltage with a reference electric dust . The pulse width modulation unit 4 operates based on a system frequency, and generates the pulse signal, and according to the comparison result of the amplification unit 32, the width of the signal is modulated by the voltage mode (4), and the partial pressure of the output element 3ι is output. When the reference voltage is greater than the reference voltage, the width of the pulse signal is reduced to reduce the output DC voltage'. When the voltage divided by the voltage dividing unit 31 is less than the reference voltage, the width of the pulse signal is increased to increase the output DC voltage. . The frequency of the system is higher than the frequency of the zero generated by the capacitor 24 and its equivalent series resistance. The output DC voltage can be changed by changing the ratio of the first-resistor 311 and the second resistor 312'. How the compensation unit 3 performs frequency compensation will be described below. Referring to FIGS. 5 and 6, the amplifying unit 32 includes an amplifier 321, a third resistor 322, a fourth resistor 323, a fifth resistor 324, a first buffer 325, and a second buffer 326. The amplifier 321 includes a forward input, an inverted input, and an - output. The third resistor 322 is electrically connected between the reverse input end and the output end of the amplifier. The fourth resistor 323 is electrically connected between the forward end of the amplifier 321 and the ground, and the pot value is set. Is the same value as the third power 16322, and the fifth power? And the electric power 11 200828753 is connected between the inverting input terminal of the amplifier 321 and the ground, and its value is set to be κ times the value of the third resistor 322. The first buffer 325 receives the divided voltage generated by the voltage dividing unit 31, and outputs the divided voltage to the inverting input terminal of the amplifier 321, and the second buffer 326 receives the reference voltage, and outputs 4 reference. Voltage to the amplification II 321 (five) forward input. An embodiment of the amplifier 321 is shown in Fig. 7, and a frequency response of the amplifying unit 32 is shown in Fig. 8. In order to stabilize the DC to DC power conversion system, the maximum gain of the amplifying unit 32 is K, and the third to the fifth resistors 322, 323, 324 are made smaller than the maximum gain of the amplifier 321, thereby The frequency of the generated pole (ie, the _3 dB frequency) falls between the frequency of the zero generated by the capacitor 24 and its equivalent series resistance and the system frequency to form an open loop frequency response as shown in FIG. Under the open loop, when the gain of the conversion function of the DC-to-DC power conversion system is 〇 decibel, the slope of the gain falls within a range of -20 dB/decade to _4 〇 decibel/decade, and The phase margin of the conversion function is greater than the ) degree). Preferably, the maximum gain of the amplifying unit W falls within a range of 30 dB 1 50 mutex, and the frequency of the generated pole falls within a range of 1/5 to 1/2 of the system frequency. Referring to Figure 3, Figure 4 and Figure 5, when the capacitor 24 is a multi-layer ceramic, it has a small equivalent series resistance (usually equivalent strings of other types of capacitors such as 1/1 of the resistor). In the following, the frequency of the zero point generated by the capacitor 24 and its equivalent series resistance will be much larger than the frequency of the pole generated by the inductor 23 and the capacitor 24. As is well known, the DC-to-DC power conversion system is unstable. At this time, a capacitor (not shown in FIG. 5) may be connected in parallel with the first resistor 12 200828753 311 of the voltage dividing unit 31 to generate a zero point, and the frequency of the zero point is set to fall on the inductor 23 and The frequency of the pole generated by the capacitor 24 and the frequency of the zero generated by the capacitor 24 and its equivalent series resistance. Preferably, the frequency of the zero point is set to be the same as the frequency of the pole generated by the inductor 23 and the capacitor 24. It should be noted that, in this embodiment, the DC to DC power conversion system is a Buck conversion system, but may also be a Boost conversion system, an Inverting conversion system, A Buck-Boost conversion system, a Cuk conversion system, a Single-Ended Primary Inductance Converter (SEPIC), a Zeta conversion system, and a return A flyback conversion system or a forward conversion system is not limited thereto, as long as the switching conversion unit 2 includes at least one inductor and at least one capacitor. In this embodiment, the amplifying unit 32 of the compensating unit 3 is implemented by means of a conducting amplifier, but can also be implemented in other ways. The compensation unit 3 may not include the voltage dividing unit 31. At this time, the output DC voltage is the same as the reference voltage. In summary, the present invention performs frequency compensation by reducing the maximum gain of the amplifying unit 32 of the compensation unit 3 to increase the frequency of the poles it generates. No additional capacitance is required, and the conventional type-frequency compensation method The first capacitor 14 is used, and when the capacitor 24 is a multilayer ceramic capacitor, the present invention only needs to connect a capacitor in parallel with the first resistor 311 of the voltage dividing unit 31, and the conventional type. The third frequency compensation method requires the use of the 13th 200828753 one to the third capacitors 14, 16, 17. mLL 丄々 ' Therefore, the present invention can indeed achieve the purpose of reducing the number of capacitors. However, the above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent change and repair of the patent application scope and the description of the invention. It is within the scope of the patent of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit block diagram of a conventional DC-to-DC power conversion system; FIG. 2 is a circuit diagram illustrating a frequency used by a compensation unit of the conventional DC-to-DC power conversion system. 3 is a circuit block diagram of a preferred embodiment of the DC to DC power conversion system of the present invention; FIG. 4 is a circuit diagram of a switching conversion unit of the preferred embodiment; Figure 6 is a circuit diagram of an amplifying unit of the compensating unit; Figure 7 is a circuit diagram of the amplifying unit; Figure 8 is a frequency response diagram of the amplifying unit; and Figure 9 is an open circuit of the preferred embodiment Frequency response diagram. 14 200828753 [Description of main component symbols] 1..., switching conversion unit 321 21 · · · Switch 322 22· * · Diode 323 23« * * Inductor 324 24 ♦... Capacitor 325 3 Compensation unit 326 31...· Voltage divider unit 4 · 311, · first resistance element 312 · · second resistance 5 · 32 · · · amplification unit amplifier third resistance fourth resistance fifth resistance first buffer second buffer pulse width modulation single load 15