200828024 MIC2006-231 21969twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是關於一種儲存箱體控制系統，且特別是關 於一種顯示硬碟狀態之儲存箱體控制系統與其儲存箱體控 制晶片。 【先前技術】 序列連接 SCCI( serial attached SCCI)是下一代的 SCSI (Small Computer System lmerface)介面，簡稱 SAS，目的 在提升儲存系統的性能、延展性及可靠度，同時提供與大 容量SATA硬碟和雙埠、高性能SAS硬碟的相容性，主要 鎖定=伺服器和工作站市場。隨著對大儲存容量的需求， 伺服器上必須設置多顆硬碟來滿足使用者的需求，因此， ，存箱體處理态（storage enclosure processor，簡稱 SEP)也 就需要更多的I/O接腳來負責顯示硬碟狀態。 f 在傳統技術中，通常使用I/C)擴展晶片，例如 ，05【、VSC056 (Vitesse Semiconductor Corporation 的 品）等來增加可支援的硬碟個數。因此，SEP可經由i/o 曰片來顯不更多硬碟的運作狀態，但是市售的ι/〇擴 二乂為叩貝’且無法依使用者需求來調整功能。 箱體存;體控制晶片’可軸 碟的運作ig。縣儲存紐處理11可顯示更多硬 本發明是在提供-種儲存箱體控制晶片之介面，可利 5 200828024 MIC2006-231 21969twf.doc/006 用複雜可料賴元件來實雜存難 以降低儲存紐控㈣統的料成本。㈤ 此’ 程式㈣嶋統’利用複雜可 多個硬==存相趙處理器的ι/〇功能，以顯示 f 制系ί達目的本發明提出一種儲存箱體控 體處理哭）體控制系統包括處理器（例如儲存箱 ==;，上述多個硬碟置 號，a中，；板間，用以控制背板上之燈 八中處理讀由儲存箱體控制晶片調整 燈號’以顯示硬碟之運作狀態 i述储存箱體控制晶片可由-複雜可^邏^^ 與輸出-確認信#，以_^片之弟—接腳’用以接收 腳，用以接收判之設置狀態；第二接 制晶片之讀U::號，以判別外界裝置對健存箱體控 個第三接腳了二接=界襄置可為儲存箱體處理器；多 制信號，多個第四接腳’用以接收燈號控 調整多個燈號之顯與燈號控制信號 在本發明另t 述碟的運作狀態。 Λ ^ ，上述儲存箱體控制晶片包括 6 200828024 MIC2006-231 21969twf.doc/006 -第五接腳，用以接收—預置錢，上雜存箱體控制晶 片根據預置信號’依序致能硬碟之馬達；多個致能接腳， 用以依序致能上述多個硬碟之馬達；第六接腳，用以輸出 儲存箱體控制晶片之狀態資料；多個第七接腳，用以偵測 硬碟的設置狀級碟為-對―；以及多個第八接腳，用以 調整多個燈號之顯示狀態來表示硬碟的設置狀態。 本發明因訂定-種儲存箱體控制晶片之介面，因此可 (，獅可料賴元件來縣料箱體處理调1/0功 能，使儲存箱體處理器可顯示更多硬碟的運作狀態，同時 降低儲存箱體控制系統的設計成本。 -為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂’下文特舉本發明之較佳實施例，並配合所附圖式， 作洋細彡兄明如下。 【實施方式】 圖1為根據本發明一實施之儲存箱體控制系統之方塊 I 圖。儲存箱體控制系統100包括處理器110、儲存箱體控 制晶片120以及背板130，其中處理器11〇可為儲存箱體 處理器或是負責儲存箱體控制的處理器，而背板130則用 以設置多個硬碟。儲存箱體控制晶片120耦接在處理器110 與背板130之間，用以控制背板13〇上的燈號131二139 =燈號^41〜149,以顯示背板130上之硬碟的運作狀態或 設置狀態，而背板13〇上的燈號131〜139燈號丨41〜M3 可分別由一個或多個發光二極體（Light Emitting Diode， LED)所構成。硬碟控制器14〇耦接於處理器ιι〇與背板 7 200828024 MIC2006-231 21969twf.doc/006 =ΪΓ，處理器n〇可經由硬碟控制器⑽控 =更碟的’例如讀g#料，亦可直 ㈣得硬碟的運作狀態。在本發明另—實施 相體控制系統100可支援SAS介面，因 裝多= SAS硬碟，而硬碟控制器14〇則可控制SAS^^ /=碟運作狀態的觸，處理器i 硬碑 系統得知，然後再經由儲存_^^^ 武9且^ 131〜139的顯不狀態，例如閃爍、亮、不亮 的組合#。使时便可經由域⑶〜139 去判斷目前各個硬碟的運作狀態。而背板130 可偵測各個硬碟是否設置於背板13G上後 趣㈣12G，_體控制2 狀氣Γ。ϋ 141〜149的顯示狀態來顯示硬碟的設置 表二祕’每一個硬碟對應於兩個燈號’分別 ‘廊於二°又置狀悲與運作狀態，例如以燈號131、141 二二個硬碟。而在本發明另—實施例中，亦可以同 ;ΐ=種顯示，例如閃爍的頻率）來表示硬碟的 、=U作狀悲’此皆為本發明之應用此不 迷0 ，下來二進-步祝明儲存箱體控制晶片㈣的相關介 以及處理器⑽與儲存箱體控制晶片UG之間的溝 ^之L獅Ξ2秘據本發明另—實施例之儲存箱體控制晶 門'。其巾’處理11 11G與贿箱體控制晶片120 a P用11根接腳作為信號的溝通，而背板130無存 200828024 MIC2006-231 21969twf.doc/006 箱體控制晶f 12G之間所利用的接腳數則根據硬碟數目與 所顯不的燈號數目而有所調整。 ’、 π處理器110與儲存箱體控制晶y m之間所傳遞的信 號包括確認信號STRB、讀寫信號R/w、目標信號丁从、 =控制信號口MODE、預置信號PRE以及狀態:身二說。 ”中，由處理H 110輸出讀寫信號卿 f200828024 MIC2006-231 21969twf.doc/006 IX. Description of the Invention: [Technical Field] The present invention relates to a storage box control system, and more particularly to a storage box control system for displaying a hard disk state and a storage box thereof The body controls the wafer. [Prior Art] Serial Attached SCCI (Serial Attached SCCI) is the next-generation SCSI (Small Computer System lmerface) interface, referred to as SAS, which aims to improve the performance, scalability and reliability of storage systems while providing high-capacity SATA hard drives. Compatibility with dual-port, high-performance SAS hard drives, mainly locked = server and workstation market. With the demand for large storage capacity, a number of hard disks must be set on the server to meet the needs of users. Therefore, the storage enclosure processor (SEP) requires more I/O. The pin is responsible for displaying the status of the hard disk. f In the conventional technology, an I/C) extension chip is usually used, for example, 05 [, VSC056 (product of Vitesse Semiconductor Corporation), etc. to increase the number of hard disks that can be supported. Therefore, SEP can display the operating status of more hard disks via i/o cymbals, but the commercially available ι/〇 乂 乂 is a mussel and cannot be adjusted according to user needs. The box is stored; the body control chip' can operate as an axis. County storage processing 11 can show more hard. The invention is in the provision of a storage box control chip interface, can be 5 200828024 MIC2006-231 21969twf.doc/006 It is difficult to reduce storage with complicated and measurable components New control (four) unified material costs. (5) This 'program (four) system' utilizes the ι/〇 function of complex multiple hard == phase-preserving processor to display the f system. The present invention proposes a storage box control body to process the crying body control system. Including a processor (such as storage box ==;, the above multiple hard disk number, a,; between the boards, to control the light on the back panel, the processing read by the storage box to control the wafer to adjust the light number' to display The operation state of the hard disk is described in the storage box control chip, which can be used to receive the set state by using the -complex and the output-confirmation letter #, and the _^---- The second U-shaped chip reads the U:: number to determine that the external device controls the third pin of the storage box to be connected to the second device. The boundary device can be a storage box processor; the multi-system signal, multiple fourth The pin 'is used to receive the lamp number to adjust the display signal of the plurality of lights and the signal control signal in the operation state of the present invention. Λ ^ , the above storage box control chip includes 6 200828024 MIC2006-231 21969twf.doc /006 - The fifth pin is used to receive - preset money, and the memory on the storage box is controlled according to the preset No. 'Sequentially enable the motor of the hard disk; a plurality of enabling pins for sequentially driving the motors of the plurality of hard disks; and a sixth pin for outputting the state information of the storage box control chip; The seventh pin is configured to detect that the set-level disc of the hard disk is -pair-; and the plurality of eighth pins are used to adjust the display state of the plurality of lights to indicate the setting state of the hard disk. Because the setting of the storage box controls the interface of the chip, the lion can expect the component to process the 1/0 function, so that the storage box processor can display more operating states of the hard disk. The above-described and other objects, features and advantages of the present invention will become more apparent and obvious <RTIgt; BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a storage cabinet control system in accordance with an embodiment of the present invention. The storage enclosure control system 100 includes a processor 110, a storage enclosure control wafer 120, and a backplane. 130, wherein the processor 11 〇 can be a storage box The processor is responsible for storing the control of the cabinet, and the backplane 130 is configured to set a plurality of hard disks. The storage box control chip 120 is coupled between the processor 110 and the backplane 130 for controlling the backplane. 13 〇 on the 131 139 = light number ^ 41 ~ 149, to display the operating state or setting state of the hard disk on the back plate 130, and the light on the back plate 13 131 131 ~ 139 lights 丨 41 ~ The M3 can be composed of one or more Light Emitting Diodes (LEDs) respectively. The hard disk controller 14 is coupled to the processor ιι〇 and the backplane 7 200828024 MIC2006-231 21969twf.doc/006=ΪΓ The processor n〇 can be controlled by the hard disk controller (10) = the other disc's 'for example, reading the g# material, or the direct (four) hard disk operating state. In the present invention, the implementation of the phase control system 100 can support the SAS interface, because the multi-=SAS hard disk, and the hard disk controller 14 can control the touch of the SAS^^ /= disk operating state, the processor i hard monument The system knows, and then stores the _^^^^9 and ^131~139 display states, such as a combination of blinking, bright, and non-bright #. The time zone (3) ~ 139 can be used to judge the current operating status of each hard disk. The backplane 130 can detect whether each hard disk is disposed on the backboard 13G. (4) 12G, _ body control 2 shaped air. ϋ 141~149 display status to display the hard disk setting table second secret 'Every hard disk corresponds to two lights 'respectively' porch in two degrees and set the sad and operational state, for example, with the lights 131, 141 two Two hard drives. In another embodiment of the present invention, the same can be used; ΐ = kind of display, such as the frequency of flashing) to represent the hard disk, = U is sorrowful, which is the application of the present invention. The step of the storage box control wafer (4) and the gap between the processor (10) and the storage box control chip UG. The storage box control gate of the present invention. . The towel 'process 11 11G and the brigade body control chip 120 a P use 11 pins as the signal communication, while the back plate 130 does not exist 200828024 MIC2006-231 21969twf.doc/006 box control crystal f 12G The number of pins is adjusted according to the number of hard disks and the number of displayed lights. ', the signal transmitted between the π processor 110 and the storage box control crystal ym includes the confirmation signal STRB, the read/write signal R/w, the target signal Ding, the = control signal port MODE, the preset signal PRE and the state: Second said. ", by processing H 110 output read and write signal f
===''預置信號pre至健耗:2希:片 片12〇雔咖^由處理器110與儲存箱體控制晶 片120雙方依時間區隔而共用，狀 體控制晶；ί 12〇輸出至處理器⑽。 難儲存相 资Ϊ本實施财’接腳Pl負責傳輸確認信號STRB，確 Γ Ϊ S™則用來確認硬碟是否設置於背板130上。當 二理，11。輸出確認信號8咖至儲存箱體控制晶片⑽ ^4^1 110(falling edge trigger) 存箱體控制“，此時，其確認信號strb的致能 f大約在14Gns至35Gns之間。當儲存箱體控制晶片12〇 ^確郝號STRB至處理器110時，儲存箱體控制晶片 以控制負緣_長短的方式來觸發處理器iiq，此時， ”續認信號STRB的致能_大約在·ns〜·仍之間。 接聊P2/i丨貞責接收讀冑錢R/w，齡箱體控制晶 乂 2〇經由讀寫信號廳的邏輯狀態來觸處理器11〇目 二對儲存f體控制；12。是在崎讀取動作或是寫入動 (例如高賴雜表賴取’低邏輯準位麵寫入）。 接腳P3〜P7則用以接收目標信號TAR，以選擇硬碟 9 200828024 MIC2006-231 21969twf.doc/006 其中之—目標硬碟，處理器lio會經由目標信號TAR告知 儲存箱體控制晶片120，目前所處理的目標硬樓為哪一 個。在本實施例中，由於接腳P3〜P7的邏輯狀態組合有 32種，即2的5次方，因此最高可支援32個硬碟。換言 之，儲存箱體控制晶片120可根據該目標信號TAR之數值 以選擇所設置的硬碟其中之一並執行相對應的動作（例如 燈號的顯示與硬碟馬達的啟動）。。當然，在本發明另一 ( 貝把例中，儲存相體控制晶片120可根據使用需求增加或 減乂接收目；號TAR的腳數，以符合所需連接的硬碟個 數。 接腳P8、P9則用以接收燈號控制信號MODE，以調整 垃號之頒示狀態，不同的燈號狀態對應於不同的硬碟狀 恶。由於接腳Ps、P9的邏輯狀態組合有4種，因此，可分 別表示四種顯示狀態，例如亮、不亮、閃爍等。配合目標 仏5虎TAR與燈號控制信號M〇DE，儲存箱體控制晶片12〇 便可得知目前需要調整哪一個燈號的顯示狀態，不同的燈 號則為對應於不同的目標硬碟。若需表示更多的顯示狀 態，則可設置更多的接腳來接收燈號控制信號]^〇〇£。在 本實施例中，每一個硬碟對應於兩個燈號，其中一個燈號 根據燈號控制信號MODE來顯示硬碟的運作狀態，另一個 燈號則用來顯示硬碟是否設置於背板13〇上，此燈號可直 接根據背板130所回傳的信號來顯示硬碟的設置狀態。 接腳P1()則用以接收預置信號PRE，儲存箱體控制晶 片120根據預置信號pre，依序致能硬碟之馬達。在本實 200828024 MIC2006-231 21969twf.doc/006 W列中’儲存箱體控制晶片㈣利用接腳以〜心輸出硬 碟預置k號HPRE來依序致能硬碟的馬達。若以連接24 2硬碟為例，則每—個接腳負責6個馬達，當然亦可依照 設計需求，適當調整各個接腳所負責的硬碟數目或是負責 致能硬碟的接腳數，而接腳Pu〜PH致能的相隔時間則可 依不同系統而定。因此，處理器110只要致能預置信號 PRE，儲存鈿體控制晶片12〇便會依序致能背板13〇上的 (] 硬碟’以避免同時啟動硬碟馬達而造成祕電源貞載過重。 此接腳？15為測試接腳，處理器110可透過接腳p15 取得儲存箱體控制晶片12〇的測試狀態資料p〇j2以確認 儲存箱體控制晶片120是否正常運作。 敫接腳PN+1〜P2N則用以偵測硬碟的設置狀態，N為正 正數，接腳Pn+1〜P2n與硬碟為一對一。背板130會根據 硬碟的設置與否，輸出偵測信號SAS_IN至接腳〜 P、2NJw儲存箱體控制晶片便根據接腳PN+1〜P2N所接收 L 的信旎，以燈號顯示各個硬碟的設置狀態，例如燈號亮表===''Preset signal pre to health consumption: 2: The slice 12 is controlled by the processor 110 and the storage box control chip 120 according to time division, and the shape control crystal; 〇 12〇 Output to the processor (10). Difficult to store the capital Ϊ 实施 ’ ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' When the second, 11,. The output confirmation signal 8 is sent to the storage box control chip (10) ^4^1 110 (falling edge trigger) storage box control ", at this time, the enable signal f of the confirmation signal strb is between 14Gns and 35Gns. When the storage box When the volume control chip 12 is confirmed to be the STRB to the processor 110, the storage box control chip triggers the processor iiq by controlling the negative edge length and length, and at this time, the enablement signal STRB is enabled. Ns ~ · still between. Chatting with P2/i is responsible for receiving and reading money R/w, the age of the box control crystal 乂 2 触 via the logic state of the read and write signal hall to touch the processor 11 attention two pairs of storage f body control; It is a reading operation or a write operation in Saki (for example, a high-reliability table). The pins P3 P P7 are used to receive the target signal TAR to select the hard disk 9 200828024 MIC2006-231 21969twf.doc/006, wherein the target hard disk, the processor lio will inform the storage box control chip 120 via the target signal TAR, Which of the target hard buildings currently being processed is. In the present embodiment, since 32 logical types of pins P3 to P7 are combined, that is, 2 to the 5th power, 32 hard disks can be supported at the maximum. In other words, the storage case control wafer 120 can select one of the set hard disks and perform a corresponding action (e.g., display of the light number and activation of the hard disk motor) according to the value of the target signal TAR. . Of course, in another example of the present invention, the storage phase control wafer 120 can increase or decrease the number of pins of the TAR according to the usage requirement to match the number of hard disks to be connected. Pin P8 P9 is used to receive the signal control signal MODE to adjust the status of the number of the number. The different status of the light corresponds to different hard disk. Because there are 4 combinations of logic states of the pins Ps and P9, It can respectively indicate four display states, such as bright, no light, blinking, etc. With the target 虎5 tiger TAR and the light control signal M〇DE, the storage box control chip 12〇 can know which lamp needs to be adjusted currently. The display status of the number, the different lights are corresponding to different target hard disks. If you need to display more display status, you can set more pins to receive the signal control signal]^〇〇£. In the embodiment, each hard disk corresponds to two light numbers, one of which lights the operating state of the hard disk according to the light control signal MODE, and the other light is used to indicate whether the hard disk is set on the back plate 13〇 On, this light can be directly based on the backplane 130 The returned signal indicates the setting state of the hard disk. The pin P1() is used to receive the preset signal PRE, and the storage box control chip 120 sequentially drives the motor of the hard disk according to the preset signal pre.实200828024 MIC2006-231 21969twf.doc/006 W column 'storage box control chip (four) use the pin to output the hard disk preset k number HPRE to sequentially enable the hard disk motor. If connected 24 2 hard For example, in the case of a disc, each of the pins is responsible for 6 motors. Of course, according to the design requirements, the number of hard disks that each pin is responsible for or the number of pins responsible for enabling the hard disk can be appropriately adjusted, and the pin Pu~ The PH-enabled interval can be determined by different systems. Therefore, as long as the processor 110 enables the preset signal PRE, the memory control chip 12 will sequentially enable the hard disk on the backplane 13 'To avoid starting the hard disk motor at the same time, causing the secret power supply to be overloaded. This pin 15 is a test pin, and the processor 110 can obtain the test status data p〇j2 of the storage case control chip 12 through the pin p15. Confirm that the storage box control wafer 120 is operating normally. 敫 Pin PN+1~P2 N is used to detect the setting state of the hard disk, N is a positive number, and the pins Pn+1~P2n are one-to-one with the hard disk. The backplane 130 outputs the detection signal SAS_IN according to the setting of the hard disk. Pins ~ P, 2NJw storage box control chip will display the status of each hard disk according to the signal received by the pin PN+1~P2N, such as the light number
示，確"又置，燈號不亮表示未正確設置或尚未設置，而儲 存箱體控制晶片120可經由接腳ρ3Ν+ι〜ρ4Ν來控制上述燈 號的顯示狀態，其輸出的控制信號則統稱為設置信號 SAS—ON ’如圖2所示。接腳ρΝ+ι〜p2N與接腳？細〜p4N 的數目則依照硬碟的數目而定，在本實施例中為一對一。 另外，接腳ρΖΝ+1〜pSN則可用來控制其他的燈號，例 如表示硬碟運作狀態的燈號131〜139，在本實施例中調整 燈號131〜139顯示狀態的信號統稱為運作信號 11 200828024 MIC2006-231 21969twf.doc/006If the indicator is not lit, it means that the light is not set correctly or has not been set yet, and the storage box control chip 120 can control the display state of the above-mentioned light source via the pin ρ3Ν+ι~ρ4Ν, and the output control signal thereof It is collectively referred to as the setting signal SAS_ON' as shown in FIG. 2. Pin ρΝ+ι~p2N and pin? The number of fine ~ p4N depends on the number of hard disks, which is one-to-one in this embodiment. In addition, the pins ρΖΝ+1~pSN can be used to control other lights, for example, the lights 131 to 139 indicating the operating state of the hard disk. In the present embodiment, the signals for adjusting the display states of the lights 131 to 139 are collectively referred to as operation signals. 11 200828024 MIC2006-231 21969twf.doc/006
BAY FAULT —而/用的接腳數目可依照設計需长执 疋。而關於儲存箱體控制晶片 :求6又 J ϋϊ 電源接腳，接地接腳等則不在此 腳Γ"-、θ域中’館存箱體控制晶片120以4Ν個接 =為例說明’但本發明並不限定其晶片上之接腳數目，上 f i:以功能介面之接腳數目或位置，均可作適當的 調正，在本技術領域具有通常知識者，經由本發明之揭露 應可輕易推知，在此不加累述。 ^ 在本發明另-實施例中，根據上述圖2之說明，可由 一複雜可程式邏輯元件（嶋plex pn)grammaWe _ devlce，CPLD)來實現本發明之儲存箱體控制晶片。圖3 為根據本發明另一實施例之複雜可程式邏輯元件之接腳 圖。在本實施例中以Xilinx XC128系列的cpLD為例說明 本發明如何以CPLD實現儲存箱體控制晶片之介面。圖3 (a)〜(c)分別摞示CPLD的各接腳所負責的介面功能。 請同時參照圖3(a)〜⑻。接腳I/Q94〜98、1〇〇〜113、115 〜125用以接收來至背板的偵測信號SAS匕IN〜 SAS24—IN’其中偵測信號SAS1 一IN〜SAS24—IN分別於24 個硬碟的設置狀態，也就是反應出24個硬碟是否正確設置 於背板上。而CPLD根據偵測信號SASlJN〜SAS24JN， 輸出設置信號SAS1 一ON〜SAS24—ON以將硬碟的設置狀 態顯示於燈號上（例如亮表示正確設置，不亮表示未正確 設置），其中設置信號SAS1_0N〜SAS24J3N則由接腳 1/02〜7、9〜21、22〜24、129〜130戶斤負責輸出，每一個 12 200828024 MIC2006-231 21969twf.doc/006 接腳負責調整一個燈號，每一個燈號對應於一個硬碟的設 置狀態。 此外，接腳1/070則用以接收確認信號strb，接腳 1/071則用以接收讀寫信號R/w。接腳1/〇74、76則用以 接收燈號控制信號MODE1、2，所以相對應的燈號可以有 四種顯示狀態的變化。接腳1/077〜81用以接收目標信號 TARO〜4 ’利用目標信號TARO〜4的邏輯組合，例如其數 ( 值，农多可標識32個硬碟，在本實施例中則僅使用其中 24個數值來標識24的硬碟，被選擇到的硬碟則可稱為目 才示硬碟。若需標識更多硬碟，可依設計需求增加目標信號 的位元數以及所接收的接腳數目。預置信號pRE則由接腳 1/087所接收，當預置信號PRE致能時，CPLD則經由接 腳1/081〜83、85、86輸出硬碟預置信號HPRE1〜HPRE4， 其中每一個硬碟預置信號負責致能6個硬碟，並以時間間 隔方式依序致能硬碟的馬達。BAY FAULT—The number of pins used and/or used can be as long as the design is required. Regarding the storage box control chip: 6 and J ϋϊ power pins, ground pins, etc. are not in this ankle "-, θ domain 'storage box control chip 120 with 4Ν connection = as an example] The present invention is not limited to the number of pins on the wafer. The upper fi: the number or position of the pins of the functional interface can be properly adjusted. Those skilled in the art can disclose the disclosure of the present invention. It is easy to infer that there is no mention here. In another embodiment of the present invention, the storage case control wafer of the present invention can be implemented by a complex programmable logic element (嶋plex pn) grammaWe _ devlce, CPLD, according to the description of Fig. 2 above. 3 is a pin diagram of a complex programmable logic element in accordance with another embodiment of the present invention. In this embodiment, the cpLD of the Xilinx XC128 series is taken as an example to illustrate how the present invention implements the interface of the storage box control chip with the CPLD. Figures 3(a) to (c) show the interface functions that each pin of the CPLD is responsible for. Please refer to FIG. 3(a) to (8) at the same time. Pins I/Q94~98, 1〇〇~113, 115~125 are used to receive the detection signals SAS匕IN~ SAS24_IN' to the backplane, wherein the detection signals SAS1_IN~SAS24-IN are respectively 24 The setting status of a hard disk, that is, whether 24 hard disks are correctly set on the backplane. The CPLD outputs a setting signal SAS1_ON~SAS24-ON according to the detection signals SASlJN~SAS24JN to display the setting status of the hard disk on the light (for example, light indicates correct setting, no light indicates incorrect setting), and the setting signal is set. SAS1_0N~SAS24J3N are output by pins 1/02~7, 9~21, 22~24, 129~130 jin, each 12 200828024 MIC2006-231 21969twf.doc/006 pin is responsible for adjusting one light, each A light number corresponds to the setting state of a hard disk. In addition, pin 1/070 is used to receive the acknowledgment signal strb, and pin 1/071 is used to receive the read/write signal R/w. Pins 1/〇74 and 76 are used to receive the lamp number control signals MODE1 and 2, so the corresponding lamp number can be changed in four display states. Pins 1/077 to 81 are used to receive the target signals TARO~4' using the logical combination of the target signals TARO~4, for example, the number (value, the number of 32 hard disks can be identified, in this embodiment only the use of 24 values to identify the hard disk of 24, the selected hard disk can be called the hard disk. If you need to identify more hard disk, you can increase the number of bits of the target signal and the received interface according to the design requirements. The number of pins. The preset signal pRE is received by the pin 1/087. When the preset signal PRE is enabled, the CPLD outputs the hard disk preset signals HPRE1 to HPRE4 via the pins 1/081 to 83, 85, 86. Each of the hard disk preset signals is responsible for enabling 6 hard disks and sequentially enabling the hard disk motor at intervals.
而關於顯示硬碟運作狀態的運作信號BAY1_FAULT ‘ 〜BAY24—FAULT 則由接腳 1/025、26、28、30、35、39、 40 41、43、45、49〜54、56〜61、68、69 所負責輸出。 CPLD根據目標信號TAR〇〜TAR4與燈號調整信號 M0DE1、2依序調整24個燈號，每一個燈號對應於一個 目標硬碟，用以表示目標硬碟的運作狀態。接腳1/〇91為 測試接腳，用以輸出儲存箱體控制晶片之測試狀態資料 P〇—12，其餘接腳分別為電源接腳、接地接腳或是程式寫 入接腳專’在此不加累述。另由於CPLD的接腳功能可依 13 200828024 MIC2006-231 21969twf.doc/006 又计需求而定，因此本發明並不以圖3實施例之接腳順 序限定本發明之技術手段。 至於背板上用來輔助偵測硬碟狀態與設置狀態的電 路則如圖4與圖5所示，圖4為根據本發明一實施例之硬 碟偵測電路圖，主要是利用硬碟所輸出的設置信號 HDOUT，將其與一預設電壓（電阻R3、R4的分壓）比較 後而輸出偵測k號SAS一IN。因此，比較器41〇的輸出會 奴著硬碟的設置正確與否而改變，儲存箱體控制晶片便可 根據偵測信號SAS—IN去調整燈號的顯示。當然，每一個 «需要配置-組硬碟制電路，其實施細節在此不加累 述。 圖5為根據本發明另一實施例之硬碟馬達致能電路。The operation signals BAY1_FAULT '~BAY24-FAULT for displaying the operating status of the hard disk are connected by pins 1/025, 26, 28, 30, 35, 39, 40 41, 43, 45, 49 to 54, 56 to 61, 68. 69 is responsible for the output. The CPLD sequentially adjusts 24 lights according to the target signals TAR〇~TAR4 and the lamp adjustment signals M0DE1, 2, and each of the lights corresponds to a target hard disk to indicate the operating state of the target hard disk. The pin 1/〇91 is a test pin for outputting the test status data P〇-12 of the storage box control chip, and the remaining pins are respectively a power pin, a ground pin or a program write pin. This is not mentioned. In addition, since the pin function of the CPLD can be determined according to the requirements of the 2008 20082424 MIC2006-231 21969 twf.doc/006, the present invention does not limit the technical means of the present invention in the pin sequence of the embodiment of FIG. As shown in FIG. 4 and FIG. 5, the circuit for assisting in detecting the state of the hard disk and the setting state on the backplane is shown in FIG. 4 and FIG. 5. FIG. 4 is a circuit diagram of the hard disk detection according to an embodiment of the present invention, which mainly uses the output of the hard disk. The setting signal HDOUT is compared with a preset voltage (the voltage division of the resistors R3 and R4), and the output detects the k number SAS-IN. Therefore, the output of the comparator 41〇 is changed depending on whether the hard disk setting is correct or not, and the storage box control chip can adjust the display of the light number according to the detection signal SAS-IN. Of course, every «requires configuration-group hard disk system, the implementation details are not mentioned here. FIG. 5 is a hard disk motor enable circuit in accordance with another embodiment of the present invention.
在圖五實施例中，發光二極體510會在硬碟預置信號HPRE =能時發光，因為當硬碟預置信號HPRE致能時，馬達致 能=號SPIN便隨之致能，相對應的硬碟馬達即開始運轉。 此日守，PNP電晶體B51因馬達致能信號SPIN而關閉，因 此，發光二極體510與電阻R8、R9形成新的導通路徑而 產生發光所需的電流。利用圖5之電路則可直接由背板產 生可供辨識的燈號，直接判斷硬碟的馬達是否已妳開始運 轉。 、二 本叙明因§丁定一種儲存箱體控制晶片之介面，因此可 =用複雜可程式邏輯元件來擴充儲存箱體處理器的"〇功 能，使儲存箱體處理器可顯示更多硬碟的運作狀態，同時 降低儲存箱體控制系統的設計成本。 14 200828024 MIC2006-231 21969twf.doc/006 雖然本發明已以較佳實施例揭露如上，麸 限定本發明，任何技術領域具有通常知^亚非用以 離本發明之精神和範圍内，t可作些 =’ ^不脫 =發明之保護範圍當視後附之申請專利= 【圖式簡單說明】In the embodiment of FIG. 5, the LED 510 emits light when the hard disk preset signal HPRE= can be enabled, because when the hard disk preset signal HPRE is enabled, the motor enable=SPIN is enabled. The corresponding hard disk motor starts to run. At this time, the PNP transistor B51 is turned off by the motor enable signal SPIN, so that the light-emitting diode 510 forms a new conduction path with the resistors R8 and R9 to generate a current required for light emission. Using the circuit of Figure 5, the identification lamp can be generated directly from the backplane to directly determine whether the motor of the hard disk has started running. The second description is based on § Dingding a storage box to control the interface of the chip, so you can use the complex programmable logic components to expand the storage box processor's "〇 function, so that the storage box processor can display more The operating state of the hard disk while reducing the design cost of the storage box control system. 14 200828024 MIC2006-231 21969 twf.doc/006 Although the invention has been disclosed in the preferred embodiments as above, the bran defines the invention, and any technical field is generally known to be within the spirit and scope of the invention. Some = ' ^ 不 off = the scope of protection of the invention when attached to the patent application = [simplified description]
圖。圖1為根據本發明-實施之儲存箱體控制系統之方塊 接聊^為根據本發明另—實施例之儲存箱體控制晶片之 之接=為根據本發明另—實施例之複雜可程式邏輯元件 圖4為根據本發明一實施例之硬碟偵測電路圖 圖5為根據本發明實施例之硬碟馬達致能電路 【主要元件符號說明】 100 :儲存箱體控制系統 110 :處理器 130 =背板 120 :儲存箱體控制晶片 130〜139、141 〜149 :燈號 140 :硬碟控制器 51〇 :發光二極體 41〇 :比較器 STRB :確認信號 15 200828024 MIC2006-231 21969twf.doc/006 R/W :讀寫信號、 TAR、TARO〜4 :目標信號 MODE、MODE1、2 :燈號控制信號 PRE :預置信號 HPRE、HPRE1〜HPRE4 :硬碟預置信號 P0_12 :測試狀態資料 BAY_FAULT :運作信號 BAY1JFAULT 〜BAY24_FAULT ·•運作信號 SAS_ON、SAS1_IN〜SAS24_IN :設置信號 SAS_IN、SAS1_IN〜SAS24_IN :偵測信號 HDOUT :設置信號 SPIN :馬達致能信號Figure. 1 is a block diagram of a storage box control system in accordance with the present invention - a storage box control chip according to another embodiment of the present invention = a complex programmable logic according to another embodiment of the present invention FIG. 4 is a diagram showing a hard disk detecting circuit according to an embodiment of the present invention. FIG. 5 is a hard disk motor enabling circuit according to an embodiment of the present invention. [Main component symbol description] 100: Storage box control system 110: Processor 130 = Backplane 120: storage case control wafer 130~139, 141~149: lamp number 140: hard disk controller 51〇: light emitting diode 41〇: comparator STRB: confirmation signal 15 200828024 MIC2006-231 21969twf.doc/ 006 R/W : Read/write signal, TAR, TARO~4: Target signal MODE, MODE1, 2: Signal control signal PRE: Preset signal HPRE, HPRE1~HPRE4: Hard disk preset signal P0_12: Test status data BAY_FAULT: Operation signal BAY1JFAULT ~ BAY24_FAULT ·• Operation signal SAS_ON, SAS1_IN~SAS24_IN: Set signal SAS_IN, SAS1_IN~SAS24_IN: Detection signal HDOUT: Set signal SPIN: Motor enable signal
Pi〜P4N、1/02〜I/O 140 :接腳 B51 : PNP電晶體 R1〜R9 :電阻 M51 : NMOS電晶體 C卜C2 :電容 VCC :工作電壓 GND :接地端 16Pi~P4N, 1/02~I/O 140: Pin B51: PNP transistor R1~R9: Resistor M51: NMOS transistor CbC2: Capacitor VCC: Operating voltage GND: Ground terminal 16