TW200826449A - DC-DC converter and related control apparatus and signal generating method - Google Patents

Abstract

A pulse width modulated pulse signal is generated and its duty cycle adjusted according to at least two different schedules, for example, a coarse tuning cycle and a fine tuning cycle. The target duty cycle is derived according to an offset between output voltage and target voltage, as well as the rate of changes in the offset. In the coarse tuning cycle, large changes in the control signal pulse width is used to derive output voltage to target voltage at a fast pace. As output voltage approaches target voltage, smaller adjustment are made to the duty cycle of the control pulse width in the fine tuning cycle. The rate of pulse width change is also taken into consideration, to further improve operation of the DC-DC converter.

Description

200826449 IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit, and more particularly to a method and apparatus for controlling a DC-DC converter for supplying power to various electronic and telephone devices . [Prior Art] f Fig. 1 shows a simplified circuit diagram of a conventional DC-to-DC converter 10Θ, in which a DC-to-DC converter 1〇〇 can generate an output voltage greater or lower than an input voltage. This DC converter is often very useful in electronic or telephony applications. The output voltage can be adjusted according to the duty cycle of a switching transistor 12 。. A brief description of the general operation of the converter is as follows. When the transistor 120 is in the on (0N) state, the input voltage source vcc 115 is directly coupled to the inductor 130, accumulating energy in the inductor 130. At this stage, capacitor 150 supplies energy to an output negative C carrier connected to v〇UT 145. When the transistor 120 is in the OFF state, the inductor 130 is coupled to the capacitor 150 and an output such that energy is transferred from the inductor 13 to the valley 150 and the output 145. The magnitude of the output voltage is determined by the ratio of the pulse width modulation (PWM) control signal 125 on/off time, or the duty cycle. In a DC-to-DC converter related application, a feedback control loop can be included to cause the converter output to follow a predetermined reference voltage. In such applications, an error signal is first generated to indicate the output voltage and the offset between the target voltages. Then, this error signal was taken

Client's Docket N〇.:95U003 TT's Docket No:0492-A40929-TW/Final/Jasonkung f 200826449 Compare with a two-wave or sawtooth signal to generate a pwM control signal that can be used to control a switch A device, such as a transistor 120 in the drawing. The transistor 12 is calibrated to a predetermined voltage level based on the pWM signal. In a digital PWM, a control signal having a duty cycle ratio is generated based on a voltage difference between an output voltage and a target input voltage. - The digital waveform produces H and is then pulsed to produce a PWM signal having a duty cycle determined by the control signal. Similarly, a digitalized two-corner waveform can be used to compare with a digitized output voltage to produce a digital PWM Ifl number. Although successful, the conventional digital pWM converter has also suffered from specific drawbacks. The DC-to-DC converters of the conventional digital pWM are increasingly facing limited accuracy problems because the interval of the adjustment time is limited by the clock frequency and the incremental voltage variation is dominated by the digitalization limit. Furthermore, conventional digital PWM converters tend to have relatively long reaction times, producing buzz (nois e) and output voltage levels that are too high (〇(10)) or undershoot. These shortcomings of the conventional digital pwM converter and other limitations will be further explained in this specification. Therefore, there is a need for an improved technique for controlling a DC-to-DC converter. SUMMARY OF THE INVENTION The present invention provides a PWM signal generated on a DC-to-DC converter and according to at least two different time courses (i.e., a coarse tuning cycle and a fine tuning cycle). And use a variety of threshold values to adjust the technology of its duty cycle. However, worth noting

Client's Docket N〇.: 95U003 TT^s Docket No:0492-A40929-TW/Final/Jasonkung 200826449, the present invention can have a wider range of applications. For example, the present invention can be used in other applications to improve the convergence performance of PWM signals. In one embodiment, the present invention provides a signal generating method for generating a PWM pulse signal to control a DC-DC conversion ◎' including the following steps: providing a -first-frequency-first clock a second pulse pulse signal having a second frequency, wherein the second frequency of the day pulse pulse signal is higher than the first frequency of the first clock pulse signal, providing a pulse width control signal, The pulse width control signal has a predetermined initial value, a voltage difference between one of the DC-to-DC converters and a target voltage, and is obtained from a DC-to-DC converter-feedback measurement. Each cycle of the clock pulse signal (CyCle) performs a coarse adjustment on the pulse width control signal, wherein the coarse adjustment is related to the feedback measurement, and each pulse of the second clock pulse signal is pulsed. The width control signal is subjected to fine adjustment, wherein the fine adjustment system is related to the feedback measurement, and generates a pWM pulse signal having a PWM clock frequency, wherein the For period ㈣⑽) by the pulse width control signal line inhibiting the towel in Example I. embodiment of 'the present invention provides - (iv) DC linear species

An embodiment of the method includes providing a first chirped pulse signal characterized by a first frequency L ^ A hand, providing a second frequency characteristic of a second frequency pulse, wherein the second clock pulse signal is second The frequency #^:: pulse pulse signal system is based on the first frequency of the first hydrazine day at the rushing signal, and is obtained from a DC-to-DC conversion measurement, wherein the feedback measurement system has a DC-to-DC (four) beta voltage and a target. In the voltage difference between the voltages, the pulse is pulsed out.

Client's Docket No.: 95U003 TT^s Docket No:0492-A40929-TW/Final/Jasonkung 200826449 - Perform feedback measurement to generate a pulse width control signal, perform feedback measurement with the second clock pulse to adjust the pulse width control signal Generating a PWM pulse signal, the pulse width of the PWM pulse signal is characterized by a pulse width control signal, applying a PWM pulse signal to one of the DC-to-DC converter output transistor switches, and according to the PWM pulse signal, by using DC The output transistor voltage is turned on or off for the DC converter to generate an output voltage. In still another embodiment, the present invention provides a control device for controlling a DC-to-DC converter, including a first clock generator, a second clock generator, a target signal line, and a An analog to digital converter, a first comparator circuit, a second comparator circuit, a third comparator circuit, and a PWM pulse generator. The first clock generator is configured to generate a first clock pulse signal having a first frequency. The second clock generator is configured to generate a second clock pulse signal having a second frequency, wherein the second frequency of the second clock pulse signal is higher than the first frequency of the first clock pulse signal. The analog-to-digital converter is connected to one of the DC-to-DC converters. The first comparator circuit is coupled to one of the DC-to-DC converter outputs and the target signal line, wherein the first comparator circuit is configured to determine whether the output signal of the DC-to-DC converter exceeds the target signal. The comparator circuit is coupled to the output of the analog-to-digital converter and the target signal line, wherein the second comparator circuit is configured to obtain a bias according to one of the output signals of the analog-to-digital converter and the signal difference between the target signals. The mobile number and an offset ratio signal. The third comparator circuit is coupled to one of the first comparator circuit and one of the second comparator circuits, and the third comparator circuit is

Clienfs Docket No.: 95U003 TT's Docket No:0492-A40929-TW/Final/Jasonkung 200826449 For each clock cycle of each time pulse signal of the first clock pulse signal, according to the low cycle period and the second time The pulse number obtains a pulse width control signal number and a correction ratio signal - a PWM pulse signal, wherein the PWM pulse 11 is generated to generate a punch width control (4). 11 δί1 脉脉敏 is the pulse-re-invention, the invention also provides a PC-DC converter, including - DC to DC converter, - = generator, - second clock generator, - Feedback control circuit, a _: generator, a second signal generator, a & a coupling circuit. The first clock generator uses the -th clock pulse signal and the second clock generator, the second clock pulse signal of the frequency, wherein the second clock pulse = the first frequency is still in the first The first frequency two control circuit of the clock pulse signal is used to obtain the feedback measurement from the DC-to-DC converter according to the voltage difference between the output voltage of the DC-to-money converter and the two target voltages. The first signal generator is configured to use the first clock pulse to return to the town measurement to generate a pulse width control position, and the second signal generation = to perform the feedback measurement using the second clock pulse signal to adjust the pulse; the degree control signal. The pwm pulse generator is used to generate a "pwm pulse", wherein the pulse width of the PWM pulse signal is controlled by the pulse width control %. The coupling circuit is configured to couple the PWM pulse signal to one of the output switches of the DC-DC converter. Many advantages over the prior art can be achieved in accordance with the present invention. The present invention provides a method and apparatus suitable for use with smaller wafer areas, higher

Client's Docket N〇.:95U003 TT,s Docket No:0492-A40929-TW/Final/Jasonkung 9 200826449 One-to-one DC-to-DC conversion with high accuracy, fast response time, and low or low output conditions Device. One or more of the above advantages may be realized in accordance with an embodiment. These and other advantages will be detailed below. The above and other objects, features and advantages of the present invention will become more <RTIgt; [Embodiment] A method according to an embodiment of the invention comprises at least two main parts: for example, a coarse tuning cycle and a fine tuning cycle. During the coarse tuning process, the DC-to-DC converter output voltage is periodically sampled and compared to a predetermined target voltage, and the voltage difference or offset between the two voltages is calculated and used to adjust the PWM control signal. Pulse Width. In one embodiment, to determine the pulse width (interval size) required to drive the output voltage toward the target, the offset voltage is first compared to a predetermined set of threshold voltages. In order to adjust the time, the larger offset is used for larger offsets when the output voltage is far from the target. As the offset becomes smaller, the interval size also decreases to minimize the condition that the level is too high or too low. At this time, when the level is too high or too low, a fine adjustment process will be performed more frequently than the coarse adjustment process. During the trimming process, the target voltage and the output voltage are compared to generate an Up/Down signal to indicate the intersection of the output voltage and the target voltage. When a change in polarity is detected on the up/down signal, the trimming process will be initiated and the PWM control pulse width will be adjusted at a small interval to control the level not too high or too low. Once offset

Clients Docket N〇.:95U003 TT's Docket No:0492-A40929-TW/Final/Jasonkung 10 200826449 Reduce to a given low level and the interval size will drop to 当 when the DC-to-DC output voltage approaches the target voltage. The PWM pulse width will then remain fixed. With the method and apparatus according to embodiments of the present invention, efficient and accurate control of the DC to DC output voltage can be achieved. These and other advantages will be detailed below. For example, Figure 2 shows a simplified schematic diagram of a block diagram of a DC to DC converter in accordance with an embodiment of the present invention. Figure 2 includes a digital PWM pulse generator 200, an analog to digital converter 210, an up-down comparator 220, and a DC-to-DC converter 27A. Among them, the conversion 270 may be a conventional DC-to-DC converter as in the above-mentioned figure. The PWM pulse generator 200 includes a second order comparator 230, a multi-order comparator 240, a pulse width calculator 250, and an N-bit counter 260. The second order comparator 230, the multi-order comparator 240, and the pulse width calculator 250 are driven by a 64 Hz cHz clock 206. The second order comparator 230 and the multi-order comparator 240 also receive clock pulses from the 8 Hz clock 208. The N-bit counter 260 is used to count the number of pulses of the primary clock 202 to control the pwm pulse width. The N-bit counter 260 is also used to determine a minimum unit dD of a PWM pulse width. In addition, dD is also the smallest unit of the PWM pulse control signal Dstep 245 generated by the multi-order comparator 240. In the feedback control loop shown in FIG. 2, the analog output voltage Vout 275 of the DC-to-DC converter 270 is converted to a digital signal Din 215 via an analog-to-digital converter (ADC) 210. The digital signal Din 215 and a predetermined target signal Vtarget 204 are all connected to the second-order comparator

Client’s Docket No. : 95U003 TT^ Docket No: 0492-A40929-TW/Final/Jasonkung 11 200826449 230. Then, an error signal Derror 235 is generated in each clock cycle of the 64 kHz clock 206. As discussed below, the error signal Derr〇r is derived from measuring the offset between Vout 275 and Vtarget 204 and the rate of change between the current and previous day pulses. The up-down comparator 220 receives Vout 275 and Vtarget 204 and generates an up-and-down signal Updown 225' to indicate whether v〇ut 275 has exceeded vtarget 204 when Vout 275 is being adjusted by the PWM pulse. In other words, the up and down signal 225 indicates whether the level is too high or too low. In addition, various signals will be processed further to obtain a PWM control pulse, as discussed below. In Fig. 2, the multi-order comparator 24 generates a pulse width control signal Dstep 245 and an up-and-down signal 225 based on the offset between Vout 275 and vtarget 204 (rate of change of the offset). Pulse width calculator 250 then generates a PWM pulse signal 255 using Dstep 245 and output D0 265 from N-bit counter 260. The PWM pulse signal 255 is coupled to the DC to DC converter 270 to provide an output Vout 275. In a particular embodiment of the invention, PWM pulse signal 255 has a frequency of 64 kHz and the trim adjustment period is also controlled by a 64 kHz clock. During each clock cycle of the 800 Hz clock 208, a new PWM duty cycle will be applied to the DC to DC converter 270. When the output 275 is being adjusted by the PWM pulse, its Pwm duty cycle will be monitored and adjusted during each clock cycle of the 64 kHz clock 206 to determine if a condition is too high or too low. In other words, assuming that V〇ut 275 changes too fast and moves past the target value Vtarget 204, the pulse width adjustment in the next cycle will decrease. In another embodiment of the invention, the fine tuning period

Client's Docket N〇.: 95U003 TT^s Docket No:0492-A40929-TW/Finaiyjasonkung 200826449 Can be driven by a different clock than the pulse generator. And the micro-difficult sequence to make the DC M flow (4) speed up the collection ^ - target setting. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A simplified flow chart according to an embodiment of the present invention will be described in detail. FIG. 3 is a simplified flowchart showing a signal generating method 1 according to the present invention to generate a PWM control signal. In the middle of this method, the method is used to reduce the number of cycles - PWM__ and « at least two different day-to-day adjustments, such as the coarse adjustment period and the - fine adjustment period, to adjust its = / month. The method also includes obtaining an offset of U(4) according to the output electric house circumference (the rate of change of the offset), and making a large change to the control signal pulse width in the (four) cycle to the target. ^_With a fast drive wheel voltage": When the power supply f is close to the target voltage, the duty cycle of the control signal pulse width is slightly adjusted. In addition, the rate of change of the 冲 width of the 夂 is also considered: this example only illustrates the operation of the pulsating converter. According to the present invention, the method and the device for directly applying the method can make the two-DC to the money (four) μ voltage quickly receive (four) a target electricity [sub-and reduce the level is too high or too low) Wave (four) coffee), these waves may produce unwanted delays. These performance improvements can bring additional benefits to the application circuit, such as a drop (four) sound. These and others (iv) please refer to the discussion below on Figure 3. Referring to Figure 3, the coarse adjustment procedure begins in step 31 and in step 33, the - 分支 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋Note that the fine tuning cycle begins at step 360. In an embodiment, in the initial step 31, the specific parameters are set first.

Client’s Docket No. : 95U003 TT^ Docket No:0492-A40929-TW/Final/Jasonkung 200826449 Initial value. As shown, a predetermined preset target duty cycle Dtarget is selected and the parameter Voffse_old is set to zero. In a particular embodiment, the preset Dtarget can be zero. In another embodiment, Dtarget can be set to a predetermined maximum such that the generated PWM can have a 90% or 95% duty cycle. As shown in step 320, the coarse adjustment period is initiated (triggered) by a clock edge of an 800 Hz clock pulse Clk_sh. In one embodiment, at the rising edge of the clock pulse Clk_sh, a new offset signal Voffset_new is obtained from the voltage difference between the target voltage vtarget and the current output voltage Vout. Wherein, Voffset_old is the previous Voffset calculated in a previous clock cycle. At this time, the difference Voffset_diff between the two consecutive offsets Voffset can be calculated by the following formula:

Voffset_diff = Voffset - new_Voffset - old, where Voffset_diff represents the rate at which the change in Voffset is increased and is used in subsequent steps. Next, step 330 is performed to compare the size of Voffset_new with a predetermined maximum offset to determine whether the special boundary condition of the duty cycle control signal Dtarget has been exceeded. For example, assuming Voffset_new &gt; 5 volts, then jump to step 340 and set Dtarget to a predetermined value Dmin. Assuming Voffset_new&lt;-5 volts, Dtarget is set to a predetermined value Dmax, for example, in an embodiment the predetermined value Dmax can be 95%. The picker does not check the rate of change of the offset set Voffset_diff as in step 345. Assuming that the Voffset-diff system is greater than 5 volts, the target duty cycle parameter Dtarget is reduced by a factor of 16 minimum adjustment unit, or

Client’s Docket N〇.: 95U003 TT's Docket No:0492-A40929-TW/Final/Jasonkung 14 200826449 16*dD. Conversely, if Voffset-diff is less than 1 volt, Dtarget will increase by 4 times the dD. The above procedure can be summarized in the following expression: If Voffset_diff> 5 volts

Dtarget=Dtarget-16*dD ; if Voffset_diff&lt;l volts

Dtarget=Dtarget+4*dD 〇 It is worth noting that although specific values are used in this example to illustrate, other close values can be used in different applications. Starting from selection block 330, if Voffset_new is no greater than 5 volts, it indicates that Vout is fairly close to Vtarget, and then step 350 is performed. Voffset_diff will be compared to a set of established threshold values, and depending on the result of the comparison, Dtarget will be adjusted by one of a set of established adjustment values. Since Voffset-diff represents the change in Voffset between two consecutive clock pulses, a large Voffset-diff indicates that Vout is changing rapidly. In order to avoid the level being too high, the pulse width control signal Dtarget will be lowered. Conversely, a small Voffset-diff indicates that Vout is slowly changing. In order to prepare for convergence, the pulse width control signal Dtarget will be reduced by a small amount. Conversely, Dtarget can also be increased by a small amount if needed. The adjustment procedure of step 350 in Fig. 3 can be expressed as the following expression: if Voffset_diff&lt;l volt

Dtarget two Dtarget+4*dD; if Voffset_diff>1 volt

Dtarget=Dtarget_4*dD ; if Voffset diff> 2 volts

Client’s Docket No.: 95U003 TT’s Docket No:0492-A40929-TW/Final/Jasonkung 15 200826449

Dtarget=Dtarget-8*dD ; if Voffset—diff>3 volts

Dtarget:=Dtarget-16*dD; Next, in step 380, a size check is performed to limit the Dtarget between the two predetermined boundary values Dmin and Dmax, which can be expressed as the following expression: If Dtarget&lt;=Dmin, Dtarget=Dmin; fi \ If Dtarget>=Dmax, Dtarget 2 Dmax 〇 Next, in step 390, a PWM pulse is generated according to the clock signal cik. In the rising edge of the clock signal Clk (64 kHz in this example), by setting the pulse width parameter DCDRV to the low level and DCFF to the 鬲 level, after a period of Dtarget*Period time, the pwM signal will drop. Low level (low). Here, the duty cycle control signal Dtarget is used to generate a PWM signal having a selected duty cycle. The DC-to-DC converter uses this duty cycle to modify its output signal V〇ut until a new Dtarget in the next cycle of coarse tuning driven by an 800 Hz clock is calculated. The cross-sectional discussion shows a coarse adjustment procedure for the pulse width control signal Dtarget in accordance with a consistent embodiment of the present invention. In accordance with the present invention, the pulse width control procedure can be improved by -micro-difficulty. Between two weeks ^, when the control signal Dtarget is recalculated, the fine-tuning program monitors Vout to make the control signal Dtarget more frequent and better tuned = as shown in step 360 of Figure 3 The rise of the 64 kHz clock-to-turn ratio is set to its initial value, and the DCDRv is the standard.

Client’s Docket N〇.: 95U003 TT’s Docket No: 〇492-A40929-TW/Final/:Tasonkung 16 200826449, while DCFF is low. The up and down indicators are loaded into Updown_new. Then in step 37, Upd〇wn-new and

Updown-old compares to determine if V〇m has exceeded vtarget. The change of the 'up and down' is shown as a condition for determining whether the level is too high or too low when V〇ut moves toward the Vtarget. Assuming a spanning situation, a fine-tuning procedure 375 will be performed to reduce further drift of V〇ut. In the fine-tuning procedure shown in step 375, v〇ffset_diff will be compared to a set of established threshold values, and depending on the result of the comparison, Dtarget will be adjusted by one of a set of predetermined adjustment values. Since V〇ffset_diff represents the change in V〇ffset between two consecutive clock pulses, a large Voffset-diff indicates that Vout is changing rapidly. To slow the rate of change, the pulse width control signal Dtarget will be reduced. Conversely, a small Voffset-diff indicates that Vout is slowly changing, and the pulse width control signal Dtarget will be reduced by a small amount or Dtarget can be increased by a smaller amount if necessary. This fine-tuning program can be expressed as the following expression: If Voffset__diff&lt;l volts

Dtarget=Dtarget+l*dD ; if Voffset_diff>1 volt

Dtarget=Dtarget-2*dD ; if Voffset_diff> 2 volts

Dtarget = Dtarget - 4 * dD 〇 Next, in step 375, the new Dtarget will be used to generate a PWM pulse in steps 380 and 390, as in the coarse tuning procedure discussed above. As discussed above, coarse tuning procedures and fine tuning in a particular embodiment

Clienfs Docket No.: 95U003 TTys Docket No: 0492-A40929-TW/Final/Jasonkung 17 200826449 The program is periodically performed by clock pulses of frequencies of 800 Hz and 64 kHz, respectively. A pulse width control signal will be monitored and adjusted to produce a PWM with the appropriate duty cycle to drive Vout towards the target value Vtarget quickly, while minimizing the condition that the level is too high or too low. In one embodiment, the target voltage Vtarget in the telephone application is set to -94 volts, which is generated by a DC-to-DC converter from a power supply voltage of about 5 volts to 12 volts. In other applications, embodiments of the present invention are also applicable to various telephone circuits or electronic circuits on mobile applications that may require multiple voltages on the same integrated circuit device. Therefore, the present invention has been described in the above preferred embodiments, and is not intended to limit the invention, and it is possible to make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a conventional DC-to-DC converter. Figure 2 is a simplified schematic diagram showing a DC-to-DC converter functional block in accordance with an embodiment of the present invention. Figure 3 is a simplified flow diagram showing a signal generation method for generating a PWM control signal for a DC-to-DC converter in accordance with an embodiment of the present invention. [Main component symbol description] 100~DC to DC converter; 115~Input voltage source VCC; 120~

Client's Docket N〇.: 95U003 TT's Docket No:0492-A40929-TW/Final/Jasonkung 18 200826449 Transistor; 125~ Pulse Width Modulation Control Signal; 13〇~Inductance; 145~ Output, 150~Capacitor; pwm~ Pulse width modulation; 200~digit PWM pulse generation, 202~main clock; 204~target signal vtarget; 206~64 仟h clock; 208~800 Hz; 210~ analog to digital converter ADC; 220 Up-down comparison, 225~ up and down signal Updown; 230~2 order comparator; 235~ error signal Derror; 240~ multi-order comparator; 245~PWM pulse control signal; 250~ pulse width calculator; 255~PWM pulse Signal; 260~N bit counter; 265~output D0; 270~DC to DC converter; dD~minimum unit; Dstep; 275~ analog output voltage v〇m; Dtarget~target duty cycle; PW~pulse width; ~ main clock cycle time; Clk~PWM clock; Clk-sh~ sample/maintained clock; Vtarget~target output voltage; v〇ffSet~Vtarget and V〇ut difference · DCDRV~ positive control output signal ;DCFF~negative control loss Signal; 3〇〇, 310, ..., 390,345,375~ step.

Client’s Docket No.: 95U003 TT’s Docket No:0492-A40929-TW/Final/Jasonkung 19

Claims (1)

200826449 X. Patent application scope: 1 · A signal generation method for generating a pulse width modulation (PWM) pulse signal for controlling a DC-DC converter, comprising the steps of: providing a first frequency a first clock pulse signal; a second clock pulse signal having a second frequency, wherein the second frequency of the second clock pulse signal is higher than the first clock pulse signal a frequency; providing a pulse width control signal, the pulse width control signal having a predetermined initial value; obtaining a DC-to-DC conversion according to a voltage difference between an output voltage of the DC-to-DC converter and a target voltage One of the feedback measurements; a cycle of the first pulse signal, a coarse adjustment (c〇arse adjustment), wherein the coarse adjustment and the feedback Measure correlation; perform fine adjustment on the pulse width control signal in each cycle of the second clock pulse signal, where The modulation system is related to the feedback measurement; and generating a pulse width modulation pulse signal having a pulse width modulation clock frequency, wherein the duty cycle of the pulse width modulation pulse signal is controlled by the pulse width control signal Controlled. 2. The method of claim 1, wherein the step of obtaining the feedback measurement further comprises the following steps: Client's Docket N〇.: 95U003 TT's Docket No: 0492_A40929-TW/Final/Jasonkung 20 200826449 The 'voltage difference' between one of the DC-to-DC converter output voltage and a target voltage is obtained by an offset signal; and two offset signals in two consecutive clock cycles from the first clock pulse signal The difference between the signals is obtained by the ratio signal. The method of claim 4, wherein the step of performing the coarse adjustment on the pulse width and the signal further comprises the following steps: whether the offset is greater than a predetermined offset limit; And if the offset/offset number is greater than the offset limit value, the step of performing the coarse adjustment on the pulse degree control signal further comprises the following step f: providing a predetermined maximum pulse width signal; comparing the ratio signal to the predetermined ratio of the complex number Threshold value; according to the (four) signal, a first adjustment signal is selected from the first-complex pulse width adjustment nickname; and a pulse width control signal is obtained according to the maximum pulse width and the first-difficult signal; or When the offset signal is equal to or less than the offset limit value, the step of adjusting the pulse width control signal includes the following steps: / self-pre-pulse width modulation clock period to raise the control signal; ^ Comparing the ratio signal and the complex predetermined threshold value, selecting a second adjustment signal according to the ratio signal m; the pulse width adjustment signal; and the basis-pre-pulse When the pulse width modulation cycle of the pulse width control signal and the second adjustment signal, to give - pulse width control signal. Clienfs Docket No.: 95U003 TT's Docket No: 0492-A40929-TW/Final/Jasonkung 21 200826449 4. The method of claim 2, wherein the step of fine-tuning the pulse width control signal further comprises The following steps: determining whether the output voltage of the DC-to-DC converter exceeds the target voltage; if the magnitude of the output voltage of the DC-to-DC converter exceeds the target voltage, the pulse width control signal is performed The step of fine tuning further comprises the steps of: providing a pulse width control signal in a clock cycle from a previous pulse width modulation; comparing the ratio signal to a predetermined threshold value of a third complex number; according to the ratio signal, from the first A third adjustment signal is selected from the plurality of predetermined pulse width adjustment signals; and a pulse width control signal is generated according to the pulse width control signal and the third adjustment signal in the pulse width period of the previous pulse width modulation. 5. The method of claim 1, wherein the step of generating the pulse width modulation pulse signal further comprises the steps of: providing a pulse width modulation clock pulse having a pulse width modulation clock frequency And adjusting a pulse width of the pulse width modulation clock pulse signal, wherein the pulse width of the pulse width modulation clock pulse signal is controlled by the pulse width control signal. 6. The method of claim 1, wherein the first frequency is about 800 Hz. Client's Docket No.: 95U003 TT, s Docket No: 0492-A40929-TW/Final/Jasonkung 22 200826449. The method of claim 1, wherein the second frequency is about 64 kHz. . 8. The method of claim 1, wherein the predetermined initial value of the pulse width control signal is 〇. 9. The method of claim 1, wherein the predetermined initial value of the pulse width control signal is a predetermined maximum signal. 10. The method of claim 1, wherein the pulse width modulated pulse signal has the second frequency 〇H. of the second clock pulse signal. The control direct current to direct current (DC_DC) conversion The method includes the steps of: providing a first clock pulse signal having a first frequency; providing a second clock pulse signal having a second frequency, wherein the second clock pulse signal is The two frequency system is higher than the first frequency of the first clock pulse signal; and the feedback voltage from one of the DC-to-DC converters is obtained according to the output voltage of one of the DC-to-DC converters and the -electric age between the target voltages Performing the feedback measurement by using the first clock pulse signal to generate a pulse width control signal; performing the feedback measurement by using the second clock pulse signal to adjust the pulse width control signal; generating a pulse width modulation pulse signal , wherein the pulse width of the pulse width modulation pulse signal is controlled by the pulse width control signal; Client's Docket No. : 95U003 TT's Docket No:0492-A40929-TW/Final/Jasonkung 23 200826449 Applying the pulse width modulation pulse signal to the DC to DC conversion crying output switch; and modulating the pulse signal according to the pulse width, by using the DC pair The output switch of the DC converter is turned on or off to generate an output voltage. 12. A control device for controlling a DC-DC converter, comprising: a first clock generator for generating a pulse signal having a first frequency; and a second clock generating For generating a first clock pulse signal having a second frequency, wherein the second frequency of the second clock pulse signal is still at the first frequency of the first clock pulse signal; Signal line; a type of analog-to-digital converter, coupled to the DC-DC conversion crying one round -..S . ...; - ._...--_---___----... -......―——.-........————1 .-...-.... ........, two...-... A first comparator circuit, coupled And an output of the DC-to-DC converter and the target signal line, wherein the first comparator circuit is configured to determine whether the output signal of the DC-to-DC converter exceeds the target signal; a second comparator circuit, And coupled to the output of the analog-to-digital converter and the target signal line, wherein the second comparator circuit uses ° to convert one of the analog-to-digital converters a signal difference between the signal signal and the target signal, obtaining an offset signal and an offset ratio signal; a third comparator circuit coupled to the output of the first comparator circuit and the second comparator circuit One output, the third comparator circuit is Client's Docket N〇.: 95U003 Docket No: 0492-A40929-TW/Final/Jasonkung 24 200826449 is used for each clock cycle of the first clock pulse signal and In each clock cycle of the second clock pulse signal, a pulse width control signal is obtained according to the offset signal and the offset ratio signal; and a pulse width modulation pulse generator is used to generate a pulse width modulation The pulse signal, wherein the pulse width of the pulse width modulation pulse signal is controlled by the pulse width control signal. 13. A direct current to direct current (DC-DC) converter comprising: a direct current to direct current converter; a first clock generator for generating a first clock pulse signal having a first frequency; a second clock generator for generating a second clock pulse signal having a second frequency, wherein the second frequency of the second clock pulse signal is higher than the first clock pulse signal a feedback control circuit for obtaining feedback from one of the DC-to-DC converters according to a voltage difference between one of the DC-to-DC converter output voltage and a target voltage; a first signal generator And performing the feedback measurement by using the first clock pulse signal to generate a pulse width control signal; a second signal generator for performing the feedback measurement by using the second clock pulse signal to adjust the pulse width control a pulse width modulation pulse generator for generating a gland width modulation pulse signal, wherein the pulse width of the pulse width modulation pulse signal is controlled by the pulse width Controlled by the signal; and a coupling circuit for coupling the pulse width modulated pulse signal to Clienfs Docket No.: 95U003 TT^ Docket No:0492-A40929-TW/Final/Jasonkung 25 200826449 The DC-to-DC conversion One of the output switches. 14. The DC-to-DC converter of claim 13, wherein the feedback control circuit further comprises: a first feedback comparator circuit for outputting a voltage according to the DC-to-DC converter and a target a voltage difference between the voltages to obtain an offset signal; and a second feedback comparator circuit for determining a signal difference between the two offset signals in the two consecutive clock cycles from the second clock signal , get an offset ratio signal. 15. The DC-to-DC converter of claim 14, wherein the first feedback comparator circuit further comprises: a first comparator for comparing the offset signal with a predetermined offset limit signal; a first selection circuit for selecting a first adjustment signal from a first plurality of predetermined pulse width adjustment signals according to the offset signal; and a signal generator for determining the offset signal and the first adjustment according to the offset signal The signal generates a pulse width control signal. 16. The DC-to-DC converter of claim 14, wherein the second feedback comparator circuit further comprises: a second comparator for determining whether the output voltage of the DC-to-DC converter exceeds the a storage circuit for storing a pulse width control signal in a previous pulse width modulation clock cycle; a second selection circuit for using the offset ratio signal from a first Client's Docket N〇 .:95U003 TT's Docket No:0492-A40929-TW/Final/Jasonkung 26 200826449 'A second adjustment signal is selected from the two complex predetermined pulse width adjustment signals; and a signal generator for adjusting according to a previous pulse width The pulse width control signal and the second adjustment signal in the clock cycle obtain a pulse width control signal. 17. The DC-to-DC converter of claim 13, wherein the pulse width modulation pulse generator further comprises: a pulse width modulation clock pulse signal generator for providing a pulse width modulation One pulse width modulation pulse pulse signal of the variable clock frequency; and a pulse width adjustment circuit for adjusting the pulse width of the pulse width modulation clock pulse signal according to the pulse width control signal. 18. The DC-to-DC converter of claim 13, wherein the first frequency is about 800 Hz. 19. The DC-to-DC converter of claim 13, wherein the second frequency is about 64 kHz. 20. The DC-to-DC converter of claim 13, wherein the pulse width modulated pulse signal has the second frequency of the second clock pulse signal. Client’s Docket No.: 95U003 TT^ Docket No:0492-A40929-TW/Final/Jasonkung 27