200825592 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種液晶顯示器，且特別是有關於一 種能夠增進液晶顯示器廣視角品質的液晶顯示器之晝素單 元。 ^ 【先前技術】 液晶顯示器已被廣泛的使用在各種電子產品中，例如 _ 電腦螢幕或電視中。為了提供廣視角，富士通（Fujitsu) 公司於1997年提出一種，晝素分割垂直配向（Multi—此贴比BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly to a pixel unit of a liquid crystal display capable of improving the wide viewing angle quality of a liquid crystal display. ^ [Prior Art] Liquid crystal displays have been widely used in various electronic products, such as _ computer screens or televisions. In order to provide a wide viewing angle, Fujitsu proposed a kind of split vertical alignment in 1997 (Multi-this ratio)
Vertical Alignment，MVA)技術。MVA技術可以獲得 wo度 的視角，而且，也可提供高對比及快速響應的優秀表現。 然而，MVA技術有一個極大之缺點，即是當斜視時對人的皮 膚顏色，尤其是亞洲人皮膚顏色，會產生色偏（c〇1〇r shift) 〇 第1圖係繪示一使用MVA技術之液晶分子之灰階電壓 與透射率的關係圖，其中橫軸係表示液晶分子之灰階電 壓’單位為伏特（V)，以及縱軸係表示透射率 (transmittance)。當人眼正視此液晶顯示器時，其透射率 與電壓之關係曲線是以虛線1〇1表示，當所施加之灰階電壓 一 增加時，其透射率隨之改變。而當人眼以一傾斜角度斜視 此液晶顯示器’其透射率與電壓之關係曲線是以虛線1 〇2表 不’雖然施加電壓增加其透射率亦隨之改變，但在區域〗〇〇 中’其透射率之變化並未隨著施加電壓之增加而增加，此 為造成色偏之主要原因。 200825592 傳統上解決上述問題之方法，係藉由在一晝素中形成 兩組可產生不同透射率與灰階電壓關係曲線之次畫素來補 償斜視時之透射率與灰階電魔之關係曲線。參閱第2圖所 $ ’其中之虛線201為原本之透射率與灰階電壓之關係曲 、 線，而另一虛線202則為同一晝素中之另一次晝素所產生之 、 透射率與灰階電《之關係曲線。藉由虛線2G1與虛線2〇2兩 者間之光學特性之混合，可獲至一較平滑之透射率與灰階 電壓之關係曲線，如第2圖中之實線203所示。 • ，然，上述藉由於一畫素單元中形成多個次畫素來補償 光學特性之方法，在相鄰圖框常會發生影像殘留之問題。 此疋口為#纟素具多個次畫素，而每一次晝素在對應薄 膜電晶體關閉之瞬間，其所儲存之資料電麈會產生不同程 f之電壓變化，藉以補償透射率與灰階電壓關係曲線。但 疋，每種不同程度之電壓變化，會使得一畫素中各次晝素 之貝料電壓，在對應一杻同共通電壓時，在相鄰兩圖框會 產生不同之育料電壓大小而造成影像殘留（image sticking) 之問題。 口此如何在一畫素中產生兩個次晝素，且不會有影 像殘留之問題，即成為追求之目標。 【發明内容】 本發明的目的之一係提供一種薄膜電晶體液晶顯示器 廣視角的技術，擁有不同之穿透率—電位曲線，用以改善色 偏現象。 本發明的另一目的是在提供一晝素單元，擁有至少兩 6 200825592 種穿透率-電位曲線而沒有影像殘留的現象 本發明的又—目的是在提供—畫素單元，用以在相 兩圖框對一資料電壓提供不同之電壓變化 有廣 本發明的又—目的是在提供—液晶顯示n，1不作呈 視角之特性，且其製程簡單、容易實施。 八Vertical Alignment, MVA) technology. MVA technology can provide a wide range of perspectives, and it also provides excellent performance with high contrast and fast response. However, MVA technology has a great disadvantage, that is, when the squint is applied to the human skin color, especially the Asian skin color, color shift (c〇1〇r shift) is generated. The first figure shows the use of MVA. A diagram showing the relationship between the gray scale voltage and the transmittance of the liquid crystal molecules of the technique, wherein the horizontal axis indicates that the gray scale voltage of the liquid crystal molecules is in volts (V), and the vertical axis indicates the transmittance. When the human eye is facing the liquid crystal display, the relationship between the transmittance and the voltage is indicated by a broken line 〇1, and as the applied gradation voltage increases, the transmittance thereof changes. When the human eye squints at the liquid crystal display at an oblique angle, the relationship between the transmittance and the voltage is indicated by the dotted line 1 〇 2, although the transmittance is also changed although the applied voltage is increased, but in the area 〇〇 The change in transmittance does not increase as the applied voltage increases, which is the main cause of color shift. 200825592 The traditional solution to the above problem is to compensate for the relationship between the transmittance of strabismus and the gray-scale electric magic by forming two sets of sub-pixels that can produce different transmittance and gray-scale voltage curves in a single element. Referring to Figure 2, the dotted line 201 is the relationship between the original transmittance and the gray-scale voltage, and the other dotted line 202 is the other transmittance of the same element, transmittance and gray. The relationship curve of the order electricity. By blending the optical characteristics between the dashed line 2G1 and the dashed line 2〇2, a smoother transmittance versus gray-scale voltage can be obtained, as indicated by the solid line 203 in FIG. • However, the above method of compensating for optical characteristics by forming a plurality of sub-pixels in a single pixel unit often causes image sticking in adjacent frames. The 疋 为 为 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 纟 对应 对应 对应 对应 对应 对应 对应 对应 对应 对应 对应 对应 对应 对应 对应Order voltage relationship curve. However, each voltage change of different degrees will cause the material voltage of each pixel in one pixel to produce different feed voltages in the adjacent two frames when corresponding to a common voltage. A problem that causes image sticking. How to produce two secondary elements in one pixel, and there is no problem of image residue, which is the goal of pursuit. SUMMARY OF THE INVENTION One object of the present invention is to provide a wide viewing angle of a thin film transistor liquid crystal display having different transmittance-potential curves for improving color shift. Another object of the present invention is to provide a halogen unit having at least two 200825592 transmittance-potential curves without image sticking. The present invention is further directed to providing a pixel unit for phase The two frames provide different voltage variations for a data voltage. The purpose of the present invention is to provide a liquid crystal display n, 1 without viewing angle characteristics, and the process is simple and easy to implement. Eight
人根，上述之㈣，本發明之—種液日日日顯示器，至少包 3 .第一基板；複數條資料線與複數條掃描線排列於該第 :基板上’其中該複數條資料線與掃描線相交又並定」出 複數個晝素，該晝素至少包含—第—次晝素和—第二次晝 素，其中每-該晝素包括：一第一電晶體，位於該第一： 晝=區’該第-電晶體之閘極端純至—該晝素所對應之 '第一該掃描線，該第一電晶體之汲極端耦接於一該畫素 所=應之-第-該資料線，該第—電晶體之源極端輕接於 —第一儲存電容；以及一第二電晶體，位於該第二次晝素 區’該第二電晶體之閘極端純至該第—該掃描線，該第 —^•晶體之汲極端耦接於該第一該資料線，該第二電晶體 之源極端耦接於一第二儲存電容，其中該第一儲存二=以 及該第二儲存電容至少其中之—為—可變電容，其中該可 、έΐ笔谷為一金屬-絕緣體-半導體電容D 根據一實施例，該金屬-絕緣體—半導體電容至少包括 一第一金屬層，一絕緣層以及一半導體層依序位於該第一 至屬層上，以及一第二金屬層位於該半導體層上，而該半 &體層至少包括一非晶矽層和一 η+摻雜非晶石夕層。 根據一實施例，該金屬-絕緣體—半導體電容之該第一 7 200825592 金屬耦接至該第一電晶體或該第二電晶體之源極端，該第 二金屬層耦接至一偏壓。當該偏壓值小於該源極端電壓 時，該金屬-絕緣體-半導體電容具有一第一電容值，而^ 偏壓值大於該源極端電壓時，該金屬_絕緣體_半導體電^ 具有一第二電容值，其中該第一電容值大於該第二電容值^ 根據一實施例，該金屬-絕緣體—半導體電容之該第一 金屬耦接至一偏壓，該第二金屬層耦接至該第一電晶體 該第二電晶體之源極#。當該偏壓值小於胃源極端電二 時，該金屬-絕緣體-半導體電容具有一第一電容值，而ι 偏壓值大於該源極端電壓時，該金屬—絕緣體—半導體 具有-第二電容值，其中該第—電容值小於該第二電容^ 根據-實施例，更包括一第二基板面對該第— 其中該第二基板上具有一共通電極。其中該共通電極 與位於該第-次畫素之晝素電極形成一第—液晶電容，以 電極與位於該第二次晝素之4素電極形成一第二 根據本發明之另-實施例，本發明提供—種液晶顧干 c，係用以驅動一畫素，”該晝素包含具一 ::電Β曰體之-第—次晝素與具一第二電晶體之一第二次 :掃η;:與第二電晶體之閑極端分別輕接於-第 晶體與該第二電晶體之沒極端_ =:猎第—資料線對該第-次晝素之晝素電 供一低t「人旦素之晝素電極’寫入-資料電壓；以及提 七、低電位至該第-掃描線，使該第—電晶體和該第二電 8 200825592 晶體絕緣於該資料線；丨中，於相鄰圖框之第—圖框時， 當該第-掃描線於該高電位與低電位轉換之後，會對該第 -次畫素之畫素電極與該第二次晝素之晝素電極產生 :電壓變化以犮一第二電壓變化，而於第二圖框時，當該 第-掃描線於該高電位與低電位轉換之後，會料第—欠 畫素之晝素電極與該第二次晝素之畫素電極產生_第三帝 壓變化以及該第二電壓變化。 包 根據一實施例，其中号笛 -U ^ . 这弟一次晝素包括一金屬-絕緣體 -半V體電容，其中該金屬—絕緣體-半導體電容至少包括一 第-金屬層’―絕緣層以及—半導體層依序位於該第一全 屬層上，以及-第二金屬層位於該半導體層上，其中者施 加於該第-金屬層上之電壓大於施加於該第二金屬層二 電壓％，s亥金屬-絕緣體_半導體電容具有一第—電容 ^當施加於該第-金屬層上之電壓小於施加於該第二金屬 二上之電壓時，該金屬-絕緣體-半導體電容具有—第二 奋值，其中該第一電容值大於該第二電容值。 ^ 根據一實施例，該金屬—絕緣體—半導體電容之該 接至叆第一電晶體之源極端’該第二金屬層耦接至 ;偏壓。而該第一讓化之絕對值小於該第二 而該第二電壓變化之絕對值小於該第三電壓變 八根據一實施例，該金屬-絕緣體-半導體電容之該第一 金屬輕接至—偏壓’該第二金屬層轉接至該第—電曰^之 :極端。而該第一電壓變化之絕對值大於該第二電：二 1巴對值，而該第二電壓變化之絕對值大於該第三電壓變 9 200825592 化之絕對值。 人:二另★二知例中’本發明提供-種晝素結構，至少包 1別作瞪，兩分離之第一金屬層位於該玻璃基板上， 刀別作為一薄膜電# _ -半導騁德尸㈣ 屬 及一金屬一絕緣層 ，一、'子包奋之下電極；一絕緣層位於該閘極金屬層Human root, the above (4), the liquid-liquid day-to-day display of the present invention includes at least 3. a first substrate; a plurality of data lines and a plurality of scanning lines are arranged on the first substrate: wherein the plurality of data lines and The scan lines intersect and define a plurality of halogens, the halogen containing at least a first-order halogen and a second halogen, wherein each of the halogens comprises: a first transistor, located at the first : 昼 = region 'the gate of the first transistor is extremely pure to - the first of the scan lines corresponding to the halogen, the first transistor is coupled to a pixel of the first antenna = the first - the data line, the source of the first transistor is extremely lightly connected to the first storage capacitor; and a second transistor is located in the second halogen region, the gate of the second transistor is extremely pure to the first - the scan line, the first transistor is coupled to the first data line, and the source of the second transistor is coupled to a second storage capacitor, wherein the first storage 2 = At least one of the second storage capacitors is a variable capacitor, wherein the tangible valley is a metal-insulator- Conductor Capacitor D According to an embodiment, the metal-insulator-semiconductor capacitor includes at least a first metal layer, an insulating layer and a semiconductor layer are sequentially disposed on the first subordinate layer, and a second metal layer is located in the semiconductor On the layer, the half & body layer comprises at least an amorphous germanium layer and an n+ doped amorphous layer. According to an embodiment, the first 7 200825592 metal of the metal-insulator-semiconductor capacitor is coupled to the source terminal of the first transistor or the second transistor, and the second metal layer is coupled to a bias voltage. When the bias value is less than the source extreme voltage, the metal-insulator-semiconductor capacitor has a first capacitance value, and when the bias voltage is greater than the source terminal voltage, the metal_insulator-semiconductor has a second a capacitance value, wherein the first capacitance value is greater than the second capacitance value. According to an embodiment, the first metal of the metal-insulator-semiconductor capacitor is coupled to a bias voltage, and the second metal layer is coupled to the capacitor A transistor is the source # of the second transistor. When the bias value is less than the gastric source extreme power, the metal-insulator-semiconductor capacitor has a first capacitance value, and when the ι bias value is greater than the source terminal voltage, the metal-insulator-semiconductor has a second capacitance The value, wherein the first capacitance value is smaller than the second capacitance, according to the embodiment, further comprising a second substrate facing the first surface - wherein the second substrate has a common electrode. Wherein the common electrode forms a first liquid crystal capacitor with the pixel electrode at the first pixel, and the electrode and the fourth electrode of the second pixel form a second embodiment according to the present invention. The present invention provides a liquid crystal Guganc for driving a pixel, "the halogen contains one:: an electric body - a first electron and a second one with a second transistor Sweep η;: lightly connected to the idle end of the second transistor, respectively - the second crystal and the second transistor are not extreme _ =: hunting - data line for the first - 昼 昼 昼 电 电a low t "human elementary electrode" write-data voltage; and a seventh, low potential to the first scan line, so that the first transistor and the second electric 8 200825592 crystal are insulated from the data line; In the first frame of the adjacent frame, after the first scan line is converted to the high potential and the low potential, the pixel element of the first pixel and the second pixel are The halogen electrode generates: the voltage changes to a second voltage change, and in the second frame, when the first scan line is turned at the high potential and the low potential After that, it is expected that the pixel element of the first-picture element and the pixel element of the second element of the pixel generate a third voltage change and the second voltage change. According to an embodiment, wherein the horn-U ^ The first element includes a metal-insulator-semi-V body capacitor, wherein the metal-insulator-semiconductor capacitor includes at least a first metal layer, an insulating layer, and a semiconductor layer sequentially on the first full layer And a second metal layer is disposed on the semiconductor layer, wherein a voltage applied to the first metal layer is greater than a voltage applied to the second metal layer, and the metal-insulator-semiconductor capacitor has a first capacitor When the voltage applied to the first metal layer is less than the voltage applied to the second metal two, the metal-insulator-semiconductor capacitor has a second value, wherein the first capacitance value is greater than the second capacitance According to an embodiment, the metal-insulator-semiconductor capacitor is connected to the source terminal of the first transistor. The second metal layer is coupled to the bias voltage, and the absolute value of the first pass is less than The second and the first The absolute value of the two voltage changes is less than the third voltage change. According to an embodiment, the first metal of the metal-insulator-semiconductor capacitor is lightly connected to the bias voltage. The second metal layer is switched to the first power. ^的: Extreme. The absolute value of the first voltage change is greater than the second power: two 1 bar pair value, and the absolute value of the second voltage change is greater than the absolute value of the third voltage change 9 200825592. In addition, in the second example, the invention provides a structure of a halogen, at least one of which is provided as a crucible, and the first separated metal layer is located on the glass substrate, and the knife is used as a thin film electricity # _ - semi-guided The corpse (4) belongs to a metal-insulation layer, and the 'sub-packaged lower electrode; an insulating layer is located at the gate metal layer
、作為該薄膜電晶體之閘極絕緣層，以及位於該第 奶:屬s上用以作為該金屬—絕緣層-半導體儲存電容之 巴緣層i #晶石夕層以及一 n+摻雜非晶石夕層依序且分別形 t晶體閘極絕緣層以及該金屬—絕緣層—半導體 7存電容絕緣層之上方，其中非該料層以及該n+摻雜非 晶矽層，係分別作為該薄膜電晶體之源極與汲極，以及該 至屬—絕緣層—半導體儲存電容之半導體層；一第二金屬層 分別位於該薄膜電晶體之源極與汲極以及該金屬—絕緣芦曰一 半，體儲存電容半導體層之上方，其中該第二金屬層、日該 非晶石夕層以及該n+換雜非晶梦層共同構成該薄膜電晶體之 源極結構與汲極結構，而胃第二金屬層作為該金屬一絕緣層 半&體儲存笔各之上電極；以及一保護層，位於該薄膜電 曰曰體之源極結構、汲極結構以及該金屬_絕緣層—半導體儲 存電容之上電極上方。 根據一實施例，該保護層更具有一第一接觸孔以曝露 出該薄膜電晶體之源極，以及一第二接觸孔以曝露出該金 屬-絕緣層-半導體儲存電容之下電極。一銦錫氧化物（110) 層為於該保護層上表面、該第一接觸孔以及該第二接觸孔 中’以連接該薄膜電晶體之源極以及該金屬—絕緣層-半導 體儲存電容之下電極。 200825592 _根二實::1::於該薄膜電晶體之叫 以至屬、，'巴緣層-半導體儲存電容半導體層上方 屬層係連接在一起。該保護層更具有一第_ u 出該金屬-絕緣層-半導㈣存電容電:接觸孔以曝露 =二 保護層上表面和該第三接觸孔中，以連 SI::晶體之源極以及該金屬，緣層-半導體儲存電 二所，’本發明藉由將一晝素單元區隔成兩次畫 人晝素中包含獨立之薄膜電晶體、液晶電容與 儲i子電谷，且至少其中之—之儲存電容係採用可變電容， 猎由可變電容之電容特性，在相鄰兩圖框時段中，可使得 貢料電壓產生不同程度之電壓變化，藉以讓變化後之資料 電壓對稱於共通電壓，而解決影像殘留之問題。、 【實施方式】 在不限制本發明之精神及應用範圍之下，以下即以複 數個實施例，介紹本發明之實施；熟悉此領域技藝者，在 瞭解本發明之精神後，當可應用本發明之液錢示器結構 於各種不同之液晶顯示器、中。 第一實施例 參閱第3圖所示為根據本發明第一實施例的晝素單元 概略圖示。晝素單元300,包含兩次晝素3〇2和綱。 其中次晝素302包含一薄膜電晶體3〇21，其閘極連接 11 200825592 於掃描線306 ’汲極連接於資料線3〇8，源極則連接於畫素 電極3022,其中晝素電極3Q22和一偏麼1心構成儲；電 容302^，畫素電極3022和共通電極v_構成液晶電容 3024。 薄膜電晶冑3021之源極和閘極間則具有一擴散電容 3025。 而次畫素304包含一薄膜電晶體3〇41，其閘極連接 於掃描線306’汲極連接於資料線3〇8，而源極則連接於畫 素電極3042,其中畫素電極難和偏壓^構成儲存= 容3_，畫素電極繼和共通電極l構成液晶電容 3044。 薄膜電晶體3Q41之源極和閘極間則具有—擴散電容 3045。 在本實施例中，要特別注意的是，儲存電容如“係 知用金屬-絕緣體-半導體-金屬之電容結構，即所謂mis之 電容結構’而儲存電容難則係採用金屬_絕緣體_金屬之 電容結構，亦即傳統之電容結構。 參閱第4A圖係顯示第3圖之儲存電容3〇23之金屬_ 絕緣體-半㈣（MIS)結構之較佳實施示意圖。在第一金屬 層401與第二金屬層4〇2 fa1，夾有絕緣層彻與半導體層 404。金屬-絕緣體_半導體_金屬會構成一個電容器。它^ -般電容器的區別在於電容值並不是恆定的。其電盘 施加在第-金屬層401和第二金屬層4〇2間之電犀： (U«2)有關，其電容電壓之關係圖如第仙圖所示:盆 中當施加於第-金屬層術上之電壓（I)大於施加於第 二金屬層4G2上之電壓（Vm2)，亦即電壓差（u_Vm2)為正 值時，其電容值隨著電壓差之增加而急遽上升。而當施加 於弟-金屬層纽上之電壓（Vmi)小於施加於第二金屬層 402上之電壓（Vm2)，亦即電壓差（id為負值時，^ 12 200825592 電容值隨著電壓差之择+ 曰π而漸趨下降。由於第4B圖所示之 電容-電壓曲線並未對稱於 於原點，因此本發明藉由於第一金 屬層401或第二金屬厣4η 、 屬9 402上施加一偏壓Vbias，來位移原 點，使得電容-電壓曲綠π μ _ 線了對稱於調整後之原點。在此情況 下，當兩者電壓差大；, ^ 門松值（VthDd+ )或小於一負門 檻值（VtM)時，J：雷交佶仏A输 、 了 ，、电奋值均會趨於一定值。在本實施例 中以c_…代表’當兩者電壓差為正值且大於一正門檻值 (v_)時之電容值，並q 。"代表，#兩者電遷差為As a gate insulating layer of the thin film transistor, and a pad layer i as a metal-insulating layer-semiconductor storage capacitor and a n+ doped amorphous layer on the first milk genus s The stone layer sequentially and separately forms a crystal gate insulating layer and the metal-insulating layer-semiconductor 7 storage capacitor insulating layer, wherein the material layer and the n+ doped amorphous germanium layer are respectively used as the film a source and a drain of the transistor, and a semiconductor layer of the semiconductor-storage capacitor; and a second metal layer respectively located at a source and a drain of the thin film transistor and a half of the metal-insulated reed, Above the bulk storage capacitor semiconductor layer, wherein the second metal layer, the amorphous layer and the n+ replaced amorphous dream layer together form a source structure and a drain structure of the thin film transistor, and the second metal of the stomach a layer as an upper electrode of the metal-insulating layer half & body storage pen; and a protective layer located on the source structure of the thin film electrical body, the drain structure, and the metal-insulating layer-semiconductor storage capacitor On the electrode square. According to an embodiment, the protective layer further has a first contact hole for exposing the source of the thin film transistor, and a second contact hole for exposing the metal-insulating layer-semiconductor storage capacitor lower electrode. An indium tin oxide (110) layer is formed on the upper surface of the protective layer, the first contact hole and the second contact hole to connect the source of the thin film transistor and the metal-insulating layer-semiconductor storage capacitor Lower electrode. 200825592 _根二实::1:: In the thin film transistor, the genus, the 'bar edge layer-semiconductor storage capacitor semiconductor layer above the layer is connected together. The protective layer further has a metal-insulating layer-semiconducting (four) storage capacitor: a contact hole to expose the upper surface of the second protective layer and the third contact hole to connect the source of the SI:: crystal And the metal, the edge layer-semiconductor storage electric two, 'the present invention comprises a separate thin film transistor, a liquid crystal capacitor and a storage sub-electric valley by dividing the monoterpenoid unit into two paintings. At least one of the storage capacitors is a variable capacitor, and the capacitance characteristic of the variable capacitor is used to cause different voltage changes in the tributary voltage during the adjacent two frame periods, so that the changed data voltage is obtained. Symmetrical to the common voltage, to solve the problem of image sticking. The embodiments of the present invention are described below in a plurality of embodiments without departing from the spirit and scope of the present invention. Those skilled in the art, after understanding the spirit of the present invention, may apply the present invention. The liquid money display of the invention is constructed in various liquid crystal displays. First Embodiment Referring to Fig. 3, there is shown a schematic diagram of a halogen unit according to a first embodiment of the present invention. The halogen unit 300 includes two halogens 3〇2 and an outline. The secondary halogen 302 comprises a thin film transistor 3〇21, the gate connection 11 200825592 is connected to the data line 3〇8 on the scan line 306′, and the source is connected to the pixel electrode 3022, wherein the halogen electrode 3Q22 And a biased one core constitutes a reservoir; a capacitor 302^, a pixel electrode 3022 and a common electrode v_ constitute a liquid crystal capacitor 3024. A thin film capacitor 3022 has a diffusion capacitor 3025 between the source and the gate. The sub-pixel 304 includes a thin film transistor 3〇41, the gate is connected to the scan line 306', the drain is connected to the data line 3〇8, and the source is connected to the pixel electrode 3042, wherein the pixel electrode is difficult to The bias voltage constitutes a storage = capacitance 3_, and the pixel electrode and the common electrode 1 constitute a liquid crystal capacitor 3044. The source of the thin film transistor 3Q41 has a diffusion capacitor 3045 between the source and the gate. In this embodiment, it is particularly important to note that the storage capacitor is such as "a metal-insulator-semiconductor-metal capacitor structure, that is, a so-called mis-capacitor structure" and the storage capacitor is difficult to use a metal_insulator-metal. The capacitor structure, that is, the conventional capacitor structure. Referring to FIG. 4A, a schematic diagram of a preferred embodiment of the metal-insulator-semi-four (MIS) structure of the storage capacitor 3〇23 of FIG. 3 is shown. The two metal layers 4〇2 fa1 are sandwiched with an insulating layer and a semiconductor layer 404. The metal-insulator_semiconductor_metal forms a capacitor. The difference between the capacitors is that the capacitance value is not constant. The electric rhinoceros between the first metal layer 401 and the second metal layer 4〇2: (U«2), the relationship between the capacitance voltages is as shown in the figure: the pot is applied to the first metal layer. The voltage (I) is greater than the voltage (Vm2) applied to the second metal layer 4G2, that is, when the voltage difference (u_Vm2) is a positive value, the capacitance value rises sharply as the voltage difference increases. The voltage on the metal layer (Vmi) is less than the voltage applied to the second The voltage on the metal layer 402 (Vm2), that is, the voltage difference (when the id is negative, the capacitance value of the ^ 12 200825592 gradually decreases with the selection of the voltage difference + 曰 π. Since the capacitance-voltage shown in Fig. 4B The curve is not symmetrical to the origin. Therefore, the present invention shifts the origin by applying a bias voltage Vbias on the first metal layer 401 or the second metal 厣4 η and the genus 9 402, so that the capacitance-voltage is π μ _ The line is symmetrical to the adjusted origin. In this case, when the voltage difference between the two is large; ^, the threshold value (VthDd+) or less than a negative threshold value (VtM), J: Thunder exchange A loses , the electric value will tend to a certain value. In this embodiment, c_... represents the capacitance value when the voltage difference between the two is positive and greater than a positive threshold (v_), and q. " , #两电迁差为
負值且小於-負門檻值（w)時之電容值。另外，誠如 上述，如第4A圖之金屬-絕緣體_半導體（MIS)結構之電容， -般係稱為可變電容’或稱電壓控制電容(v〇itagec〇ntr〇i capacitor ， VCCAP) 〇 本發明之畫素單元300可由多種不同之畫素結構加以 形成，第5A圖與第5B圖為多種晝素結構其中之一，且不 用以限，本發明之結構。其中第5A圖所示為根據次晝素 302之薄膜電晶體3021與金屬-絕緣體-半導體（Mis)儲存 電容3023之結構示意圖。而第5B圖所示則為次晝素3〇4 中之薄膜電晶體3041及金屬-絕緣體—金屬儲存電容3〇43 之結構示意圖。值得注意的是，雖然第5A圖與第5B圖為 了燒明目的而分開展示，但均係以同一製程程序加以完成。 首先请麥閱第5A圖’次畫素302中，共通電極vCDm形 成於一玻璃基板510上，而薄膜電晶體3021與具金屬—絕 緣體-半導體結構之儲存電容3023則共同形成在另一玻璃 基板500上。其中於玻璃基板500上具有一金屬層5〇2，分 別作為薄膜電晶體3021之閘極金屬層，以及儲存電容3〇23 13 200825592 之第一金屬層（即第4A圖中之第一金屬層401)。一絕緣層 503形成於玻璃基板500上，用以覆蓋金屬層502，其中絕 緣層503分別作為薄膜電晶體3021之閘極絕緣層，以及儲 存電容3023之絕緣層（即第4A圖中之絕緣層403 )。一非 晶矽層504以及一 n+摻雜非晶矽層505依序且分別形成於 薄膜電晶體閘極絕緣層以及儲存電容絕緣層之上方，其中 非晶矽層504以及一 n+摻雜非晶矽層505，係分別作為薄 膜電晶體3021之主動區（或半導體層），以及儲存電容3023 之半導體層（即第4A圖中之半導體層404)。接著一金屬層 506形成於薄膜電晶體3021之n+摻雜非晶矽層505上以形 成源極與淚極電極，以及儲存電容3 0 2 3半導體層之上方， 其中金屬層506、非晶矽層504以及n+摻雜非晶矽層505 共同構成溥膜電晶體3 0 21之源極結構與及極結構’同時金 屬層506亦作為儲存電容3023之第二金屬層（即第4八圖 中之金屬層402)。一保護層507沉積於該玻璃基板500之 上，用以覆蓋薄膜電晶體3021之源極結構、汲極結構以及 儲存電容3023之第二金屬層，其中保護層507具有接觸孔 (through hole)509以曝露出薄膜電晶體3021之源極，以 及接觸孔511和512以曝露出儲存電容3023之第一金屬層 上表面。然後一作為像素電極之銦錫氧化物（IT0)層508形 成於保護層507之上表面，以連接薄膜電晶體3021之源 極、儲存電容3023之第一金屬層，作為次晝素302之晝素 電極3022。其中薄膜電晶體3021中之源極電極以及閘極金 屬層502共同構成擴散電容3025。而玻璃基板510上之共 通電極V_與銦錫氧化物（IT0)層508構成液晶電容3024。 14 200825592 接著請參閱第5B圖，次晝素304中，共通電極形 成於一玻璃基板510上，而薄膜電晶體3041與具金屬-絕 緣體-金屬結構之儲存電容3043共同形成在另一玻璃基板 500上。其中於玻璃基板500上具有一金屬層502，分別作 為薄膜電晶體3041之閘極金屬層，以及儲存電容3043之 第一電極。一絕緣層503形成於玻璃基板500上，用以覆 蓋金屬層502，其中絕緣層503分別作為薄膜電晶體3041 之閘極絕緣層，以及儲存電容3043之絕緣層。一非晶矽層 504以及一 η+摻雜非晶矽層505依序形成於薄膜電晶體閘 極絕緣層上方，作為薄膜電晶體3041之主動區。接著一金 屬層506形成於薄膜電晶體3041之源極與汲極，以及儲存 電容3043絕緣層層之上方，其中金屬層506、非晶矽層504 以及η+摻雜非晶矽層505共同構成薄膜電晶體3041之源極 結構與汲極結構，同時金屬層506亦作為儲存電容3043之 第二電極。另外，一保護層507沉積於該玻璃基板500之 上，用以覆蓋薄膜電晶體3041之源極結構、汲極結構以及 儲存電容3043之第二電極，其中保護層507具有接觸孔513 以曝露出儲存電容3043之第二電極上表面。然後一作為像 素電極之銦錫氧化物（ΙΤΟ)層508形成於保護層507之上表 面，以連接儲存電容3043之第二電極。其中薄膜電晶體 3041中之源極結構以及閘極金屬層502共同構成第3圖之 擴散電容3045。而玻璃基板510上之共通電極與銦錫 氧化物（ITO)層508構成液晶電容3044。 參閱第6圖所示為根據本發明一較佳實施例用以驅動 本發明晝素單元300之驅動波形圖，請同時參閱第3圖。 15 200825592 在一寫入正極性資料之奇數圖框中，在時段Τι開始時，掃 描線306電位上升至一高位準狀態，Vgh，薄膜電晶體3021 以及3041被打開，資料線308上傳送之正極性電壓資料， 假設為VP，會分別由經由薄膜電晶體3021及3041對液晶 電容3024和3044以及儲存電容3023和3043進行充電。 在時段T!終了時，掃描線306電位下降成一低位準狀態， VgL，薄膜電晶體3021及3041被關閉。此時液晶電容3024 和3044兩端之電壓是藉由儲存電容3023和3043維持住。 但是在薄膜電晶體3021及3041被關閉之瞬間，正極性電 壓資料，Vp，會下降一 值，此值之大小與薄膜電晶 體之閘極源極間之擴散電容、液晶電容和儲存電容有關。 根據本發明之第一實施例，晝素單元300包括次晝素302 和304，因此具有兩AV值，以及△ V2，並分別使該兩 次晝素之晝素電極具不同之壓值，VP1* VP2，其中AVi與薄 膜電晶體3021之閘極源極間之擴散電容3025、液晶電容 3024和儲存電容3023有關，其大小如下所述： AV{ = (Vgh — VgL) X C3〇25 /(Q〇25 Q〇24 Q〇23) 而AV2與薄膜電晶體3041之閘極源極間之擴散電容 3045、液晶電容3044和儲存電容3043有關，其大小如下 所述： ΔΚ2 = (Vgh — VgL)X C3〇45 /(Q〇45 + Q〇44 + Q043) 根據本實施例，儲存電容3023係採用如第4A圖所示 16 200825592 由至屬絶緣體-半導體結構所形成之可變電容（或稱電壓 控制电谷）’因此，在寫入正極性資料之奇數圖框中，其寫 入之正極性電壓資料Vp之電壓值大於施加之偏壓值vbias’， 亦P ^加於第4A圖所示電容結構中第一金屬層術上之 *電^大於知加於第二金屬層4G2上之電壓，因此電壓差為 .正值且大於正門檻電壓值（ν_)。依此實施例，儲存電容 3〇23_，電容值將為如第4Β圖所示），因此在寫入正 極性貢料之奇數圖框中，其AVi值大小如下所述： ^.(-) = (^-rgJxC3025 /(C3025 + C3024 + C3023,on) 士在一寫入負極性資料之偶數圖框中，在時段T2開始 時’掃描線306電位上升至一高位準狀態，Vgh，薄膜電晶 體扣21以及3041被打開，資料、線3〇8上傳送之負極性電 壓資料’假設為-vP，會分別由經由薄膜電晶體3〇21及3〇4ι 對液晶電容3〇24和3044以及儲存電容3〇23和3〇43進行 _ 充，。在時段T遵了時，掃描線議電位下降成一低位準 =恶’ vgL ’薄膜電晶體3021及3〇41被關閉。此時液晶電 容3024和3044兩端之電壓是藉由儲存電容3〇23和3〇43 維持住。但是在薄膜電晶體3021及3〇4"皮截止之瞬間， • 負極性電壓資料…V”會下降-AV值。此Λν值之大小與 薄膜電晶體之閘極源極間之擴散電容、液晶電容和儲存電 容有關。 根據本實施例，由於儲存電容3〇23係採用如第4八圖 所示由金屬-絕緣體-半導體結構所形成之可變電容，= 17 200825592 此，對次書去q Π 9 1 ^ ~ ’在寫入負極性資料之偶數圖框中，其寫 :之負極性電壓資料之電壓值—Vp小於施加之偏壓值V—， :P知加於第4A圖所示電容結構中第一金屬層4〇1上之 :幻於苑加於第二金屬層4〇2上之電壓，因此電壓差為 、〗於負門榼電壓值（Vthc)d_ 依此實施例，儲存電容 . 23，电合值將為价（如第4B圖所示）因此在寫入負 極性貧料之偶數圖框中，其/^值大小如下所述： • δκι(〇#) . {Vgh ^l)x /{c^ + ^ + ❿次畫素304，其與薄膜電晶體3041之閘極源極 1之擴政包谷3045、液晶電容3044和儲存電容3043有關， 其大小如下所述： X C3045 /(C3045 +c3044 +c3043) % ，由於次晝素302中之儲存電容3023係採用金屬—絕緣 體-半導體結構所形成之可變電容，因此，對次晝素3〇2而 "寫入負極性貢料與寫入正極性資料降產生不同之電壓 變化，電容值C_…大於，因此，寫入正極性資料 • %之電壓變化值△ Vl⑽）小於寫人負極性資料時之電壓變 • 化值AVl (〇ff)°而次晝素304中之儲存電容3043係採用 至屬-絶緣體-金屬結構所形成之電容，因此，對次畫素 而吕，不論是在寫入負極性資料或正極性資料時之圖框， 其電壓變化值均為AV2。 18 200825592 根據本實施例，擴散電容3025之電容值等於擴散電容 3045之電容值。液晶電容3024之電容值等於液晶電容3044 之電容值。而儲存電容3023為一可變電容，在寫入正極性 資料時儲存電容3023之電容值Cmmw大於儲存電容3043 之電容值，而在寫入負極性資料時，儲存電容3023之電容 值C加“//將小於儲存電容3043之電容值。因此，電壓變化 值間之大小關係為△MOffhADAMON)。然而，值得 注意的是，雖然本實施例係以擴散電容3025之電容值等於 擴散電容3045之電容值，以及液晶電容3024之電容值等 於液晶電容3044之電容值為例，然，本發明之實施將不以 此為限。 請再次參閱第6圖所示，由於儲存電容3023是使用如 第4A圖所示由金屬-絕緣體-半導體結構所形成之可變電 容。因此就次晝素302而言，在薄膜電晶體3021及3041 被截止之瞬間，對寫入之正極性資料與寫入之負極性資料 將產生不同之電壓變化值。而儲存電容3043其電容值不可 變。因此就次晝素304而言，在薄膜電晶體3021及3041 被截止之瞬間，對寫入之正極性資料與寫入之負極性資料 將產生相同之電壓變化值。因此，在本實施例中，可藉由 調整可變儲存電容3023，使得次晝素302與次晝素304, 在相鄰兩圖框於薄膜電晶體3021及3041關閉後之資料電 壓彼此趨近對稱於共通電壓亦即，就次晝素302而言， 在奇圖框之資料電壓V/，，等於在偶圖框之資料電壓V;，e。而 就次晝素304而言’在奇圖框之貧料電壓V σ等於在偶圖框 之貧料電麗V & ^。 19 200825592 次晝素302之光學特性可藉由資料電壓 之均方根值（Root Mean Square)來加以評估。而，查Vie 304之光學特性可藉由資料電壓以及而次晝素 -hxj ϋ2 iSR A4- « =方根值來 因此，次畫素 302 之光幾处 尤學特性為The value of the capacitor when it is negative and less than - negative threshold (w). In addition, as mentioned above, the capacitance of the metal-insulator-semiconductor (MIS) structure as shown in FIG. 4A is generally referred to as a variable capacitor or a voltage-controlled capacitor (VCCAP). The pixel unit 300 of the present invention can be formed by a plurality of different pixel structures, and FIGS. 5A and 5B are one of various halogen structures, and the structure of the present invention is not limited thereto. FIG. 5A is a schematic view showing the structure of a thin film transistor 3021 and a metal-insulator-semiconductor (Mis) storage capacitor 3023 according to the secondary halogen 302. The structure of the thin film transistor 3041 and the metal-insulator-metal storage capacitor 3〇43 in the secondary halogen 3〇4 is shown in Fig. 5B. It is worth noting that although Figures 5A and 5B are shown separately for the purpose of burning, they are all done in the same process. First, in the fifth pixel of FIG. 5A, the common electrode vCDm is formed on a glass substrate 510, and the thin film transistor 3021 and the storage capacitor 3023 having a metal-insulator-semiconductor structure are formed together on another glass substrate. 500. There is a metal layer 5〇2 on the glass substrate 500, which is respectively used as a gate metal layer of the thin film transistor 3021, and a first metal layer of the storage capacitor 3〇23 13 200825592 (ie, the first metal layer in FIG. 4A). 401). An insulating layer 503 is formed on the glass substrate 500 for covering the metal layer 502. The insulating layer 503 serves as a gate insulating layer of the thin film transistor 3021 and an insulating layer of the storage capacitor 3023 (ie, the insulating layer in FIG. 4A). 403). An amorphous germanium layer 504 and an n+ doped amorphous germanium layer 505 are sequentially formed over the thin film transistor gate insulating layer and the storage capacitor insulating layer, respectively, wherein the amorphous germanium layer 504 and an n+ doped amorphous layer The germanium layer 505 is used as the active region (or semiconductor layer) of the thin film transistor 3021 and the semiconductor layer of the storage capacitor 3023 (i.e., the semiconductor layer 404 in FIG. 4A). A metal layer 506 is then formed on the n+ doped amorphous germanium layer 505 of the thin film transistor 3021 to form a source and a tear electrode, and a storage capacitor 3 0 2 3 over the semiconductor layer, wherein the metal layer 506, amorphous germanium The layer 504 and the n+ doped amorphous germanium layer 505 together form the source structure and the pole structure of the germanium transistor 3 0 21 , and the metal layer 506 also serves as the second metal layer of the storage capacitor 3023 (ie, in FIG. Metal layer 402). A protective layer 507 is deposited on the glass substrate 500 to cover the source structure of the thin film transistor 3021, the drain structure, and the second metal layer of the storage capacitor 3023. The protective layer 507 has a through hole 509. The source of the thin film transistor 3021 is exposed, and the contact holes 511 and 512 are exposed to expose the upper surface of the first metal layer of the storage capacitor 3023. Then, a layer of indium tin oxide (IT0) 508 as a pixel electrode is formed on the upper surface of the protective layer 507 to connect the source of the thin film transistor 3021 and the first metal layer of the storage capacitor 3023 as the second layer of the secondary oxide 302. Element electrode 3022. The source electrode and the gate metal layer 502 in the thin film transistor 3021 together constitute a diffusion capacitor 3025. The common electrode V_ and the indium tin oxide (IT0) layer 508 on the glass substrate 510 constitute a liquid crystal capacitor 3024. 14 200825592 Next, referring to FIG. 5B, in the secondary halogen 304, the common electrode is formed on a glass substrate 510, and the thin film transistor 3041 is formed together with the storage capacitor 3043 having a metal-insulator-metal structure on the other glass substrate 500. on. The glass substrate 500 has a metal layer 502 as a gate metal layer of the thin film transistor 3041 and a first electrode of the storage capacitor 3043. An insulating layer 503 is formed on the glass substrate 500 for covering the metal layer 502. The insulating layer 503 serves as a gate insulating layer of the thin film transistor 3041 and an insulating layer of the storage capacitor 3043, respectively. An amorphous germanium layer 504 and an n+ doped amorphous germanium layer 505 are sequentially formed over the thin film transistor gate insulating layer as the active region of the thin film transistor 3041. A metal layer 506 is formed over the source and drain of the thin film transistor 3041 and over the insulating layer of the storage capacitor 3043, wherein the metal layer 506, the amorphous germanium layer 504, and the n+ doped amorphous germanium layer 505 are combined. The source structure and the drain structure of the thin film transistor 3041, and the metal layer 506 also serves as the second electrode of the storage capacitor 3043. In addition, a protective layer 507 is deposited on the glass substrate 500 to cover the source structure of the thin film transistor 3041, the drain structure, and the second electrode of the storage capacitor 3043. The protective layer 507 has a contact hole 513 for exposing The upper surface of the second electrode of the storage capacitor 3043 is stored. Then, a layer of indium tin oxide (germanium) 508 as a pixel electrode is formed on the upper surface of the protective layer 507 to connect the second electrode of the storage capacitor 3043. The source structure of the thin film transistor 3041 and the gate metal layer 502 collectively constitute the diffusion capacitor 3045 of FIG. The common electrode on the glass substrate 510 and the indium tin oxide (ITO) layer 508 constitute a liquid crystal capacitor 3044. Referring to Fig. 6, there is shown a driving waveform diagram for driving the pixel unit 300 of the present invention in accordance with a preferred embodiment of the present invention. Please also refer to Fig. 3. 15 200825592 In the odd-numbered frame of the positive polarity data, at the beginning of the period Τ, the potential of the scanning line 306 rises to a high level state, Vgh, the thin film transistors 3021 and 3041 are turned on, and the positive electrode transmitted on the data line 308 The voltage data, assuming VP, charges the liquid crystal capacitors 3024 and 3044 and the storage capacitors 3023 and 3043 via thin film transistors 3021 and 3041, respectively. At the end of the period T!, the potential of the scan line 306 drops to a low level state, and VgL, the thin film transistors 3021 and 3041 are turned off. At this time, the voltage across the liquid crystal capacitors 3024 and 3044 is maintained by the storage capacitors 3023 and 3043. However, at the moment when the thin film transistors 3021 and 3041 are turned off, the positive polarity voltage data, Vp, drops by a value which is related to the diffusion capacitance, the liquid crystal capacitance and the storage capacitance between the gate and source of the thin film transistor. According to the first embodiment of the present invention, the halogen unit 300 includes the secondary halogens 302 and 304, thus having two AV values, and ΔV2, and respectively causing the two halogen elements to have different pressure values, VP1 * VP2, where AVi is related to the diffusion capacitance 3025, liquid crystal capacitor 3024 and storage capacitor 3023 between the gate and source of the thin film transistor 3021, and its size is as follows: AV{ = (Vgh - VgL) X C3〇25 / ( Q〇25 Q〇24 Q〇23) The AV2 is related to the diffusion capacitor 3045, the liquid crystal capacitor 3044 and the storage capacitor 3043 between the gate and source of the thin film transistor 3041. The size is as follows: ΔΚ2 = (Vgh — VgL) X C3〇45 /(Q〇45 + Q〇44 + Q043) According to the present embodiment, the storage capacitor 3023 is a variable capacitor formed by an insulator-semiconductor structure as shown in FIG. 4A 16 200825592 (or Therefore, in the odd-numbered frame in which the positive polarity data is written, the voltage value of the positive polarity voltage data Vp written is greater than the applied bias value vbias', and P ^ is added to FIG. 4A. In the capacitor structure shown, the first metal layer is greater than the above-mentioned metal layer 4G2 Voltage, the voltage difference is positive value and is greater than a positive threshold voltage value (ν_). According to this embodiment, the storage capacitor 3〇23_, the capacitance value will be as shown in Fig. 4), so in the odd frame of the positive polarity tribute, the AVi value is as follows: ^.(-) = (^-rgJxC3025 / (C3025 + C3024 + C3023, on) In the even-numbered frame of the negative polarity data, at the beginning of the period T2, the potential of the scan line 306 rises to a high level, Vgh, thin film The crystal buckles 21 and 3041 are turned on, and the negative polarity voltage data transmitted on the data and line 3〇8 is assumed to be -vP, which will be respectively passed through the thin film transistors 3〇21 and 3〇4 to the liquid crystal capacitors 3〇24 and 3044, and The storage capacitors 3〇23 and 3〇43 are _charged. When the time period T is followed, the scan line potential drops to a low level = ' 'vgL 'thin film transistors 3021 and 3〇41 are turned off. At this time, the liquid crystal capacitor 3024 And the voltage across the 3044 is maintained by the storage capacitors 3〇23 and 3〇43. However, at the instant of the thin film transistor 3021 and 3〇4" skin cutoff, • the negative voltage data...V” will drop-AV value The magnitude of this Λν value and the diffusion capacitance, liquid crystal capacitance and storage between the gate and source of the thin film transistor According to the present embodiment, since the storage capacitor 3〇23 is a variable capacitor formed by a metal-insulator-semiconductor structure as shown in FIG. 4, = 17 200825592 Therefore, the second book goes to q Π 9 1 ^ ~ 'In the even frame of the negative polarity data, write: the voltage value of the negative voltage data - Vp is less than the applied bias voltage V -, : P is known to be added to the capacitor structure shown in Figure 4A On the first metal layer 4〇1: the voltage applied to the second metal layer 4〇2 by the magical field, so the voltage difference is 〖at the negative threshold voltage value (Vthc) d_ according to this embodiment, the storage capacitor. 23, the value of electricity will be the price (as shown in Figure 4B). Therefore, in the even frame of the negative polarity, the value of /^ is as follows: • δκι(〇#) . {Vgh ^l x /{c^ + ^ + ❿ 画 304 304, which is related to the expansion of the gate source 1 of the thin film transistor 3041, the liquid crystal capacitor 3044 and the storage capacitor 3043, the size of which is as follows: X C3045 /(C3045 +c3044 +c3043) % , because the storage capacitor 3023 in the secondary halogen 302 is a metal-insulator-semiconductor structure Therefore, for the secondary sputum 3 〇 2 and " write negative polarity tribute and write positive polarity data drop to produce a different voltage change, the capacitance value C_... is greater than, therefore, write positive polarity data • % voltage change The value ΔVl(10)) is smaller than the voltage change value AV1 (〇ff)° when the negative polarity data is written, and the storage capacitor 3043 in the secondary halogen 304 is a capacitance formed by the genus-insulator-metal structure, therefore, For the secondary pixels, the voltage change value is AV2 regardless of whether the negative polarity data or the positive polarity data is written. 18 200825592 According to this embodiment, the capacitance value of the diffusion capacitor 3025 is equal to the capacitance value of the diffusion capacitor 3045. The capacitance of the liquid crystal capacitor 3024 is equal to the capacitance of the liquid crystal capacitor 3044. The storage capacitor 3023 is a variable capacitor. When the positive polarity data is written, the capacitance value Cmmw of the storage capacitor 3023 is greater than the capacitance value of the storage capacitor 3043, and when the negative polarity data is written, the capacitance value C of the storage capacitor 3023 is added. / / will be smaller than the capacitance value of the storage capacitor 3043. Therefore, the magnitude relationship between the voltage change values is ΔMOffhADAMON). However, it is worth noting that although the capacitance value of the diffusion capacitor 3025 is equal to the capacitance of the diffusion capacitor 3045 The value, and the capacitance value of the liquid crystal capacitor 3024 is equal to the capacitance value of the liquid crystal capacitor 3044. However, the implementation of the present invention will not be limited thereto. Please refer to FIG. 6 again, since the storage capacitor 3023 is used as in 4A. The figure shows a variable capacitance formed by a metal-insulator-semiconductor structure. Therefore, in the case of the secondary halogen 302, at the moment when the thin film transistors 3021 and 3041 are turned off, the positive polarity data written and the written negative electrode are written. The data will produce different voltage change values, while the storage capacitor 3043 has a variable capacitance value. Therefore, in the case of the secondary halogen 304, at the moment when the thin film transistors 3021 and 3041 are cut off, The written positive polarity data and the written negative polarity data will produce the same voltage change value. Therefore, in the present embodiment, the variable storage capacitor 3023 can be adjusted to make the secondary halogen 302 and the secondary halogen 304, After the adjacent two frames are closed, the data voltages of the thin film transistors 3021 and 3041 are close to each other and symmetrical to the common voltage. That is, in the case of the secondary crystal 302, the data voltage V/, in the odd frame is equal to The data voltage of the frame is V;, e. For the case of the secondary halogen 304, the poor material voltage V σ in the odd frame is equal to the poor material in the even frame V & ^. 19 200825592 The optical characteristics can be evaluated by the Root Mean Square of the data voltage. However, the optical characteristics of the Vie 304 can be obtained by the data voltage and the secondary-hxj ϋ2 iSR A4- « = square root Therefore, the characteristics of the sub-pixel 302 are several
册S (次畫素302) = ^ZlKZ 次畫素304之光學特性為 舰S (次畫素304) = 根據本發明之第一實施例，每一個晝素中包含兩欠苎 素’因此整個畫素之光學特性是由兩次畫素各自之光學ς ，共同蚊。由於’本發明其中之—次晝素係使用可變電 容作為儲存電容，因此可藉由調整可變電容之I數值來使 得兩相鄰圖框於薄膜電晶體關閉後之資壓彼 共通電壓。如此，可避免因電壓之不對稱所造成之== 像。 值得注意的是，在第一實施例，如第3圖所示雖麸只 針對儲存電容3023引入可變電容，然而本發明當不以此為 限，在另一實施例中，亦可針對儲存電容3〇43引入可變電 容或於晝素中引入複數個可變電容等。另外，雖然在第一 實施例中，並未對偏壓值Vbias之值做限制，在另—實施例 中，偏壓值vbias之值亦可直接由Vc〇m提供。 第二實施例 20 200825592 參閱第7圖所示為根據本發明第一實施例的晝素單元 概略圖示。畫素單元700，包含兩次畫素702和704。 其中次晝素702包含一薄膜電晶體7021，其閘極連接 於掃描線706，汲極連接於資料線708，源極則連接於晝素 電極7022，其中晝素電極7022和一偏壓Vbi as構成儲存電 容7023 ’晝素電極7022和共通電極Vc〇m構成液晶電容 7024。 薄膜電晶體7021之源極和閘極間則具有一擴散電容 7025。 而次晝素704包含一薄膜電晶體7041，其閘極連接 於掃描線706，汲極連接於資料線708，而源極則連接於晝 素電極7042，其中晝素電極7042和偏壓Vbias構成儲存電 容7043’晝素電極7042和共通電極V_構成液晶電容 7044。 薄膜電晶體7041之源極和閘極間則具有一擴散電容 7045。 在本實施例中，儲存電容7023係採用金屬-絕緣體-半導體（MIS)之電容結構，而儲存電容7043則係採用金屬-絕緣體-金屬之電容結構。 本實施例中儲存電容7023之金屬-絕緣體-半導體之 電容結構可應用如第4A圖所示之電容結構，且其中電容值 與電壓值間之曲線圖亦如第4B圖所示。相似於第一實施例 所述，當電壓值大於一正門檀值（V thDd+ )或小於一負門植 值（VthcMi-)時，其電容值均會趨於一定值。於本實施例中， 以〇似，⑽代表，當兩者電壓差為正值且大於一正門檻值 (V thod + )時之電容值，並以C 7023, off 代表，當兩者電壓差為 負值且小於一負門檻值（Vf -)時之電容值。 本實施例與第一實施例最大之不同處在於，於第一實 施例中，儲存電容3023之第一金屬層是藉由一接觸孔與薄 21 200825592 膜電晶體3021之源極結構耦接，而形成儲存電容3〇23之 第二金屬層與偏壓Vfcias耦接。然而於第二實施例中，形成 儲存電容7023之第一金屬層其係與偏壓Vbus耦接，而形成 儲存電容7023之第二金屬層則與薄膜電晶體7〇21之源極 結構耦接。 本發明之晝素單元7〇〇可由多種不同之晝素結構加以 形成’第8A圖與第8B圖為多種畫素結構其中之一，且不 用以限制本發明之結構。其中第8A圖所示為根據第七圖中 次晝素702之薄膜電晶體7〇21與金屬—絕緣體—半導體儲存 電容7023之結構示意圖。而第8β圖所示則為次晝素7〇4 中之薄膜電晶體7041金屬-絕緣體—金屬儲存電容7〇43之 結構示意圖。值得注意的是，雖然第8A圖與第8B圖為了 說明目的而分開展示，但均係以同一製程程序加以完成。 首先請參閱第8A圖，次晝素702中，共通電極v⑽形 成於一玻璃基板810上，而薄膜電晶體7〇21與具金屬絕 緣體-半導體結構之儲存電容則共同形成在另一玻璃 基板800上。其中於玻璃基板8〇〇上具有一金屬層8〇2，分 別作為薄膜電晶體7〇21之閘極金屬層，以及儲存電容7〇23 之第-金屬層(即第4A圖中之第一金屬層樹)。_絕緣層 803形成於玻璃基板8GG上，用以覆蓋金屬層8()2，直中絕 緣層80S分別作為薄膜電晶體7〇2i之閘極絕緣層，二及儲 存電容7023之絕緣層（即第4入圖中之絕緣層4〇3)。一非 ，石夕層8G4以及-n+摻雜非晶料8()5依序且分別形成於 薄膜電晶體閘極絕緣層以及儲存電容絕緣層之上方，盆 非晶碎層804以及一 n+推雜非曰石々昆。Λ 、 雜非日日矽層805，係分別作為薄 22 200825592 膜電晶體7021之源極與汲極之半導體層，以及儲存電容 7023之半導體層（即第4A圖中之半導體層404)。接著一 金屬層806形成於薄膜電晶體7021之源極與汲極，以及儲 存電容7023半導體層之上方，其中金屬層806、非晶矽層 804以及n+摻雜非晶矽層805共同構成薄膜電晶體7021之 源極結構與汲極結構，同時金屬層806亦作為儲存電容 7023之第二金屬層（即第4A圖中之金屬層402)，值得注 意的是，在本實施例中，薄膜電晶體7021之源極結構與儲 存電容7023之第二金屬層相接，而薄膜電晶體7021之汲 極結構則耦接於 < 資料線。另外，一保護層807沉積於該 玻璃基板800之上，用以覆蓋薄膜電晶體7021之源極結 構、汲極結構以及儲存電容7023之第二金屬層，其中保護 層807具有接觸孔809以曝露出儲存電容7023之第二金屬 層上表面。然後一作為像素電極之銦錫氧化物（ITO)層808 形成於保護層807之上表面，以連接儲存電容7023之第二 金屬層，作為次晝素702之晝素電極7022。其中薄膜電晶 體7021中之源極電極以及閘極金屬層802共同構成擴散電 容7025。而玻璃基板810上之共通電極與銦錫氧化物 (ITO)層808構成液晶電容7024。 接著請參閱第8B圖，次晝素704中，共通電極形 成於一玻璃基板810上，而薄膜電晶體7041與具金屬-絕 緣體-金屬結構之儲存電容7043共同形成在另一玻璃基板 800上。其中於玻璃基板800上具有一金屬層802，分別作 為薄膜電晶體7041之閘極金屬層，以及儲存電容7043之 第一電極。一絕緣層803形成於玻璃基板800上，用以覆 23 200825592 蓋金屬層802，其中絕緣層803分別作為薄膜電晶體7041 之閘極絕緣層，以及儲存電容7043之絕緣層。一非晶矽層 804以及一 n+摻雜非晶矽層805依序形成於薄膜電晶體閘 極絕緣層上方，作為薄膜電晶體7041之源極與汲極之半導 體層。接著一金屬層806形成於薄膜電晶體7041之源極與 汲極，以及儲存電容7043絕緣層層之上方，其中金屬層 806、非晶矽層804以及n+摻雜非晶矽層805共同構成薄膜 電晶體7041之源極結構與汲極結構，同時金屬層806亦作 為儲存電容7043之第二電極。值得注意的是，在本實施例 中，薄膜電晶體7041之源極結構與儲存電容7043之第二 電極相接，而薄膜電晶體7041之汲極結構則耦接於一資料 線。另外，——保護層807沉積於該玻璃基板800之上，用 以覆盖薄膜電晶體7 0 41之源極結構、>及極結構以及儲存電 容7043之第二電極，其中保護層807具有接觸孔811以曝 露出儲存電容7043之第二電極上表面。然後一作為像素電 極之銦錫氧化物（ITO)層808形成於保護層807之上表面， 以連接儲存電容7043之第二電極。其中薄膜電晶體，7041 中之源極電極以及閘極金屬層802共同構成擴散電容 7045。而玻璃基板810上之共通電極Ve〇m與銦錫氧化物（ITO) 層808構成液晶電容7044。 參閱第9圖所示為根據本發明第二較佳實施例用以驅 動本發明晝素單元700之驅動波形圖，請同時參閱第7 圖。在一寫入正極性資料之奇數圖框中，在時段T!開始時， 掃描線706電位上升至一高位準狀態，Vgh，薄膜電晶體7021 以及7041被打開，資料線708上傳送之正極性電壓資料， 24 200825592 假設為Vp，會分別由經由薄膜電晶體7021及7041對液晶 電容7024和7044以及儲存電容7023和7043進行充電。 在時段T!終了時，掃描線706電位下降成一低位準狀態， ’薄膜電晶體7021及7041被截止。此時液晶電容7024 , 和7044兩端之電壓是藉由儲存電容7023和7043維持住。 但疋在薄膜電晶體7021及7041被截止之瞬間，正極性電 壓資料’ VP，會下降一 △ v值，此△ v值之大小與薄膜電晶 體之閘極源極間之擴散電容、液晶電容和儲存電容有關。 • 根據本發明之第二實施例，儲存電容7023係採用如第 4A圖所示由金屬—絕緣體—半導體結構所形成之可變電容 (或稱電壓控制電谷），因此，在寫入正極性資料之奇數圖 框中，其寫入之正極性電壓資料^之電壓值大於施加之偏 壓值Vbias，亦即，施加於第4A圖所示電容結構中第二金屬 層402上之電壓大於施加於第一金屬層4〇1上之電壓，因 此，因此電壓差為負值且小於負門檻電壓值（v^d )。依此 實施例，儲存電容7023之電容值將為…，因此在寫入 鲁 正極〖生資料之奇數圖框中，其△ V1值大小如下所述： 1 i°ff) - (Vgh -VgL)x c7025 /(C7025 + C7024 + C7023 〇#) ▲ 而△ 與溥膜電晶體7 〇 41之閘極源極間之擴散電容 • 7045、液晶電容7044和儲存電容7043有關，其大小如 ^ 所述： 八 卜 2 VgL ) X C7045 /(C7045 + C7044 + C7043) 25 200825592 在寫入負極性資料之偶數圖框中，在時段I開始時， 掃描線706電位上升至一高位準狀態，Vgh，薄膜電晶體7〇21 以及7041被打開，資料線708上傳送之負極性電壓資料， 假設為-VP，會分別由經由薄膜電晶體7〇21及7〇41對液晶 電容7024和7044以及儲存電容7023和7043進行充電。 在時段T2終了時，掃描線706電位下降成一低位準狀態， VgL薄膜龟曰曰體7021及7041被截止。此時液晶電容了 Q24 和7044兩端之電壓是藉由儲存電容7〇23和7〇43維持住。 但疋在薄膜電晶體7021及7041被截止之瞬間，負極性電 壓資料，-VP，會下降一值、此Δν值之大小與薄膜電晶 體之閘極源極間之擴散電容、液晶電容和儲存電容有關。 根據本實施例，由於儲存電容7〇23係採用如第41圖 所示由金屬-絕緣體—半導體結構所形成之可變電容，因 此，對次晝素702，在寫入負極性資料之偶數圖框中，其寫 入之負極性電壓資料之電壓值-Vp小於施加之偏壓值VbUs， 亦即’施加於第4A圖所示電容結構中第一金屬層401上之 电壓大於施加於第二金屬層402上之電壓，因此電壓差為 正值且大於正門檻電壓值（Vth^—)。依此實施例，儲存電容 7023之電容值將為，因此在寫入負極性資料之偶數 圖框中’其△ V 1值大小如下所述： AFj(on) - {Vgk *- VgL) x C7025 /(C7025 + C7024 + Clm 〇n) 而次晝素704，其與薄膜電晶體7041之閘極源極 間之擴散電容7045、液晶電容7044和儲存電容7043有關， 26 200825592 其大小如下所述： △F2 = (F於- X C7045 /(C7045 + C7044 + C7043) 由於次晝素702中之儲存電容7023係採用金屬-絕緣 體-半導體結構所形成之可變電容，因此，對次畫素702而 ^ 言，寫入負極性資料與寫入正極性資料降產生不同之電壓 變化，由於電容值C 7023, on 大於C 7023, off 5 因此，寫入負極性 U 資料時之電壓變化值△ l(ON)大於寫入正極性資料時之電 壓變化值(off )。而次畫素704中之儲存電容7043係 採用金屬-絕緣體-金屬結構所形成之電容，因此，對次晝 素704而言，不論是在寫入負極性資料或正極性資料時之 圖框，其電壓變化值均為△ V2。 根據本實施例，擴散電容7025之電容值等於擴散電容 7045之電容值。液晶電容7024之電容值等於液晶電容7044 之電容值。而儲存電容7023為一可變電容，在寫入正極性 資料時儲存電容7023之電容值Ο^小於儲存電容7043 _ 之電容值，而在寫入負極性資料時，儲存電容7023之電容 值Ο似，。〃將大於儲存電容7043之電容值。因此，電壓變化 請再次參閱第9圖所示，由於儲存電容7023是使用如 ’ 第4A圖所示由金屬-絕緣體-半導體結構所形成之可變電 、 容。因此就次畫素702而言，在薄膜電晶體7021及7041 被截止之瞬間，對寫入之正極性資料與寫入之負極性資料 將產生不同之電壓變化值。而儲存電容7043其電容值不可 27 200825592 變。因此就次畫素7Q4而古，為墙 、、 ^ ^ -在厚膜電晶體7021及7041 被截止之瞬間，對寫入之正極性眘粗 生貝科與寫入之負極性資料 將產生相同之電壓變化值。因此，在本實施例中，可藉由 調整可變儲存電容，使得次4素7Q2與次畫素 在相鄰兩圖框於薄膜電晶體順及7Q41截止後之資料電 塵彼此趨近對稱於共通電壓Vcm。亦即，就次畫素7〇2而+， 料圖框之資料電壓v“#於在偶圖框之資料電壓而 就次畫素704而言’在奇圖框之資料電壓u於在偶圖框 之資料電壓Vu。 -人畫素702之光學特性可藉由資料電壓以及 之均方根值（Root Mean Square)來加以評估。而次晝素 704之光學特性可藉由資料電壓v“以及1〇之均方根^來 加以評估。 因此’次晝素702之光學特性為 顧(次晝素702) = 次晝素/7〇4之光學特性為 _ (次晝素704)= 根據本發明之第二實施例，每一個晝素中包含兩次查 素，因此整個晝素之光學特性是由兩次畫素各自之光學特 性共同決定。由於，本發明其中之一次晝素係使用可變電 容作為儲存電容，因此可藉由調整可變電容之參數值來S 得兩相鄰圖框於薄膜電晶體截止後之資料電壓彼此對稱於 28 200825592 共通電壓。如此，可避免因電壓之不對稱所造成之殘影現 像0 同理’在第二實施例，如第7圖所示，雖然只針對儲 存電容7023引入可變電容，然而本發明當不以此為限，在 另一實施例中，亦可針對儲存電容7〇43引入可變電容或於 晝素中引入複數個可變電容等。另外，雖然在第二實施例 中，並未對偏壓值Vbias之值做限制，在另一實施例中，偏 壓值vbias之值亦可直接由Vcdib提供。Book S (sub-pixel 302) = ^ZlKZ sub-pixel 304 has the optical characteristic of ship S (sub-pixel 304) = according to the first embodiment of the present invention, each element contains two auxin' so the whole The optical properties of the pixels are the optical enthalpy of the two pixels, and the common mosquito. Since the nucleus of the present invention uses a variable capacitor as the storage capacitor, the I value of the variable capacitor can be adjusted to make the voltage of the two adjacent frames after the thin film transistor is turned off. In this way, the == image caused by the asymmetry of the voltage can be avoided. It should be noted that, in the first embodiment, as shown in FIG. 3, although the bran only introduces a variable capacitor for the storage capacitor 3023, the present invention is not limited thereto, and in another embodiment, it may also be for storage. The capacitor 3〇43 introduces a variable capacitor or introduces a plurality of variable capacitors and the like into the halogen. Further, although in the first embodiment, the value of the bias value Vbias is not limited, in another embodiment, the value of the bias value vbias may be directly provided by Vc〇m. Second Embodiment 20 200825592 Referring to Fig. 7, there is shown a schematic diagram of a pixel unit according to a first embodiment of the present invention. The pixel unit 700 includes two pixels 702 and 704. The secondary halogen 702 comprises a thin film transistor 7021 having a gate connected to the scan line 706, a drain connected to the data line 708, and a source connected to the halogen electrode 7022, wherein the halogen electrode 7022 and a bias voltage Vbi as The storage capacitor 7023's halogen electrode 7022 and the common electrode Vc〇m constitute a liquid crystal capacitor 7024. The thin film transistor 7021 has a diffusion capacitor 7025 between the source and the gate. The secondary halogen 704 comprises a thin film transistor 7041, the gate is connected to the scan line 706, the drain is connected to the data line 708, and the source is connected to the halogen electrode 7042, wherein the halogen electrode 7042 and the bias voltage Vbias are formed. The storage capacitor 7043' halogen electrode 7042 and the common electrode V_ constitute a liquid crystal capacitor 7044. The thin film transistor 7041 has a diffusion capacitor 7045 between the source and the gate. In the present embodiment, the storage capacitor 7023 is a metal-insulator-semiconductor (MIS) capacitor structure, and the storage capacitor 7043 is a metal-insulator-metal capacitor structure. In the capacitor structure of the metal-insulator-semiconductor of the storage capacitor 7023 in this embodiment, a capacitor structure as shown in Fig. 4A can be applied, and a graph between the capacitance value and the voltage value is also shown in Fig. 4B. Similar to the first embodiment, when the voltage value is greater than a positive gate value (V thDd + ) or less than a negative gate value (VthcMi-), the capacitance value tends to a certain value. In the present embodiment, (10) represents a capacitance value when the voltage difference between the two is positive and greater than a positive threshold (V thod + ), and is represented by C 7023, off when the voltage difference between the two is The value of the capacitor when it is negative and less than a negative threshold (Vf -). The first difference between this embodiment and the first embodiment is that, in the first embodiment, the first metal layer of the storage capacitor 3023 is coupled to the source structure of the thin film 200825592 membrane transistor 3021 by a contact hole. The second metal layer forming the storage capacitor 3〇23 is coupled to the bias voltage Vfcias. However, in the second embodiment, the first metal layer forming the storage capacitor 7023 is coupled to the bias voltage Vbus, and the second metal layer forming the storage capacitor 7023 is coupled to the source structure of the thin film transistor 7〇21. . The halogen unit 7 of the present invention can be formed by a plurality of different halogen structures. Figs. 8A and 8B are one of a plurality of pixel structures, and are not intended to limit the structure of the present invention. FIG. 8A is a schematic view showing the structure of the thin film transistor 7〇21 and the metal-insulator-semiconductor storage capacitor 7023 according to the seventh pixel in the seventh figure. The figure 8β shows the structure of the thin film transistor 7041 metal-insulator-metal storage capacitor 7〇43 in the secondary halogen 7〇4. It is worth noting that although Figures 8A and 8B are shown separately for illustrative purposes, they are all performed in the same process. Referring first to FIG. 8A, in the secondary 702, the common electrode v(10) is formed on a glass substrate 810, and the thin film transistor 7〇21 and the storage capacitor having the metal insulator-semiconductor structure are formed together on the other glass substrate 800. on. There is a metal layer 8〇2 on the glass substrate 8〇〇, which is respectively used as a gate metal layer of the thin film transistor 7〇21, and a first metal layer of the storage capacitor 7〇23 (ie, the first in FIG. 4A) Metal layer tree). The insulating layer 803 is formed on the glass substrate 8GG for covering the metal layer 8() 2, and the straight insulating layer 80S is used as the gate insulating layer of the thin film transistor 7〇2i, respectively, and the insulating layer of the storage capacitor 7023 (ie, Insulation layer 4〇3) in the fourth figure. A non-stone layer 8G4 and -n+ doped amorphous material 8 () 5 are sequentially formed on the thin film transistor gate insulating layer and the storage capacitor insulating layer, respectively, the basin amorphous layer 804 and an n+ push Miscellaneous non-曰石々昆. The Λ and 非 日 805 805 layers are respectively a semiconductor layer of the source and the drain of the thin film 2272125, and a semiconductor layer of the storage capacitor 7023 (ie, the semiconductor layer 404 in FIG. 4A). A metal layer 806 is formed over the source and drain of the thin film transistor 7021 and over the semiconductor layer of the storage capacitor 7023. The metal layer 806, the amorphous germanium layer 804, and the n+ doped amorphous germanium layer 805 together form a thin film The source structure and the drain structure of the crystal 7021, and the metal layer 806 also serves as the second metal layer of the storage capacitor 7023 (ie, the metal layer 402 in FIG. 4A). It is noted that in this embodiment, the thin film is electrically The source structure of the crystal 7021 is connected to the second metal layer of the storage capacitor 7023, and the drain structure of the thin film transistor 7021 is coupled to the < In addition, a protective layer 807 is deposited on the glass substrate 800 for covering the source structure of the thin film transistor 7021, the drain structure, and the second metal layer of the storage capacitor 7023. The protective layer 807 has a contact hole 809 for exposure. The upper surface of the second metal layer of the storage capacitor 7023 is discharged. Then, an indium tin oxide (ITO) layer 808 as a pixel electrode is formed on the upper surface of the protective layer 807 to connect the second metal layer of the storage capacitor 7023 as the halogen electrode 7022 of the secondary halogen 702. The source electrode and the gate metal layer 802 in the thin film transistor 7021 collectively constitute a diffusion capacitor 7025. The common electrode on the glass substrate 810 and the indium tin oxide (ITO) layer 808 constitute a liquid crystal capacitor 7024. Next, referring to Fig. 8B, in the secondary 704, the common electrode is formed on a glass substrate 810, and the thin film transistor 7041 is formed on the other glass substrate 800 together with the metal-insulator-metal structure storage capacitor 7043. The metal substrate 800 has a metal layer 802 as a gate metal layer of the thin film transistor 7041 and a first electrode of the storage capacitor 7043. An insulating layer 803 is formed on the glass substrate 800 for covering the cover layer 802 of the 200825592, wherein the insulating layer 803 serves as a gate insulating layer of the thin film transistor 7041 and an insulating layer of the storage capacitor 7043, respectively. An amorphous germanium layer 804 and an n+ doped amorphous germanium layer 805 are sequentially formed over the thin film transistor gate insulating layer as a source and drain semiconductor layer of the thin film transistor 7041. A metal layer 806 is formed over the source and drain of the thin film transistor 7041 and over the insulating layer of the storage capacitor 7043. The metal layer 806, the amorphous germanium layer 804, and the n+ doped amorphous germanium layer 805 together form a thin film. The source structure and the drain structure of the transistor 7041, and the metal layer 806 also serves as the second electrode of the storage capacitor 7043. It should be noted that, in this embodiment, the source structure of the thin film transistor 7041 is connected to the second electrode of the storage capacitor 7043, and the drain structure of the thin film transistor 7041 is coupled to a data line. In addition, a protective layer 807 is deposited on the glass substrate 800 to cover the source structure of the thin film transistor 7041, and the second structure of the electrode structure and the storage capacitor 7043, wherein the protective layer 807 has contact. The hole 811 exposes the upper surface of the second electrode of the storage capacitor 7043. Then, an indium tin oxide (ITO) layer 808 as a pixel electrode is formed on the upper surface of the protective layer 807 to connect the second electrode of the storage capacitor 7043. The thin film transistor, the source electrode of the 7041, and the gate metal layer 802 together form a diffusion capacitor 7045. The common electrode Ve〇m and the indium tin oxide (ITO) layer 808 on the glass substrate 810 constitute a liquid crystal capacitor 7044. Referring to Fig. 9, there is shown a driving waveform diagram for driving the halogen unit 700 of the present invention in accordance with a second preferred embodiment of the present invention. Please also refer to Fig. 7. In an odd-numbered frame in which the positive polarity data is written, at the beginning of the period T!, the potential of the scanning line 706 rises to a high level state, Vgh, the thin film transistors 7021 and 7041 are turned on, and the positive polarity is transmitted on the data line 708. Voltage data, 24 200825592 Assuming Vp, liquid crystal capacitors 7024 and 7044 and storage capacitors 7023 and 7043 are charged via thin film transistors 7021 and 7041, respectively. At the end of the period T!, the potential of the scan line 706 drops to a low level state, and the thin film transistors 7021 and 7041 are turned off. At this time, the voltage across the liquid crystal capacitors 7024, and 7044 is maintained by the storage capacitors 7023 and 7043. However, at the moment when the thin film transistors 7021 and 7041 are turned off, the positive polarity voltage data 'VP' will drop by a value of Δv, and the magnitude of the Δv value and the diffusion capacitance between the gate source of the thin film transistor and the liquid crystal capacitor It is related to the storage capacitor. According to the second embodiment of the present invention, the storage capacitor 7023 is a variable capacitor (or voltage-controlled electric valley) formed of a metal-insulator-semiconductor structure as shown in FIG. 4A, and therefore, a positive polarity is written. In the odd-numbered frame of the data, the voltage value of the positive polarity voltage data written is greater than the applied bias voltage value Vbias, that is, the voltage applied to the second metal layer 402 in the capacitor structure shown in FIG. 4A is greater than the applied voltage. The voltage on the first metal layer 4〇1, therefore, the voltage difference is therefore negative and less than the negative threshold voltage value (v^d). According to this embodiment, the capacitance value of the storage capacitor 7023 will be..., so in the odd-numbered frame of the raw data, the ΔV1 value is as follows: 1 i°ff) - (Vgh -VgL) x c7025 /(C7025 + C7024 + C7023 〇#) ▲ and △ is related to the diffusion capacitance of the gate source of the 溥 film transistor 7 〇41 • 7045, liquid crystal capacitor 7044 and storage capacitor 7043, the size is as described in ^ : 八卜2 VgL ) X C7045 /(C7045 + C7044 + C7043) 25 200825592 In the even frame of the negative polarity data, at the beginning of the period I, the potential of the scanning line 706 rises to a high level state, Vgh, film The transistors 7〇21 and 7041 are turned on, and the negative voltage data transmitted on the data line 708, assuming -VP, will be respectively passed through the thin film transistors 7〇21 and 7〇41 to the liquid crystal capacitors 7024 and 7044 and the storage capacitor 7023. Charge with 7043. At the end of the period T2, the potential of the scanning line 706 drops to a low level state, and the VgL film turtle bodies 7021 and 7041 are turned off. At this time, the voltage across the liquid crystal capacitors Q24 and 7044 is maintained by the storage capacitors 7〇23 and 7〇43. However, at the moment when the thin film transistors 7021 and 7041 are cut off, the negative voltage data, -VP, will decrease by a value, the magnitude of the Δν value and the diffusion capacitance between the gate source of the thin film transistor, the liquid crystal capacitance and the storage. Capacitance related. According to the present embodiment, since the storage capacitor 7 〇 23 is a variable capacitor formed by a metal-insulator-semiconductor structure as shown in FIG. 41, the even-numbered map of the negative polarity data is written to the secondary 702. In the frame, the voltage value -Vp of the written negative voltage data is smaller than the applied bias value VbUs, that is, the voltage applied to the first metal layer 401 in the capacitor structure shown in FIG. 4A is greater than the second applied to the second The voltage on the metal layer 402, and therefore the voltage difference is positive and greater than the positive threshold voltage value (Vth^-). According to this embodiment, the capacitance value of the storage capacitor 7023 will be, so in the even frame of the negative polarity data, the value of ΔV 1 is as follows: AFj(on) - {Vgk *- VgL) x C7025 /(C7025 + C7024 + Clm 〇n) and the halogen 704, which is related to the diffusion capacitance 7045, the liquid crystal capacitor 7044 and the storage capacitor 7043 between the gate and source of the thin film transistor 7041, 26 200825592 The size is as follows: ΔF2 = (F in - X C7045 / (C7045 + C7044 + C7043) Since the storage capacitor 7023 in the secondary halogen 702 is a variable capacitance formed by a metal-insulator-semiconductor structure, therefore, for the sub-pixel 702 ^ 言, write negative polarity data and write positive polarity data drop to produce a different voltage change, because the capacitance value C 7023, on is greater than C 7023, off 5 Therefore, the voltage change value △ l when writing negative polarity U data ( ON) is greater than the voltage change value (off) when the positive polarity data is written. The storage capacitor 7043 in the secondary pixel 704 is a capacitor formed by a metal-insulator-metal structure, and therefore, for the secondary halogen 704, Whether it is when writing negative or positive data The voltage change value of the frame is ΔV2. According to the embodiment, the capacitance value of the diffusion capacitor 7025 is equal to the capacitance value of the diffusion capacitor 7045. The capacitance value of the liquid crystal capacitor 7024 is equal to the capacitance value of the liquid crystal capacitor 7044. The storage capacitor 7023 is a The variable capacitance, when the positive polarity data is written, the capacitance value of the storage capacitor 7023 is smaller than the capacitance value of the storage capacitor 7043 _, and when the negative polarity data is written, the capacitance value of the storage capacitor 7023 is similar, and 〃 will be greater than The capacitance value of the storage capacitor 7043 is stored. Therefore, please refer to FIG. 9 again for the voltage change, since the storage capacitor 7023 is a variable electric current formed by a metal-insulator-semiconductor structure as shown in FIG. 4A. For the sub-pixel 702, when the thin film transistors 7021 and 7041 are turned off, the positive polarity data written and the negative polarity data written will have different voltage change values. The storage capacitor 7043 has a non-capacitance value. 27 200825592 Change. Therefore, the sub-pixel 7Q4 is ancient, for the wall, ^ ^ - at the moment when the thick-film transistors 7021 and 7041 are cut off, the positive polarity of the writing is carefully written and written. The polarity data will produce the same voltage change value. Therefore, in this embodiment, the variable storage capacitor can be adjusted so that the secondary 4Q2 and the sub-pixel are in the adjacent two frames in the thin film transistor and the 7Q41 cut-off. After the data, the electric dust approaches each other symmetrically to the common voltage Vcm. That is, for the sub-pixels 7〇2 and +, the data voltage of the material frame v “# is in the data voltage of the even frame and the pixel 704 For example, the data voltage u in the odd frame is the data voltage Vu in the even frame. The optical properties of the human pixel 702 can be evaluated by the data voltage and the Root Mean Square. The optical properties of the secondary 704 can be evaluated by the data voltage v "and the rms of 1 。 ^. Therefore, the optical characteristic of the secondary 702 is 顾 (subsequent 702) = secondary / / 7 The optical characteristic of 〇4 is _ (sub-halogen 704) = According to the second embodiment of the present invention, each element contains two elements, so that the optical properties of the entire element are the optics of the two pixels. The characteristics are determined jointly. Since one of the halogens of the present invention uses a variable capacitor as the storage capacitor, the parameter voltage of the variable capacitor can be adjusted to obtain the data voltage of the two adjacent frames after the thin film transistor is turned off. Symmetrical to each other, the common voltage of 28 200825592. In this way, the residual image caused by the asymmetry of the voltage can be avoided. Similarly, in the second embodiment, as shown in FIG. 7, although the variable capacitance is introduced only for the storage capacitor 7023. However, the present invention is not limited thereto. In another embodiment, a variable capacitor may be introduced for the storage capacitor 7〇43 or a plurality of variable capacitors may be introduced into the pixel. In addition, although in the second implementation In the example, there is no bias value Vbias The value is limited. In another embodiment, the value of the bias value vbias can also be directly provided by Vcdib.
綜合上述所言，本發明藉由將一畫素單元區隔成兩次 旦素，而每一次晝素中包含獨立之薄膜電晶體、液晶電容 與儲存包令，且其中至少一儲存電容係採用可變電容（或電 ，控制電容），藉由可變電容之電容特性，在相鄰兩圖框時 段中，當對應之薄膜電晶體關閉時可使得資料電壓產生不 同私度之電壓k化’藉以讓變化後之資料電壓趨近對稱於 共通電壓，而解決影像殘留之問題。 雖然本發明已以數個實施例揭 _，，，aπ山，阶丹亚非用 限定本發明’任何孰習π姑藐本 u…、為此技藝者，在不脫離本發明 圍内’當可作各種之更動與潤飾，因此本發明之： 範圍當視後附之巾請專利範圍所界定者為準。 ’、 29 200825592 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之詳細說明如下： 第1圖為一垂直排列向列型彩色液晶顯示器，其穿透 率-電壓曲線圖。 第2圖為一垂直排列向列型彩色液晶顯示器，其包含 兩組伽瑪曲線之穿透率—電壓曲線圖。 第3圖係為本發明第一實施例的晝素單元概略圖示。In summary, the present invention comprises a separate pixel transistor, a liquid crystal capacitor and a storage package in each pixel by dividing a pixel unit into two densities, and at least one of the storage capacitors is used. Variable capacitance (or electric, control capacitor), by the capacitance characteristics of the variable capacitor, in the adjacent two frame periods, when the corresponding thin film transistor is turned off, the voltage of the data voltage can be generated with different degrees of privacy. In order to make the changed data voltage close to the common voltage, the problem of image sticking is solved. Although the present invention has been disclosed in a number of embodiments, aπ山, 代丹亚非用的发明's any π π 藐 u 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 Various changes and modifications may be made, and thus the scope of the invention is as defined in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; Type color liquid crystal display, its transmittance-voltage curve. Figure 2 is a vertical alignment nematic color liquid crystal display comprising a set of transmittance-voltage graphs of two sets of gamma curves. Fig. 3 is a schematic illustration of a halogen unit according to a first embodiment of the present invention.
第4A圖所示為根據本發明實施例之金屬—絕緣體一半 導體電容之結構示意圖。 第4B圖所不為根據本發明實施例之金屬—絕緣體一半 導體電容之電容-電壓曲線圖。 · 第5A圖所示為根據本發明第一實施例之薄膜電晶體 與金屬，-絕緣體-半導體儲存電容之結構示意圖。 第5B圖所示為根據本發明第_實施例之薄膜電晶體 與金屬-絕緣體-金屬儲存電容之結構示意圖。 第6圖所TF.為根據本發明—較佳實施例用以驅動本發 明晝素單元之驅動波形圖。 $ 7圖係為本發明第二實施例的晝素單元概略圖示。 =8A圖所示為根據本發明第二實施例之薄膜電晶體 與絕緣體-半導體儲存電容之結構示意圖。 弟8B圖所示為根據本-每 月弟一灵施例之溥膜電晶體 ”金ir緣體—金屬儲存電容之結構示意圖。 ，據本發明第二實施例用以驅動本發明 畫素早凡之驅動波形圖。 + k 71 30 200825592 【主要元件符號說明】 100區域 101、102、201 和 202 虛線 203實線 300和700晝素單元 302、304、702 和 704 次畫素 3021、 7021、3041和7041薄膜電晶體 3022、 7022、3042 和 7042 畫素電極 3023、 7023、3043 和 7043 儲存電容 3024、 7024、3044 和 7044 液晶電容 3025、 7025、3045 和 7045 擴散電容 306和706掃描線 308和708資料線 500、510、800和810玻璃基板 502、506、802 和 806 金屬層 503和803絕緣層 5 0 4和8 0 4非晶石夕層 505和805 n+摻雜非晶矽層 507和807 保護層 508和808銦錫氧化物（ITO)層 509、511、512、513、809 和 811 接觸孔 31Fig. 4A is a view showing the structure of a metal-insulator half conductor capacitor according to an embodiment of the present invention. Figure 4B is a graph showing the capacitance-voltage curve of a metal-insulator half conductor capacitance in accordance with an embodiment of the present invention. Fig. 5A is a view showing the structure of a thin film transistor and a metal-insulator-semiconductor storage capacitor in accordance with a first embodiment of the present invention. Fig. 5B is a view showing the structure of a thin film transistor and a metal-insulator-metal storage capacitor according to the first embodiment of the present invention. Figure 6 is a diagram showing driving waveforms for driving the pixel unit of the present invention in accordance with the present invention. The $7 diagram is a schematic illustration of the pixel unit of the second embodiment of the present invention. Figure 8 is a schematic view showing the structure of a thin film transistor and an insulator-semiconductor storage capacitor in accordance with a second embodiment of the present invention. Figure 8B is a schematic view showing the structure of a 溥 film transistor "gold ir edge body-metal storage capacitor" according to the present embodiment of the present invention. The second embodiment of the present invention is used to drive the pixel of the present invention. Driving waveform diagram + k 71 30 200825592 [Description of main component symbols] 100 regions 101, 102, 201 and 202 Dotted line 203 solid line 300 and 700 pixel units 302, 304, 702 and 704 sub-pixels 3021, 7021, 3041 And 7041 thin film transistors 3022, 7022, 3042, and 7042 pixel electrodes 3023, 7023, 3043, and 7043 storage capacitors 3024, 7024, 3044, and 7044 liquid crystal capacitors 3025, 7025, 3045, and 7045 diffusion capacitors 306 and 706 scan lines 308 and 708 Data lines 500, 510, 800, and 810 glass substrates 502, 506, 802, and 806 metal layers 503 and 803 insulating layers 504 and 804 amorphous slabs 505 and 805 n+ doped amorphous layers 507 and 807 Protective layer 508 and 808 indium tin oxide (ITO) layers 509, 511, 512, 513, 809 and 811 contact holes 31