200822133 九、發明說明： 【發明所屬之技術領域】 本u般係關於可卸除式非揮發性記憶體裝置裝置之 使用及結構，特定言之，係關於具有用以與其他電子系統 連接的標準化介面。 _ 【先前技術】 依據若干熟知的標準，已採用商用方式實施包含非揮發 性記憶卡的電子電路卡。記憶卡係與個人電腦、行動電 f 話、個人數位助理（PDA)、數位相機、數位攝影機、可攜 式音訊播放器及其他主機電子裝置使用，以儲存大量資 料。此類卡通常包含-可重新程式化非揮發性半導體記憶 體單元陣列連同一控制器，其控制該記憶體單元陣列之操 作且與該卡連接的一主機介接。若干同一類型的卡可在設 計用以接受該類型卡的主機卡槽中互換。然而，許多電子 卡標準的發展已產生不同類型的卡，其在各種程度上彼此 不相容。依據一標準所製造的卡通常不可與設計成採用另 ^ 一個標準之卡操作的主機使用。記憶卡標準包含PC卡'200822133 IX. Description of the Invention: [Technical Field of the Invention] The use and structure of a removable non-volatile memory device device, in particular, is related to standardization for connection with other electronic systems. interface. _ [Prior Art] Electronic circuit cards containing non-volatile memory cards have been implemented commercially in accordance with a number of well-known standards. Memory cards are used with personal computers, mobile phones, personal digital assistants (PDAs), digital cameras, digital cameras, portable audio players, and other host electronics to store large amounts of data. Such cards typically include a reprogrammable non-volatile semiconductor memory cell array coupled to the same controller that controls the operation of the memory cell array and interfaces with a host to which the card is connected. Several cards of the same type can be interchanged in a host card slot designed to accept this type of card. However, the development of many electronic card standards has produced different types of cards that are incompatible with each other to varying degrees. Cards manufactured in accordance with a standard are generally not available for use with a host designed to operate with another standard card. Memory card standard includes PC card'
CompactFlash™卡（CFTM卡）、SmanMediaTM卡多媒體卡 (MMC™)、安全數位（SD)卡、miniSDTM+、用戶識別模組 (SIM)、Memory Stick™、Mem〇ry SUck Du〇 卡及CompactFlashTM card (CFTM card), SmanMediaTM card multimedia card (MMCTM), secure digital (SD) card, miniSDTM+, Subscriber Identity Module (SIM), Memory StickTM, Mem〇ry SUck Du〇 card and
TransFlash™記憶體模組標準。亦已使小型、手持式可重 斤矛σ式化非揮土性s己憶體透過通用串列匯流排（Usb)連接 器與一電腦或其他類型的主機介接。市面上可買到若干有 SanD1Sk公司之商標"Cruzer(g)"的USB快閃驅動器產品。 124724.doc 200822133 USB快閃驅動器通常較大且形狀不同於以上說明的記憶 卡。 兩種通用記憶體單元陣列架構已得到商業應用，即N〇R 與NAND。在典型的n〇R陣列中，記憶體單元係連接於相 鄰的位元線源極與汲極擴散之間，汲極擴散會在行方向上 延伸’其中控制閘極係連接至沿單元列延伸的字線。一記 U體單元包括至少一儲存元件’其位於該源極與沒極之間 的單元通道區域之至少一部分之上。儲存元件上的一程式 化電荷位準因而控制該等單元的一操作特徵，該等單元可 藉由向已定址的記憶體單元施加適當的電壓來讀取。此類 單元之範例、其於記憶體系統中的用途及其製造方法係提 仏於下列美國專利第 5,〇7〇,〇32 ; 5,〇95,344 ; 5,3 13,421 ; 5,315’541 , 5,343,063 ; 5,661，053及 6,222,762號中。 NAND陣列利用兩個以上記憶體單元（例如“或”個）之 串聯字串’其連同一或多個選擇電晶體連接在個別位元線 與一參考電位之間以形成單元行。字線會橫跨大量此等行 内的單70而延伸。藉由使該字串中的剩餘單元硬開啟以便 机過一子串的電流取決於儲存在已定址單元中之電荷位 準而在私式化期間項取並驗證一行内的一個別單元。作 為一記憶體系統之-部分的NAND架構陣列及其操作之範 例係見於美國專利第 5,57G，315; 5,774,397; M46,935; 6,456,528及 6,522,580號。 如先月il所引用之專利案中所論述，目前快閃陣 列的電荷儲存元件係最常見料電浮動閘極，冑常由導電 124724.doc 200822133 “的多sa ♦材料所形成。可用於快閃系統之一 替代類型之把憶體單元利用_非導電介電材料替代該導電 浮動間極來以轉純方切存電荷。在-範财，由氧 化石夕、氮化石夕及氧化石夕（〇N〇)所形成的三層介電質係夾置 於—導電控制閘極與記憶體單元通道上方的—半導電基板 表，之間。藉由將電子從單元通道注人該氮化物而程式化 該單元’在該氮化物中該等電子受到截獲並儲存於一受限 區域中，並藉由將熱電洞注人該氮化物而加以抹除。數種 知用介電儲存兀件的特定單元結構與陣列係說明於美國專 利第6,925,007號中。 =別快閃EEPR0M^在—電荷儲存元件或單元中儲存 一疋數量的電荷（其代表一或多個位元的資料卜一儲存元 件之電荷位準控制其記憶體單元的臨界電壓（一般引用為 v广其係用作讀取單元之儲存狀態的一依據。通常將一 臨界電壓視窗分成若干範圍，記憶體單元之兩個或兩個以 上儲存狀態之每個狀態對應一範圍。此等範圍係由保護帶 分開，此等保護帶包括一標稱感測位準，其允許決定個別 單元之儲存狀態。Λ等儲存位準確實會由於干擾在相鄰或 其他相關記憶體單元、頁或區塊内所執行的程式化、讀取 或抹除操作之電荷而偏移。因此，一般藉由控制器來計算 錯誤校正碼（ECC)，並將其與所程式化的主機資料一起儲 存，且在讀取期間用以驗證資料並必要時執行某一位準的 貧料校正。 典型快閃EEPROM陣列的記憶體單元係分成一起抹除的 124724.doc 200822133 早疋之離散區塊。即，區塊（抹除區塊）係抹除單元，即可 同時抹除的最小單元數目。每個抹除區塊一般儲存一或多 個資料頁，該頁係程式化及讀取的最小單元，但是在不同 的子陣列或平面中可平行地程式化或讀取一頁以上。各頁 • 一般儲存一或多個資料區段，區段之大小係由主機系統來 定義。一範例性區段遵循一針對磁碟機所建立的標準，包 括5 12位元組的主機資料，加上關於主機資料及/或儲存其 f) <抹除區塊的若干位元組管理資訊。此類記憶體一般在每 個抹除區塊内組態16、32或更多頁，且每個頁儲存一或多 個區段的主機資料。主機資料可包括來自一在主機上運轉 的應用程式之使用者資料與主機在管理記憶體所產生的資 料（例如FAT(檔案配置表））以及目錄資料。 一般而言一記憶體陣列係於一晶粒（”記憶體晶粒，，或，，晶 片）上形成，該晶粒亦可具有連接至該記憶體陣列之周邊 電路。周邊電路之範例包含列與行控制電路、暫存器、狀 〇 態機、電荷幫浦，以及與讀取、寫入及抹除一記憶體陣列 中之資料相關聯的其他電路。 一圮憶體控制器可具有包含一中央處理單元（CPU)、一 . 緩衝區快取（緩衝區RAM)及一 CPU RAM之若干組件。緩衝 • 區RAMC及CPU RAM兩者可為SRAM記憶體。此等組件可在 相同晶粒或分離晶粒上。該CPU係一微處理器，其運轉軟 體（韌體）以實現包含使資料轉移至及自該記憶體陣列之操 作。在美國專利第5,297,148號（其全部以引用的方式併入 本文中）所示的一範例中，一緩衝區快取可用以當作一寫 124724.doc 200822133 以減少磨損用於當作一非揮發性記憶體Η ==電路⑽），使得—單_積體電路（控制器晶粒 或曰曰片）執行所有記憶體控制器功能。 某些C憶卡可與並非永遠使用相同標準之不同主機使 用例如，某些主機可提供3.3伏特之功率給~記憶卡， 而-他可提供1.8伏特之功率。以兩個不同電壓位準供應 之主機功率操作之卡可視為雙電壓記憶卡。 u f Ο 圖1顯不先前技術的一雙電壓記憶卡1〇〇，其具有連接至 :雙電壓記憶體晶粒1()4的一雙電壓控制器晶粒1〇2。控制 裔曰曰粒1G2及記憶體晶粒1()4兩者接收其來自—主機透過一 共同接點106並在-該主機所供應之電壓％的功率。無論 4主機提供3·3伏特或18伏特之％，在控制器晶粒1们及 記憶體晶粒104兩者之内部電路允許每―^粒進行操作。 圖1中亦顯示-共同接地接點1〇8，其提供一接地電壓Vss 、、口該控制器晶粒及该記憶體晶粒兩者。此外，提供接點 11 〇a至d，用於資料、命令及狀態資訊之交換。 【發明内容】 根據本發明之一具體實施例，一記憶體晶粒之電壓調節 係由與該記憶體晶粒分離的一電壓調節電路所執行。當主 機提供兩個或兩個以上不同電壓之任一者之功率給該卡 時，該電壓調節電路提供一所要求電壓之功率給該記憶體 晶粒。因此，不再要求一雙電壓記憶體晶粒。可使用僅以 一單一功率電壓運作的一記憶體晶粒。此類晶粒一般而言 124724.doc -10- 200822133 較雙電壓記憶體晶粒更便宜而且更小。雖然該電壓調節電 路提供功率給該記憶體晶粒，但該記憶體控制器可直接接 收來自該主機並在一取決於該主機之電壓的功率。於一具 體實施例中電壓調節電路提供與該輸人電壓相同或低 於該輸入電壓的一輸出電壓。另一具體實施例中，一電壓 調節電路提供與該輸入電壓相同或高於該輸入電壓的一輸 出。 Ο 在某些記憶體系統中，對於一控制器晶粒内之不同電 路，該控制器晶粒接收不同電壓位準之不同電源供應。例 如對於主機介面電路’可在—第—電壓位準提供—電源供 應，對於控制ϋ核心、電路，亦可在該第—電壓位準提供另 一電源供應，而且對於記憶體介面電路，可在一第二電壓 位準提供又另一供應。於一範例中，該第一電壓位準係接 收自該主機之電壓位準’而該第二電壓位準係由該記憶卡 内的-電壓調節電路所提供。該電壓調節電路可與該控制 器晶粒及該記憶體晶粒兩者分離，或者可位於該控制器晶 粒中。該記憶體晶粒之不同部分亦可具有不同電源供應， 但此等部分-般而言具備與該電壓調節電路所提供相同之 電壓位準的功率。 本發明之各方面的額外方面、優點、特徵及細節係包含 在以下其示範性具體實施例之說明中，應結合附圖來進行 該說明。 【實施方式】 圖2顯示根據本發明之-具體實施例的—雙電壓記憶卡 124724.doc 11 200822133 雙電壓記憶卡212包含一根據用以連接至各式各樣主 機之一標準的實體介面214。實體介面214包含個別接點 2〇6 208、21〇a至d，其與一主機插座中之對應接點連 接。提供接點206、208、21(^至（1以便交換資料，而且亦 . 帛以提供功率給記憶卡212。尤其，提供一電源供應接點 2〇6，其連接至該主機插座中的一電源供應接點。將該主 機供應給電源供應接點206之電壓指定為Vdd。不同主機可 《 提供不同電壓位準之功率。所以取決於記憶卡212連接至 何種主機，VDD可具有兩個或兩個以上不同位準。尤其， 忑隐卡2 12係設計成與提供兩個預定電壓位準之功率的主 機操作。其他情況中，可將卡設計成在三或多個電壓位準 操作，或者在電壓位準的一寬範圍中操作。除了該電源供 應接點206外，一接地接點2〇8提供從該主機至記憶卡η] 並在一指定為Vss之電壓的一接地連接。 記憶卡212包含藉由形成一資料匯流排2 2 〇之多重導體而 V 連接在一起的一控制器晶粒216及一記憶體晶粒218。於其 他記憶卡中，可存在額外晶粒。例如，可提供多重記憶體 晶粒。同時，一控制器可包括執行不同控制器功能的兩個 伽以上晶粒，取代在一單一控制器晶粒執行所有控制 器功能。 除了提供控制器晶粒216及記憶體晶粒218外，亦提供— 電塵調節電路222,該電麼調節電路222供應—已調節電塵 給記憶體晶粒218。電壓調節電路222接收來自電源供應接 點206在兩個或兩個以上不同電壓位準之一者的一輸入電 124724.doc -12 - 200822133 壓，而且電壓調即電路222提供一在非取決於該輸入電壓 之固疋電壓的一電壓輸出。因此，可將記憶卡連接至 提供不同電壓位準之功率的主機，但記憶體晶粒218接收 之電壓位準係由電壓調節電路222加以調節，使得記憶體 曰曰粒218未必為一雙電壓記憶體晶粒。此可提供節省成 本、即省空間，而且亦較通常可能使用一雙電壓記憶體晶 粒具有更多設計彈性。 圖3A顯示本發明之一具體實施例的一較詳細圖式。圖 3A顯示一雙電壓控制器晶粒332，其具有三個不同部分 332a至c，其各具有一分離功率輸入。一主機輸入/輸出部 分332a係連接至與一主機連接的一實體介面^斗。因此， 到達及來自該主機之信號通過主機輸入/輸出部分Μ。。 主機輸入/輸出部分332a接收經連接至一功率輸入接點336 的一電源供應335。因此，一主機輸入/輸出部分33。接收 在一電壓vDD之功率，該電壓Vdd係該主機提供給記憶卡 330之電壓，取決於記憶卡33〇連接之主機，其可在不同位 準。 一控制器核心部分332b含有管理記憶卡33〇與該主機間 之資料交換及管理記憶卡330内之資料的電路。控制器核 心部分332b接收經連接至功率輸入接點336的一電源供靡 338。因此，控制器核心部分33孔接收在一電壓v如之功 率，該電壓VDD係該主機提供給記憶卡330之電壓，取決於 。己憶卡330連接之主機，其可在不同電壓位準。 控制器晶粒332的一記憶體輸入/輸出部分332(：係藉由形 124724.doc • 13 · 200822133 成一匯流排342之多重導體而連接至記憶體晶粒34〇。記憶 體輸入/輸出部分332c提供與記憶體晶粒34〇的一介面。記 憶體輸入/輸出部分332c接收經連接至電壓調節電路346之 輸出的一電源供應344。因此，提供給該記憶體輸入/輸出 部分332c之電源供應係在非取決於該主機提供之電壓vdd 的一固定電壓位準V〇。 記憶體晶粒340的一控制器輸入/輸出部分34〇a係透過形 成匯流排342之多重導體而連接至控制器晶粒332之輸入/ 輸出部分332c ’該匯流排在控制器晶粒332與記憶體晶粒 340間交換資料、命令及狀態資訊。控制器輸入/輸出部分 340a提供與控制器晶粒332的一介面。控制器輸入/輸出部 分340a接收經連接至電壓調節電路346之輸出的一電源供 應348。因此，提供給控制器輸入/輸出部分340a之電源供 應在非取決於該主機提供之電壓Vdd的一固定電壓位準 V〇。 一圮fe體核心部分340b包含一或多個記憶體陣列及某些 周邊電路。§己憶體核心部分340b接收經連接至電壓調節電 路346之輸出的一電源供應350。因此，提供給記憶體核心 部分340b之電源供應在非取決於該主機提供之電壓的 一固定電壓位準v0。此範例中，記憶體晶粒340係一單一 電壓（非一雙電壓）晶粒。 圖3B顯示圖3A之控制器晶粒332的一較詳細圖式。尤 其’圖3B顯示控制器晶粒332之三個部分332a至c及每一部 分中之某些組件。該主機輸入/輸出部分332a含有連接至 124724.doc -14- 200822133 導體之輸入/輸出驅動器352，該等導體連接至與該主機之 實體介面。輸入/輸出驅動器352接收在一電壓VDD的一電 源供應，該電壓VDD係接收自該主機之輸入電壓。該主機 與該控制器晶粒332之主機輸入/輸出部分332a間之邏輯信 號一般而言使用VDD當作一邏輯電壓位準。輸入/輸出驅動TransFlashTM memory module standard. It has also enabled small, hand-held, heavy-duty, sinusoidal, non-grasping suffixes to interface with a computer or other type of host through a universal serial bus (Usb) connector. A number of USB flash drives with the trademark "Cruzer(g)" of SanD1Sk are available on the market. 124724.doc 200822133 USB flash drives are usually larger and different in shape from the memory card described above. Two general-purpose memory cell array architectures have been commercially available, namely N〇R and NAND. In a typical n〇R array, the memory cell is connected between the adjacent bit line source and the drain diffusion, and the drain diffusion extends in the row direction. The control gate is connected to the cell column. Word line. A U-body unit includes at least one storage element 'on which is located over at least a portion of the cell channel region between the source and the gate. A stylized charge level on the storage element thus controls an operational characteristic of the units that can be read by applying an appropriate voltage to the addressed memory unit. Examples of such units, their use in memory systems, and methods for their manufacture are set forth in U.S. Patent Nos. 5, 〇 7, 〇 32; 5, 〇 95, 344; 5, 3 13, 421; 5, 315 '541, 5, 343, 063. 5,661,053 and 6,222,762. A NAND array utilizes a series string of more than two memory cells (e.g., "or") that are coupled between an individual bit line and a reference potential to form a cell row. The word line will extend across a large number of singles 70 within these lines. A unit within a row is fetched and verified during the privateization period by hard-switching the remaining cells in the string so that the current through a substring depends on the level of charge stored in the addressed unit. An example of a NAND architecture array and its operation as part of a memory system is found in U.S. Patent Nos. 5,57,350,315; 5,774,397; M46,935; 6,456,528 and 6,522,580. As discussed in the patent cited by Xianyueil, the current charge storage element of the flash array is the most common material floating gate, which is often formed by conductive material 124724.doc 200822133. It can be used for flashing. One of the alternative types of the system is to replace the conductive floating interpole with a non-conductive dielectric material to cut the charge in the pure square. In - Fancai, from Oxide Xi, Nitride Xi and Oxide Xi ( The three-layer dielectric system formed by 〇N〇) is sandwiched between the conductive control gate and the semi-conductive substrate above the memory cell channel, by injecting electrons from the cell channel into the nitride. Stylizing the unit 'in the nitride, the electrons are intercepted and stored in a restricted area and erased by injecting the thermal hole into the nitride. Several known dielectric storage elements are used. Specific cell structures and arrays are described in U.S. Patent No. 6,925,007. = Do not flash EEPR0M^ store a quantity of charge in a charge storage element or cell (which represents one or more bits of data) Charge level Controlling the threshold voltage of its memory cell (generally referred to as v-based as a basis for the storage state of the read cell. Usually a threshold voltage window is divided into several ranges, two or more storage states of the memory cell Each of the states corresponds to a range. These ranges are separated by a guard band that includes a nominal sense level that allows for determining the storage state of the individual cells. The storage locations are accurately adjacent due to interference. Or the offset of the charge of the stylized, read, or erase operations performed in other associated memory cells, pages, or blocks. Therefore, the error correction code (ECC) is typically calculated by the controller and is The programmed host data is stored together and used to verify the data during reading and to perform a certain level of lean correction if necessary. The memory cells of a typical flash EEPROM array are erased together 124724.doc 200822133 Discrete block early, that is, the block (erase block) is the minimum number of cells that can be erased at the same time. Each erase block generally stores one or more resources. Page, which is the smallest unit of stylization and reading, but can be programmed or read more than one page in parallel in different sub-arrays or planes. Pages • General storage of one or more data sections, sections The size is defined by the host system. An exemplary section follows a standard established for the drive, including 5 12-bit host data, plus information about the host and/or storage thereof f) In addition to a number of byte management information for the block, such memory typically configures 16, 32 or more pages in each erase block, and each page stores host data for one or more segments. The data may include user data from an application running on the host and data generated by the host in the management memory (eg, FAT (File Configuration Table)) and directory data. Generally, a memory array is formed on a die ("memory die, or, wafer"), and the die may have peripheral circuits connected to the memory array. Examples of peripheral circuits include columns. And a row control circuit, a register, a state machine, a charge pump, and other circuits associated with reading, writing, and erasing data in a memory array. A central processing unit (CPU), a buffer cache (buffer RAM), and a component of a CPU RAM. Buffers • Both the RAMC and the CPU RAM can be SRAM memory. These components can be in the same die. Or the detachment of the dies. The CPU is a microprocessor that operates the software (firmware) to effect the operation of transferring data to and from the memory array. U.S. Patent No. 5,297,148 (which is incorporated by reference in its entirety) In an example shown in this document, a buffer cache can be used as a write 124724.doc 200822133 to reduce wear and tear for use as a non-volatile memory Η == circuit (10), such that - single _ integrated circuit (controller Granules or cymbals) perform all memory controller functions. Some C memory cards can be used with different hosts that do not always use the same standard. For example, some hosts can provide 3.3 volts of power to the memory card, and - he can A power supply of 1.8 volts is provided. A card operating at two different voltage levels can be considered a dual voltage memory card. uf Ο Figure 1 shows a dual voltage memory card 1 of the prior art with a connection to: A dual voltage controller die 1 () 4 of a dual voltage controller die 1 〇 2. Both the control 曰曰 1 1G2 and the memory die 1 () 4 receive it from the host through a common contact 106 And at the power of the voltage supplied by the host. Regardless of the 4 host providing 3·3 volts or 18 volts, the internal circuit of both the controller die 1 and the memory die 104 allows each Operation is also performed. Figure 1 also shows a common ground contact 1〇8, which provides a ground voltage Vss, a port of the controller die and the memory die. Further, contacts 11 〇a to d are provided. For the exchange of data, commands and status information. According to an embodiment of the invention, the voltage regulation of a memory die is performed by a voltage regulating circuit separate from the memory die. When the host provides one of two or more different voltages When the power is applied to the card, the voltage regulating circuit supplies a required voltage power to the memory die. Therefore, a dual voltage memory die is no longer required. A memory operating only with a single power voltage can be used. The grain is generally 124724.doc -10- 200822133 is cheaper and smaller than the dual voltage memory die. Although the voltage regulation circuit provides power to the memory die, the memory controller The power from the host can be received directly and at a voltage dependent on the host. In one embodiment, the voltage regulating circuit provides an output voltage that is the same as or lower than the input voltage. In another embodiment, a voltage regulating circuit provides an output that is the same as or higher than the input voltage. Ο In some memory systems, the controller die receives different power supplies at different voltage levels for different circuits within a controller die. For example, the host interface circuit can provide a power supply at the -first voltage level. For the control core, the circuit can also provide another power supply at the first voltage level, and for the memory interface circuit, A second voltage level provides yet another supply. In one example, the first voltage level is received from a voltage level of the host and the second voltage level is provided by a voltage regulation circuit within the memory card. The voltage regulating circuit can be separate from both the controller die and the memory die or can be located in the controller crystal. Different portions of the memory die may also have different power supplies, but these portions generally have the same voltage level power as provided by the voltage regulating circuit. The additional aspects, advantages, features, and details of the various aspects of the invention are set forth in the description of the exemplary embodiments herein below. [Embodiment] FIG. 2 shows a dual voltage memory card 124724.doc 11 200822133 in accordance with an embodiment of the present invention. The dual voltage memory card 212 includes a physical interface 214 according to a standard for connecting to a wide variety of hosts. . The physical interface 214 includes individual contacts 2〇6 208, 21〇a through d that are coupled to corresponding contacts in a host socket. Contacts 206, 208, 21 are provided (1 to exchange data, and also to provide power to the memory card 212. In particular, a power supply contact 2〇6 is provided, which is connected to one of the host sockets The power supply contact. The voltage that supplies the host to the power supply contact 206 is designated as Vdd. Different hosts can "provide power at different voltage levels. Therefore, depending on which host the memory card 212 is connected to, VDD can have two. Or more than two different levels. In particular, the hidden card 2 12 is designed to operate with a host that provides power at two predetermined voltage levels. In other cases, the card can be designed to operate at three or more voltage levels. Or operating in a wide range of voltage levels. In addition to the power supply contact 206, a ground contact 2〇8 provides a ground connection from the host to the memory card η] and at a voltage designated as Vss The memory card 212 includes a controller die 216 and a memory die 218 that are connected together by forming a plurality of conductors of a data bus 2 2 。. In other memory cards, additional die may be present. For example, available Re-memory die. At the same time, a controller can include two gamma or more dies that perform different controller functions, instead of performing all controller functions in a single controller die. In addition to providing controller die 216 and memory Outside the die 218, a dust regulation circuit 222 is also provided, which is supplied with the adjusted dust to the memory die 218. The voltage regulating circuit 222 receives two or two from the power supply contact 206. An input power of one of the above different voltage levels is 124724.doc -12 - 200822133, and the voltage modulation circuit 222 provides a voltage output at a solid voltage that is not dependent on the input voltage. Therefore, the memory can be The card is connected to a host that provides power at different voltage levels, but the voltage level received by the memory die 218 is adjusted by the voltage regulation circuit 222 such that the memory particles 218 are not necessarily a dual voltage memory die. This provides cost savings, i.e., space savings, and also has more design flexibility than is typically possible with a dual voltage memory die. Figure 3A shows an embodiment of the present invention. A more detailed diagram. Figure 3A shows a dual voltage controller die 332 having three different portions 332a-c each having a separate power input. A host input/output portion 332a is coupled to a host The physical interface arrives at the signal from the host through the host input/output portion. The host input/output portion 332a receives a power supply 335 connected to a power input contact 336. Thus, The host input/output portion 33 receives power at a voltage vdd which is the voltage supplied by the host to the memory card 330, which may be at different levels depending on the host to which the memory card 33 is connected. A controller core portion 332b contains circuitry for managing the exchange of data between the memory card 33 and the host and managing the data in the memory card 330. Controller core portion 332b receives a power supply port 338 that is coupled to power input contact 336. Therefore, the core of the controller core portion 33 receives a voltage v such as the voltage which is the voltage supplied by the host to the memory card 330, depending on . It is recalled that the card 330 is connected to a host, which can be at different voltage levels. A memory input/output portion 332 of the controller die 332 is connected to the memory die 34 by a multiple conductor of a busbar 342 of shape 124724.doc • 13 · 200822133. Memory input/output section 332c provides an interface with the memory die 34. The memory input/output portion 332c receives a power supply 344 connected to the output of the voltage regulating circuit 346. Therefore, the power supplied to the memory input/output portion 332c The supply is at a fixed voltage level V〇 that is independent of the voltage vdd provided by the host. A controller input/output portion 34A of the memory die 340 is connected to the control through multiple conductors forming the bus bar 342. The input/output portion 332c' of the die 332 exchanges data, command and status information between the controller die 332 and the memory die 340. The controller input/output portion 340a is provided with the controller die 332. An interface. The controller input/output portion 340a receives a power supply 348 connected to the output of the voltage regulating circuit 346. Therefore, a power supply to the controller input/output portion 340a is provided. The supply is at a fixed voltage level V〇 that is independent of the voltage Vdd provided by the host. A body core portion 340b includes one or more memory arrays and certain peripheral circuits. § The memory core portion 340b receives the A power supply 350 is coupled to the output of voltage regulating circuit 346. Thus, the power supply to memory core portion 340b is supplied at a fixed voltage level v0 that is independent of the voltage provided by the host. In this example, memory crystal The granules 340 are a single voltage (non-double voltage) die. Figure 3B shows a more detailed view of the controller die 332 of Figure 3A. In particular, Figure 3B shows three portions 332a-c of the controller die 332. And some of the components in each section. The host input/output portion 332a includes an input/output driver 352 coupled to 124724.doc -14-200822133 conductors that are connected to a physical interface with the host. Input/output drivers 352 receives a power supply at a voltage VDD that is received from the input voltage of the host. Logic between the host and the host input/output portion 332a of the controller die 332 No general use as a logic voltage VDD level input / output drivers
器3 5 2係透過一資料匯流排3 5 4與控制器晶粒3 3 2上之其他 電路進行通信。資料匯流排354連接包含一微處理器356、 隨機存取記憶體（RAM) 358、唯讀記憶體（ROM) 360及錯 誤校正碼（ECC)電路362之控制器核心332b内的各種組件。 其他組件亦可存在於控制器核心332b中。 一内部電壓調節電路364位於記憶體核心332b中。内部 電壓調節電路364接收一在該主機提供之電壓Vdd的輸入電 壓。内部電壓調節電路364將此電壓轉換成一輸出電壓， 供控制器核心332b内之組件使用。以此方式，該控制器晶 粒332可以一個以上之輸入電壓位準操作。通常，此一控 制器晶粒係設計成以兩個不同輸入電壓位準運作，而且視 為-雙電壓控制器。例如’可將—控制器料成在Μ伏 特或3.3伏特操作。此等電壓係標稱電壓，而且允許與任 -電壓位準的-些偏^，所以定義例如Μ伏特至195伏特 及2.7伏特至3·6伏特之兩電壓範圍。將瞭解一般而言與一 標稱電壓的一些偏差係可允許。 、 卞 U此，可將一雙電壓記憶 卡視為指-接受在兩個不同電壓範圍之—以内的—電源供 應之卡。某些情況中，只要接受在—包含主⑽統所使用 之兩個特定電壓之單一連續電壓範圍内的一電源供應，則 124724.doc -15- 200822133 可將記憶卡視為一雙電壓記憶卡。 資料匯流排354亦連接至控制器332之記憶體輸入/輸出 部分332c中之記憶體輸入/輸出驅動器366。記憶體輸入/輸 出驅動器366透過導體將邏輯信號驅動至記憶體晶粒34〇。 記憶體輸入/輸出驅動器366接收在一電壓位準v〇的一電源 供應，該電壓位準V0亦即電壓調節電路346之輸出電壓。 該電壓V〇與接收自該主機之輸入電壓Vdd無關。記憶體輸 入/輸出驅動器366透過導體在其接收之電源供應所決定之 電壓位準驅動信號。只要已接收功率在一電壓位準v〇，則 在一電壓位準V〇傳送信號（而且一般而言另一電壓位準接 地）。因此，電壓位準Vo可表示一邏輯”丨”，而接地或零伏 特可表示一邏輯。或者ν〇可表示一邏輯，，〇”，而接地可 表示一邏輯” 1 ”。 圖4A顯示具有圖2、3A及3B之一替代配置的一記憶卡 468。於圖4A所示之配置中，在該記憶卡468中並未提供任 何分離電壓調節電路，因為電壓調節係於一控制器晶粒中 執行。如前面，一供應電壓VDD係由該主機所提供。電壓 vDD供應給包含該主機輸入/輸出電路470a及控制器核心 470b兩者的一控制器晶粒470。一電壓V〇 (V—flash)係於控 制器晶粒470中產生，而且提供給控制器晶粒470之内部電 路以及給記憶體晶粒472。因此，此組態中不要求任何分 離電壓調節器。 圖4 B顯不圖4 A之控制晶粒4 7 0的一較詳細圖式。控制 器晶粒470類似於圖3B之控制器晶粒，而且包含提供一已 124724.doc -16- 200822133 調卽電壓給控制器晶粒4 7 0之内部電路的一内部電壓調節 電路474。然而，對比於圖3B之控制器晶粒，此控制器晶 粒之電壓調節電路亦提供一已調節電壓Vq當作供應給該記 憶體晶粒472的一輸出（亦可將V()稱為v一 flash，即供應給該 快閃記憶體陣列之電壓）。因此，該電壓調節電路負責提 供例如輸入/輸出驅動器476之内部電路及控制器晶粒470 外部之電路兩者的一已調節電壓。除了該等控制器晶粒 ❹ 470及記憶體晶粒472之電路外，只要提供其他電路，該電 壓V 〇亦可提供給此類電路。 圖5顯示圖3A之單一電壓記憶體晶粒34〇的一較詳細圖 式，其顯示記憶體晶粒340之控制器輸入/輸出部分34〇a及 圮憶體核心部分340b的某些組件（單一電壓記憶體晶粒472 可具有一同樣或類似結構）。顯示該控制器輸入/輸出部分 340a具有連接至往控制器晶粒332之匯流排342之導體的控 制器輸入/輸出驅動器580。該等控制器輸入/輸出驅動器 C； 580接收在一電壓位準v〇的一電源供應348，該電壓位準 V〇係電壓調節電路346之輸出電壓。因此，控制器輸入/輸 出驅動器580在電壓位準¥〇驅動導體，並且類似於該控制 ， 器晶粒332中之記憶體輸入/輸出驅動器366而接地，而且 此等驅動器間所交換之信號使用相同電壓位準。 此範例中，控制器輸入/輸出驅動器58〇係藉由三個匯流 排5 82a至c連接至該記憶體晶粒34〇上其他電路。一位址匯 流排582a在輸入/輸出驅動器58〇與列控制電路及行控 制電路586間承載位址資訊。一資料匯流排582b在輸入/輸 124724.doc -17- 200822133 出驅動器580與連接至記憶體陣列590之資料輸入/輸出電 路588間承載資料。一控制/狀態匯流排582c在記憶體晶粒 340之輸入/輸出驅動器580與命令介面電路592間承載命令 及狀態資訊。 列控制電路584、行控制電路586、資料輸入/輸出電路 588及命令介面電路592全部具備來自電壓調節電路346之 輸出並在該電壓位準V〇的供應功率。除了該記憶體晶粒 340中所示之電路外，亦可提供而且可在一電壓位準v〇供 應額外電路。甚至當該主機所供應之電壓Vdd變動時，仍 在一電壓位準V〇供應記憶體晶粒34〇，使得記憶體晶粒34〇 永遠接收一單一電壓位準V〇。因此，記憶體晶粒34〇未必 為一雙電壓記憶體晶粒，而且可為一單一電壓記憶體晶 粒。例如，記憶體晶粒340可僅以18伏特（或從17伏特至 1.95伏特之一範圍）的一電源供應運作，或者記憶體晶粒 340可僅以3.3伏特（或從2.7伏特至3.6伏特之一範圍）的一電 源供應運作。 雖然記憶體晶粒340可為無法以不同電源供應電壓位準 操作的一單一電壓記憶體晶粒，但記憶體晶粒340内可存 在一個以上電壓位準。記憶體晶粒上普遍產生高電壓，以 允許在一記憶體陣列中寫入及抹除資料。可於該記憶體晶 粒上提供電荷幫浦或其他電路，以便從該電源供應電心。 發展此類電壓。 圖6顯示根據本發明之一具體實施例的—電壓調節電路 601 ’其提供在一永遠小於或等於該輸入電壓之位準的一 124724.doc -18 - 200822133 =所=輸出錢。藉由設計’該輸入電壓永遠大於或 :“輸出。根據此具體實施例，當一主機提供在一高 於^準的—電源供應時，電壓調節電路6G1提供在一低 :二入之電壓位準的一輸出。因此，該電壓調節電路具 =一電壓降低能力，而且可與要求—在—低電壓之電源供 應的單—電壓記憶體晶粒使用。當該主機提供在-低電魔The device 3 5 2 communicates with other circuits on the controller die 3 3 through a data bus 3 5 4 . The data bus 354 is coupled to various components within a controller core 332b that includes a microprocessor 356, random access memory (RAM) 358, read only memory (ROM) 360, and error correction code (ECC) circuitry 362. Other components may also be present in controller core 332b. An internal voltage regulation circuit 364 is located in the memory core 332b. Internal voltage regulation circuit 364 receives an input voltage at a voltage Vdd provided by the host. Internal voltage regulation circuit 364 converts this voltage into an output voltage for use by components within controller core 332b. In this manner, the controller crystal 332 can operate at more than one input voltage level. Typically, this controller die is designed to operate at two different input voltage levels and is considered a dual voltage controller. For example, the controller can be operated in either volts or 3.3 volts. These voltages are nominal voltages and allow some bias with any voltage level, so two voltage ranges, for example, Μ volts to 195 volts and 2.7 volts to 3.6 volts are defined. It will be appreciated that some deviations from a nominal voltage are generally acceptable.卞 U, a pair of voltage memory cards can be regarded as a card that accepts power supply within two different voltage ranges. In some cases, a memory card can be considered as a pair of voltage memory cards as long as it accepts a power supply within a single continuous voltage range containing two specific voltages used by the main (10) system. 124724.doc -15- 200822133 . The data bus 354 is also coupled to the memory input/output driver 366 in the memory input/output portion 332c of the controller 332. The memory input/output driver 366 drives the logic signal to the memory die 34 through the conductor. The memory input/output driver 366 receives a power supply at a voltage level V0, which is the output voltage of the voltage regulating circuit 346. This voltage V〇 is independent of the input voltage Vdd received from the host. The memory input/output driver 366 drives the signal through a voltage level determined by the conductor at the power supply it receives. As long as the received power is at a voltage level v〇, the signal is transmitted at a voltage level V (and generally another voltage level is grounded). Thus, voltage level Vo can represent a logic "丨", while ground or zero volts can represent a logic. Alternatively, ν 〇 may represent a logic, 〇 ”, and the ground may represent a logic “ 1 ”. Figure 4A shows a memory card 468 having an alternative configuration of Figures 2, 3A and 3B. In the configuration shown in Figure 4A No separate voltage regulation circuit is provided in the memory card 468 because the voltage regulation is performed in a controller die. As before, a supply voltage VDD is provided by the host. The voltage vDD is supplied to the host. A controller die 470 of both input/output circuit 470a and controller core 470b. A voltage V〇 (V-flash) is generated in controller die 470 and is provided to internal circuitry of controller die 470. And to the memory die 472. Therefore, no separate voltage regulator is required in this configuration. Figure 4B shows a more detailed diagram of the control die 470 of Figure 4. The controller die 470 is similar. The controller die of Figure 3B, and includes an internal voltage regulation circuit 474 that provides an internal circuit for the controller block die 4100. The comparison with Figure 3B is provided. Controller die, this controller die The voltage regulating circuit also provides an adjusted voltage Vq as an output to the memory die 472 (may also refer to V() as v-flash, ie, the voltage supplied to the flash memory array). The voltage regulating circuit is responsible for providing a regulated voltage for both the internal circuitry of the input/output driver 476 and the circuitry external to the controller die 470. In addition to the circuitry of the controller die 470 and the memory die 472 In addition, as long as other circuits are provided, the voltage V 〇 can also be provided to such a circuit. Figure 5 shows a more detailed diagram of the single voltage memory die 34A of Figure 3A, showing the controller of the memory die 340 Certain components of the input/output portion 34A and the core portion 340b (single voltage memory die 472 may have the same or similar structure). The controller input/output portion 340a is shown to have a connection to the controller The controller input/output driver 580 of the conductors of the bus bars 342 of the die 332. The controller input/output drivers C; 580 receive a power supply 348 at a voltage level v ,, the voltage level V 〇 The output voltage of the voltage regulating circuit 346. Therefore, the controller input/output driver 580 is at the voltage level 〇 drive conductor, and similar to the control, the memory input/output driver 366 in the die 332 is grounded, and this The signals exchanged between the drivers use the same voltage level. In this example, the controller input/output driver 58 is connected to the other circuits on the memory die 34 by three bus bars 5 82a to c. The address bus 582a carries address information between the input/output driver 58A and the column control circuit and the row control circuit 586. A data bus 582b carries data between the input/output 124724.doc -17-200822133 output driver 580 and the data input/output circuit 588 connected to the memory array 590. A control/status bus 582c carries command and status information between the input/output driver 580 and the command interface circuit 592 of the memory die 340. Column control circuit 584, row control circuit 586, data input/output circuit 588, and command interface circuit 592 all have supply power from the voltage regulation circuit 346 and at the voltage level V〇. In addition to the circuitry shown in the memory die 340, additional circuitry can be provided and can be provided at a voltage level. Even when the voltage Vdd supplied by the host changes, the memory die 34 is supplied at a voltage level V 〇 so that the memory die 34 永远 always receives a single voltage level V 〇 . Therefore, the memory die 34 is not necessarily a dual voltage memory die, but can be a single voltage memory die. For example, memory die 340 may operate with only one power supply of 18 volts (or range from 17 volts to 1.95 volts), or memory die 340 may only be 3.3 volts (or from 2.7 volts to 3.6 volts). A range of power supply operations. Although the memory die 340 can be a single voltage memory die that cannot operate at different power supply voltage levels, there can be more than one voltage level within the memory die 340. High voltages are commonly generated on the memory grains to allow writing and erasing of data in a memory array. A charge pump or other circuit can be provided on the memory grain to supply the core from the power source. Develop such voltages. Figure 6 shows a voltage regulating circuit 601' that provides a 124724.doc -18 - 200822133 = = output money for a level that is always less than or equal to the input voltage, in accordance with an embodiment of the present invention. By designing 'the input voltage is always greater than or: "output. According to this embodiment, when a host provides a higher than a power supply, the voltage regulating circuit 6G1 provides a low: two input voltage level An accurate output. Therefore, the voltage regulating circuit has a voltage-reducing capability, and can be used with a single-voltage memory die that requires a low-voltage power supply. When the host provides a low-powered magic
位準的-電源供應時’該電壓調節電路可提供與該輸入相 同之位準的一輸出。 範例中’-主機提供3.3伏特（如圖6中所示）或U伏特 的一電源供應，而且任—情況中，該電壓調節電路601提 供1.8伏特的一輸出。該電壓調節電路包含將— Μ伏特輸 電壓轉換成- 1·8伏特輸出電壓的一低壓降（LD〇)調節器 曰曰粒603除了邊LD0調節器晶粒603外，提供電容器 〇5a 60外以^作電壓調節電路6〇1的一部分。同時，於 某些具體實施μ中，彳提供感測㉟主機所供應之輸入電壓 在一高位準或一低位準的一感測電路。當該輸入電壓在一 高位準時，使用一LD0將該輸出降低至一低電壓位準。當 該輸入在一低位準時，可旁通該LD0，而且可直接提供該 輸入位準以當作該電壓調節電路之輸出。 電壓調節電路601含有可將一高位準（例如3 ·3伏特）轉換 成一較低電壓（例如1 ·8伏特）的一低壓降（ld〇)調節器。一 適合之電壓調節器的一範例係一 T〇rex xC6215。一般而言 一LDO調節器使用一或多個（此情況中為二）電容器。因 此’該電壓調節電路可包括至少一晶粒（積體電路），而且 124724.doc -19- 200822133 /N或多個離散裝置。此類型之電壓調節電路適合 ^ 在一面電壓及一低電壓（此範例中之3·3伏特及1.8伏 特）兩者操作之雙電壓記憶卡中設計成用於一低電壓（例 •8伏特）的一單一電壓記憶體晶粒使用。 圖7顯不根據一替代具體實施例的一電壓調節電路7 u， 提供來自一可在該輸出電壓以上或以下之輸入範圍的一 I疋、預定輸出電壓。根據此具體實施例，當一主機提供 在一低位準的一電源供應時，該電壓調節電路提供在一高 於該輸入之電壓位準的一輸出。因此，電壓調節電路7ιι 具有一電壓升壓能力。當一主機提供在一高電壓位準之功 率時，電壓調節電路711可提供在與該輸入相同之電壓位 準的一輸出。此類型之電壓調節電路可與一單一電壓記憶 體晶粒使用。無論來自一主機之電壓輸入在一高位準或一 低位準，該記憶體晶粒接收其在一高位準之電源供應。於 一範例中，一單一電壓記憶體晶粒以3·3伏特的一電源供 應電壓操作。此一記憶體晶粒可用於接收一來自一主機並 在3.3伏特或ι·8伏特之電源供應的一雙電壓記憶卡。任一 情況中，-電壓調節電路提供在3_3伏特的一輸出電壓給 該記憶體晶粒。尤其，當該主機提供18伏特的一電壓 時，該電壓調節電路將該電壓增加至3·3伏特的一輸出電 壓。某些情況中，電壓調節電路711亦可具有一電^降低 能力。電壓調節電路711可調節某一範圍内的一電壓，以 達成低於該範圍的一預定輸出電壓。例如，口 要一主機提 供3.3伏特與3.6伏特間的一電壓，電壓調節電路7ΐι可提供 124724.doc •20- 200822133 在3·3伏特的一輸出。 ^圖:之範例中’電壓調節電路7ιι包含一晶粒7ΐ3上的 扠供阿於该輸出電壓的一輸出電壓。 電壓調節電路711當作一 电曼 田忭已調即之倍壓器而操作，其接受 在一寬廣範圍（例如，1 7你4主 特至3·6伏特）中的-輸入電 ’而且提供在適合心—單—電壓,記憶體晶粒之 電壓範圍（例如，2.7伏特至3 又乍 ， ·6伙特）内的一輸出電壓。市 。曰曰粒可用於此一電壓調節電路。一範例係購自―的 :=xm59"，其可以例如Mu_咖4 7阳 電…電容器加以組態。因此，電壓調節電路7ΐι可包 含-或多個積體電路’而且亦包含一或多個離散裝置。可 將=-電路從當作—電荷幫浦之操作切換成當作—電麗隨 7之#作，使得t —主機提供—高電壓時，該電麼調節 電路以-高效率提供相同之高電壓位準當作一輸出。一般 而言可形成具有—適於低廓輪記憶卡之實體 Ο 輪的電荷幫浦(某些情況中，可要求具有-不大於。.5公羞 或〇·55公釐之厚度的組件）。 ”在使用一電荷幫浦的一替代方案中，亦可使用一高頻降 麼/升壓轉換器產生高於—輸入電壓的一輸出電壓給一電 壓調即電路。可形成具有一低輪廓電感器的一降壓/升壓 轉換器’使得該電壓調節電路之輪廓在—記憶卡之限制 内。圖8中顯示使用一電感器升壓一輸入電壓之-電壓調 節電路821的-範例。電壓調節電路821包含—轉換器晶粒 823、一電感器825及兩個電容器以〜至匕。例如電路82ι、 124724.doc •21- 200822133 711及601之電壓調節電路可當作如此處所示之分離電路而 實施’或者可當作一控制器晶片或ASIC的一部分而實施。 一般而言’例如一記憶卡的一記憶體系統内之晶粒全部 由一印刷電路板（PCB)所支援，而且可藉由該PCB上之跡 線加以互連。在一替代配置中，某些晶粒可以減少該等晶 粒佔用之面積的一配置加以堆疊，因而提供一經濟之配 置。尤其，可將一電壓調節晶粒堆疊在一控制器晶粒上或The level-power supply circuit provides an output that is the same level as the input. In the example, the host provides a power supply of 3.3 volts (as shown in Figure 6) or U volts, and in any case, the voltage regulating circuit 601 provides an output of 1.8 volts. The voltage regulating circuit includes a low dropout (LD〇) regulator that converts the Μ volt output voltage to an output voltage of -1.8 volts. The granule 603 provides a capacitor 〇5a 60 in addition to the LD0 regulator die 603. Take ^ as part of the voltage regulation circuit 6〇1. At the same time, in some implementations, the 彳 provides a sensing circuit that senses the input voltage supplied by the host 35 at a high level or a low level. When the input voltage is at a high level, the output is reduced to a low voltage level using an LD0. When the input is at a low level, the LD0 can be bypassed and the input level can be directly provided as the output of the voltage regulating circuit. Voltage regulating circuit 601 includes a low dropout (ld) regulator that converts a high level (e.g., 3 · 3 volts) to a lower voltage (e.g., 1 · 8 volts). An example of a suitable voltage regulator is a T〇rex xC6215. In general, an LDO regulator uses one or more (two in this case) capacitors. Therefore, the voltage regulating circuit can include at least one die (integrated circuit), and 124724.doc -19-200822133 /N or a plurality of discrete devices. This type of voltage regulation circuit is designed to be used for a low voltage (eg 8 volts) in a dual voltage memory card operating on both one voltage and a low voltage (3.3 volts and 1.8 volts in this example). A single voltage memory die is used. Figure 7 shows a voltage regulation circuit 7 u according to an alternative embodiment providing a predetermined output voltage from an input range above or below the output voltage. In accordance with this embodiment, the voltage regulating circuit provides an output at a voltage level above the input when a host provides a power supply at a low level. Therefore, the voltage regulating circuit 7 has a voltage boosting capability. When a host provides power at a high voltage level, voltage regulating circuit 711 can provide an output at the same voltage level as the input. This type of voltage regulation circuit can be used with a single voltage memory die. Whether the voltage input from a host is at a high level or a low level, the memory die receives its power supply at a high level. In one example, a single voltage memory die operates at a supply voltage of 3.3 volts. The memory die can be used to receive a dual voltage memory card from a host and supplied at 3.3 volts or ι·8 volts. In either case, the -voltage regulation circuit provides an output voltage of 3_3 volts to the memory die. In particular, when the host provides a voltage of 18 volts, the voltage regulating circuit increases the voltage to an output voltage of 3.3 volts. In some cases, the voltage regulating circuit 711 can also have a power reduction capability. The voltage regulating circuit 711 can adjust a voltage within a range to achieve a predetermined output voltage below the range. For example, if a host provides a voltage between 3.3 volts and 3.6 volts, the voltage regulation circuit 7 can provide 124724.doc • 20-200822133 at an output of 3.3 volts. In the example of the figure, the voltage regulating circuit 7 ι includes a cross on a die 7 ΐ 3 for an output voltage of the output voltage. The voltage regulating circuit 711 operates as a voltage-controlled voltage doubler of Mandala, which accepts -inputs in a wide range (for example, 1 7 4 4 to 3.6 volts) and provides An output voltage within a voltage range (eg, 2.7 volts to 3 volts, 6 terabytes) suitable for the heart-single-voltage, memory die. City. The granules can be used in this voltage regulating circuit. An example is purchased from: ==xm59", which can be configured, for example, as a Mu_Cai 47 solar capacitor. Thus, the voltage regulating circuit 7 can include - or a plurality of integrated circuits ' and also include one or more discrete devices. The =- circuit can be switched from the operation of the -charge pump to the operation of the battery, so that the t-host provides - the high voltage, the regulation circuit provides the same high efficiency - high efficiency The voltage level is treated as an output. In general, a charge pump having a physical wheel suitable for a low profile memory card can be formed (in some cases, a component having a thickness of -5 mm or 〇·55 mm can be required). . In an alternative to using a charge pump, a high frequency drop/boost converter can also be used to generate an output voltage higher than the input voltage to a voltage modulation circuit, which can be formed with a low profile inductance. A buck/boost converter of the device makes the outline of the voltage regulating circuit within the limits of the memory card. An example of a voltage regulating circuit 821 that uses an inductor to boost an input voltage is shown in FIG. The adjustment circuit 821 includes a converter die 823, an inductor 825, and two capacitors from ~ to 匕. For example, the voltage adjustment circuits of the circuits 82ι, 124724.doc • 21-200822133 711 and 601 can be regarded as shown here. Separating the circuit and implementing 'either can be implemented as part of a controller chip or ASIC. Generally, a die in a memory system such as a memory card is all supported by a printed circuit board (PCB), and Interconnected by traces on the PCB. In an alternative configuration, some of the dies can be stacked in a configuration that reduces the area occupied by the dies, thereby providing an economical configuration. Stacking a voltage regulating die on a controller die or
ϋ 一記憶體晶粒上。此類晶粒間可直接進行連接，無需連接 至該PCB。 一般而言，分離晶粒具有允許將晶粒個別地放置於一電 源切斷條件中之分離晶片啟用（CE)輸入。在將電壓調節至 少部分定位於一分離晶片（而非於該記憶體晶粒或控制器 晶粒）的一配置中，可將此調節器晶粒分離地放置於一電 源切斷條件中。此可藉由在無論何時不需要時關閉該調節 器晶粒而允許較多功率效率。 雙電壓記憶卡的一特定應用係適合用於例如蜂巢式電話 之行動裝置中之小型記憶卡。—範例係Mem〇ry 8滅ϋ A memory grain. Such dies can be connected directly without the need to connect to the PCB. In general, the split dies have separate wafer enable (CE) inputs that allow the dies to be individually placed in a power cut-off condition. In a configuration in which the voltage is adjusted to at least a portion of a separate wafer (rather than the memory die or controller die), the regulator die can be placed separately in a power cut-off condition. This allows for more power efficiency by turning off the regulator die whenever it is not needed. A particular application of a dual voltage memory card is suitable for use with small memory cards in mobile devices such as cellular telephones. —The example is Mem〇ry 8
Micro (M2)卡，其支援h8伏特及3.3伏特之操作電壓。其 他雙電壓記憶卡包含支援5.0伏特及33伏特之操作電壓的 CompactFlash卡。 雖然以上具體實施例係關於一種具有供應來自主機並在 兩個或兩個以上不同電壓之功率的一單一接點之記憶：， 但某些情況中’可使用一個以上接點。 具有分離接點組，其形成與不同主機介接之分離實體介 ’一記憶卡可 124724.doc -22- 200822133 面 具有兩個或兩個以上不因與辦八上 wΜ上不问貝體介面之卡可與不僅供 應不同電廢之功遂Η θ «Λ* /v . 羊而且具有含不同實體尺寸之插座的主機 使用。在此類記憶卡中，一一 ^ 弟；丨面如供一第一電源供 應接點，而且於一楚-人t , 1 咕、 、苐一 ；1面獒供一弟二電源供應接點。此 專電源供應接點可同時連接 〃了堤搔至電壓调即電路，然後該電 壓調節電路提供一在一楛 在匣疋電壓位準之輸出給該記憶卡中 的一或多個電路。 本文所引用的全部專利、專射請案、文章、書籍、說 明書、其他公告案、文件及内容皆出於所有目的而以引用 的方式全文併人本文中。在任何併人之公開案文件或事 物與本文件之正文間一術語之定義或使用之任何不一致或 衝突之範圍内，應優先採用該術語在本文件中之定義或使 雖然已就本發明之㈣性具體實施例及變化而說明本發 明之各方面，但是應瞭解，本發明有權在所附中請專利範 圍之全部範疇内受到保護。 【圖式簡單說明】 圖1顯示先前技術的一雙電壓記憶卡，並 /、丹百一雙電壓 控制器晶粒及一雙電壓記憶體晶粒。 圖2顯示根據本發明之一具體實施例的一雙電壓記情 卡，其具有一電壓調節電路，用以接受右 °思 、# a 接又在兩個不同電壓位 準的一輸入電壓，而且提供在一電壓位準的_輪出。 圖3A顯示根據本發明之一具體實施 . ^ ^ ^罨螘記憶 卡，其具有以該主機之電壓位準之功率所供應的_控制_ 124724.doc -23- 200822133 晶粒之部分，而且具有以透過一電壓調節電路的一不同電 壓位準所供應之一記憶體晶粒與該控制器晶粒的一部分。 圖3B顯示圖3A之控制器晶粒的—較詳細圖式，其1含 存在於該控制器晶粒中之某些電路。 圖4A顯示一替代雙電壓記憶卡’其中一控制器晶粒包含 提供一已調節電壓給一記憶體晶粒的一電壓調節電路。 圖4B顯示圖4A之控制器晶粒的一較詳細圖式，其包含 -内部電壓調節電路，帛以提供一已調節輸出給該控制： 晶粒之電路，而且當作來自該控制器晶粒的一輸出。 圖5顯示圖3 A之圮憶體晶粒的一較詳細圖式，其包含存 在於該記憶體晶粒中之某些電路。 圖6顯示一電壓調節電路，其提供在一永遠小於或等於 該輸入電壓之位準的-敎、預定輸出電壓。藉由設計，、 该輸入電壓永遠大於或等於所需輸出。 圖7顯示-電壓調節電路，其提供來自一可在該輸出電 壓以上或以下之輸入範圍的一穩定、預定輸出電壓。 圖8顯示一替代電壓調節電路，當該輸入電壓位準為低 時’其使用-電感器提供在一高於該輸入電壓位準之位 的一輸出電壓。 〆 【主要元件符號說明】 100 雙電壓記憶卡 102 雙電壓控制器晶粒 104 雙電壓記憶體晶粒 106 共同接點 124724.doc -24- 200822133 108 共同接地接點 110a 接點 110b 接點 110c 接點 llOd 接點 206 電源供應接點 208 接地接點 210a 接點 210b 接點 210c 接點 210d 接點 212 雙電壓記憶卡 214 實體介面 216 控制器晶粒 218 記憶體晶粒 220 資料匯流排 222 電壓調節電路 330 記憶卡 332 雙電壓控制器晶粒 332a 主機輸入/輸出部分 332b 控制器核心部分 332c 記憶體輸入/輸出部分 334 實體介面 335 電源供應 124724.doc -25- 200822133 336 功率輸入接點 338 電源供應 340 記憶體晶粒 340a 控制器輸入/輸出部分 340b 記憶體核心部分 342 匯流排 344 電源供應 346 電壓調節電路 348 電源供應 350 電源供應 352 輸入/輸出驅動器 354 資料匯流排 356 微處理器 358 隨機存取記憶體（RAM) 360 唯讀記憶體（ROM) 362 錯誤校正碼（ECC)電路 364 内部電壓調節電路 366 記憶體輸入/輸出驅動器 470 控制器晶粒 470a 主機輸入/輸出電路 470b 控制器核心 468 記憶卡 472 記憶體晶粒 474 内部電壓調節電路 124724.doc -26- 200822133Micro (M2) card, which supports operating voltages of h8 volts and 3.3 volts. Other dual-voltage memory cards include CompactFlash cards that support operating voltages of 5.0 volts and 33 volts. Although the above specific embodiments relate to a memory having a single contact that supplies power from a host and at two or more different voltages: in some cases, more than one contact can be used. It has a separate contact group, which forms a separate entity interface with different hosts. A memory card can be 124724.doc -22- 200822133. There are two or more non-caused interfaces. The card can be used with a host that not only supplies different electrical waste, θ «Λ* /v . sheep but also has sockets with different physical dimensions. In this kind of memory card, one by one brother; the face is for a first power supply contact point, and in one Chu-person t, 1 咕, 苐一; 1 獒 for a brother and two power supply contacts . The dedicated power supply contact can simultaneously connect the dike to the voltage modulation circuit, and then the voltage regulation circuit provides an output of one or more circuits to the memory card at a voltage level. All patents, special requests, articles, books, descriptions, other announcements, documents and contents cited herein are hereby incorporated by reference in their entirety for all purposes. In the event of any inconsistency or conflict between the definition or use of a term between any public document or thing and the body of this document, the definition of the term in this document shall be preferred or may be (4) Aspects of the invention are described in terms of specific embodiments and variations, but it is to be understood that the invention is intended to be protected within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a prior art dual voltage memory card, and /, Dan Baiyi dual voltage controller die and a pair of voltage memory die. 2 shows a dual voltage quotation card having a voltage regulating circuit for accepting an input voltage at two different voltage levels, in accordance with an embodiment of the present invention, and Provides a _ turn at a voltage level. 3A shows an embodiment of the present invention. The ^ ^ ^ ant memory card has a portion of the _ control _ 124724.doc -23- 200822133 dies supplied with the power level of the host, and has A memory die and a portion of the controller die are supplied through a different voltage level of a voltage regulating circuit. Figure 3B shows a more detailed view of the die of Figure 3A, with 1 including some of the circuitry present in the die of the controller. Figure 4A shows an alternative dual voltage memory card' in which a controller die includes a voltage regulating circuit that provides a regulated voltage to a memory die. 4B shows a more detailed diagram of the controller die of FIG. 4A, including an internal voltage regulation circuit to provide an adjusted output to the control: die circuit, and as a die from the controller An output. Figure 5 shows a more detailed view of the memory die of Figure 3A, including certain circuitry present in the memory die. Figure 6 shows a voltage regulating circuit that provides a predetermined output voltage at a level that is always less than or equal to the level of the input voltage. By design, the input voltage is always greater than or equal to the desired output. Figure 7 shows a voltage regulation circuit that provides a stable, predetermined output voltage from an input range above or below the output voltage. Figure 8 shows an alternative voltage regulation circuit that uses an inductor to provide an output voltage above the input voltage level when the input voltage level is low. 〆[Main component symbol description] 100 dual voltage memory card 102 dual voltage controller die 104 dual voltage memory die 106 common contact 124724.doc -24- 200822133 108 common ground contact 110a contact 110b contact 110c Point llOd contact 206 power supply contact 208 ground contact 210a contact 210b contact 210c contact 210d contact 212 dual voltage memory card 214 physical interface 216 controller die 218 memory die 220 data bus 222 voltage regulation Circuit 330 Memory Card 332 Dual Voltage Controller Die 332a Host Input/Output Portion 332b Controller Core Portion 332c Memory Input/Output Section 334 Physical Interface 335 Power Supply 124724.doc -25- 200822133 336 Power Input Contact 338 Power Supply 340 Memory die 340a Controller input/output section 340b Memory core section 342 Busbar 344 Power supply 346 Voltage regulation circuit 348 Power supply 350 Power supply 352 Input/output driver 354 Data bus 356 Microprocessor 358 Random access Memory (RAM) 360 read-only memory (ROM) 362 Error Correction Code (ECC) Circuitry 364 Internal Voltage Regulation Circuitry 366 Memory Input/Output Driver 470 Controller Die 470a Host Input/Output Circuit 470b Controller Core 468 Memory Card 472 Memory Die 474 Internal Voltage Regulation Circuitry 124724.doc -26- 200822133
ί； 476 580 582a 582b 582c 584 586 588 590 592 601 603 605a 605b 711 713 821 823 825 827a 827b 輸入/輸出驅動器 控制器輸入/輸出驅動器 位址匯流排 資料匯流排 控制/狀態匯流排 列控制電路 行控制電路 資料輸入/輸出電路 記憶體陣列 命令介面電路 電壓調節電路 低壓降（LDO)調節器晶粒 電容器 電容器 電壓調節電路 晶粒 電壓調節電路 轉換為晶粒 電感器 電容器 電容器 124724.doc -27-476; 582 580 582a 582b 582c 584 586 588 590 592 601 603 605a 605b 711 713 821 823 825 827a 827b Input/Output Driver Controller Input/Output Driver Address Busbar Data Bus Control/State Bus Alignment Control Circuit Row Control Circuit Data input/output circuit memory array command interface circuit voltage regulation circuit low dropout (LDO) regulator die capacitor voltage regulator circuit voltage regulation circuit converted to die inductor capacitor capacitor 124724.doc -27-