200820937 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種生理訊號擷取分析系統，尤指一種可 擷取及分析生理訊號兼具放大三跡訊號功能，以判別細胞 動作電位之訊號擷取分析系統。 【先前技術】 在醫學研究上，醫生常依病患的生理訊號，如心電圖、腦波 馨 圖、肌電圖，來判斷及分析病人的疾病狀態，進而給予藥物的治 療或做適當的處理，然而，這些生理訊號均屬幾十微伏特非常微 弱的訊號，一般人或經驗不足的醫療人員，很難從這些看似雜亂 的訊息中判讀出有意義的生理資訊。 一般係利用窗限鑑別器處理這些微弱的訊息，其處理的方式 及步驟如下，首先要確定系統的接地系統要良好，雜訊的干擾要 :降到最低，約為最小有意義訊號之三分之一以下，將訊號接到前 _ 置放大器做阻抗匹配，再經放大器放大後，再接至濾波器，選擇 適切之頻率響應範圍。 由於上述之_限鑑別裔價格相當昂貴，且該生理訊號經上 述處理僅7C將訊號放大，尚無法雌藏在生理訊號中有意義的訊 號加以擷取及分析。因此’在醫學研紅，對生理贿做積分處 理或利用電腦分析軟體對生理訊號做頻譜分析為―般常見 方式。 然而’刚述將訊號放大、積分處理及頻譜分析的過程相當費 5 200820937 時與不便，甚至會影響到醫生對病患病情的判斷。 故’如何提供—種價格較低雜立即將上_生理訊號加以 操取亚分析轉換為有意義資訊為本發明之創作重點。 【發明内容】 : 树明之主要目的，在於解決上述的問題而提供一種 .生理訊號擷取分析系統，其係將窗限鐘別裝置中之上限位 準及下限位準與訊號分別經由時序電路所控制的數位開關 • I理後衫混合及放大，以便得三跡錢輸出，藉此，使 本發明具有擷取並立即分析轉換生理訊號的功用。 本發明之另一目的，在於組成該生理訊號擷取分析系 統之構件均為規格品且取得容易，故，本發明具有降低製 造成本的功用。 為達成前述之目的，本發明係包括· • — S限鑑別裝置，該窗限鑑別裝置包含-窗限比較單元 • 、— TTL邏輯脈波處理單元、—單擊複振器、-計數電 路及一數字顯示器； 一二跡放大裝置，係與該窗限鑑別裝置呈電性連結， 立該三跡放大裝置包含一數位控制單元、一電路放大單元 、-時序電路單it、-遮沒訊號單元及—脈波產生器； 一顯不裝置，用以連結上述之窗限鑑別裝置、顯示器 與三跡放大裝置； 一電源供應單元，係供應該窗限鑑別裝置、三跡放大 6 200820937 裝置及一顯示裝置所需之電力。 本發明之上述及其他目的與優點，不難從下述所選用 實施例之詳細說明與附圖中，獲得深入了解。 當然，本發明在某些另件上，或另件之安排上容許有 所不同，但所選用之實施例，則於本說明書中，予以詳細 說明，並於附圖中展示其構造。 【實施方式】 請參閱第1圖，圖中所示者為本發明所選用之實施例 結構，此僅供說明之用，在專利申請上並不受此種結構之 限制。 本實施例之生理訊號擷取分析系統，其係包括： 一窗限比較單元1，該窗限比較單元1包含一上限位 準比較器1 1、一下限位準比較器1 2及一訊號輸入端1 3，該上限位準比較器1 1可接收一上限位準訊號1 1 1 ，而該下限位準比較器1 2則可接收一下限位準訊號1 2 1 〇 一TTL邏輯脈波處理單元2，係分析處理來自前述 之上、下限位準比較器1 1、1 2的脈波，並將之轉換成 一負向脈衝訊號（圖中未示）。 一單擊複振器3，連接於該TTL邏輯脈波處理單元 2，係由該負向脈衝訊號（圖中未示）所觸發。 一數位控制單元4，該數位控制單元4與該窗限比較 7 200820937 早兀1為電性連接’且該數位控制單元4，財實施例中 ’其係包含三緩衝級4 1與三數位_4 2，以讀取由該 自限比較單70 1令上、下限位準訊號1 1 1、i 2 i之資 訊0 $路放大單元5，連接於該數位控制單元4，係接 收X數位控制單之位準訊號，加以放大，並將訊號輸200820937 IX. INSTRUCTIONS: [Technical Field] The present invention relates to a physiological signal extraction analysis system, and more particularly to a signal that can extract and analyze a physiological signal and amplify a three-track signal to discriminate a cell action potential Capture the analysis system. [Prior Art] In medical research, doctors often judge and analyze the patient's disease state according to the patient's physiological signals, such as electrocardiogram, brain wave map, and electromyogram, and then give the drug treatment or appropriate treatment. However, these physiological signals are very weak signals of several tens of microvolts. It is difficult for ordinary people or inexperienced medical personnel to read meaningful physiological information from these seemingly messy messages. Generally, the window limit discriminator is used to process these weak messages. The processing method and steps are as follows. First, it is necessary to determine that the grounding system of the system is good, and the interference of the noise should be minimized, which is about three-thirds of the minimum meaningful signal. One or less, the signal is connected to the front _ amplifier for impedance matching, and then amplified by the amplifier, and then connected to the filter to select the appropriate frequency response range. Since the above-mentioned limited identification price is quite expensive, and the physiological signal is amplified by the above only 7C, it is not possible to capture and analyze the meaningful signals in the physiological signal. Therefore, it is a common way to do research in medical research, to perform integral processing on physiological bribery, or to use the computer analysis software to perform spectrum analysis on physiological signals. However, the process of amplifying the signal, integrating the processing and spectrum analysis is quite expensive. 5 200820937 is inconvenient and may even affect the doctor's judgment on the patient's condition. Therefore, 'how to provide a kind of low price and immediately convert the _ physiological signal to the sub-analysis into meaningful information for the creative focus of the invention. SUMMARY OF THE INVENTION The main purpose of Shuming is to solve the above problems and provide a physiological signal acquisition analysis system, which is to set the upper limit level and the lower limit level and the signal in the window limit device through the sequential circuit. The digital switch of the control is integrated and enlarged to obtain a three-note output, thereby enabling the present invention to extract and immediately analyze the function of converting the physiological signal. Another object of the present invention is that the components constituting the physiological signal acquisition analysis system are all specifications and are easy to obtain, and therefore, the present invention has a function of reducing the cost of the system. In order to achieve the foregoing objects, the present invention includes an S-limit discriminating device including a window threshold comparing unit, a TTL logic pulse processing unit, a click oscillating device, a counting circuit, and a digital display; a two-track amplifying device electrically connected to the window limiting device, wherein the three-track amplifying device comprises a digital control unit, a circuit amplifying unit, a sequential circuit single it, and a blanking signal unit And a pulse wave generator; a display device for connecting the window threshold discriminating device, the display and the three-track amplifying device; a power supply unit for supplying the window limit discriminating device, the three-track magnifying device 6 200820937 device and a device Display the power required by the device. The above and other objects and advantages of the present invention will be readily understood from Of course, the invention may be varied on certain components, or in the arrangement of the components, but the selected embodiments are described in detail in the specification and their construction is shown in the drawings. [Embodiment] Please refer to Fig. 1, which shows the structure of the embodiment selected for the present invention, which is for illustrative purposes only and is not limited by this structure in the patent application. The physiological signal acquisition and analysis system of the embodiment includes: a window limit comparison unit 1 including an upper limit level comparator 1 1 , a lower limit level comparator 12 and a signal input The terminal 1 3, the upper limit level comparator 1 1 can receive an upper limit level signal 1 1 1 , and the lower limit level comparator 1 2 can receive a lower limit level signal 1 2 1 TTL TTL logic pulse wave processing The unit 2 analyzes and processes the pulse wave from the upper and lower limit level comparators 1 1 and 12 and converts it into a negative pulse signal (not shown). A click oscillating device 3 is connected to the TTL logic pulse processing unit 2 and is triggered by the negative pulse signal (not shown). a digital control unit 4, the digital control unit 4 is compared with the window limit 7 200820937, the first is an electrical connection 'and the digital control unit 4, in the embodiment, the system includes three buffer stages 4 1 and three digits _ 4 2, in order to read the information from the self-limiting comparison list 70 1 upper and lower limit level signals 1 1 1 , i 2 i 0 0 way amplification unit 5, connected to the digital control unit 4, is to receive X digital control Single position signal, zoom in, and lose the signal
出至口顯不裝置c ’於本實施射，該顯示裝置c係為一 丁波而°亥电路放大單元5包含一和合放大器5丄與一 位準調節放大器5 2。 :時序電路單元6，與該數位控制單元4及-脈波產 口。8相連接且該時序電路單元6包含一時鐘脈衝6 1The output device c is a single wave, and the display circuit c is a DB and the circuit amplifying unit 5 includes a summing amplifier 5A and a level adjusting amplifier 52. : The timing circuit unit 6, and the digital control unit 4 and the pulse wave port. 8 phases are connected and the timing circuit unit 6 includes a clock pulse 6 1
(如型號N E 5 5 5之I c )、一正反器6 2 (如型號S N(such as model I E 5 5 5 I c ), a flip-flop 6 2 (such as model S N
7 4 7 3之1 C)及-反及閘6 3 (如型號7 4 0 〇之I -遮沒訊號單元7，連接於脈波產生n8，係接收該 脈波產生器8之婦u，並將之放大，轉換成負值訊號，再 送至該示波器之柵極端。 一脈波產生器8，係產生脈波訊號來控制上述之時序 電路6及該遮沒訊號單元7。 ' 一計數單元9 本實施例中，該 係一"亥單擊複振器3呈電性連接，於 冲數單％ 9係以正緣觸發（Positive 8 200820937 trigger)方式設置，且該計數單元9包含一計數電路9工 及一數字顯不器9 2相連接，俾供計數及訊號輸出，於本 實施例中，該計數電路9 1係由cm〇S系列型鱿4 5 1 1之I C與型说4 5 18之I C所組成，而該數字顯示器 9 2係為一二位數七段顯示器 一電源供應單元（圖中未示），於本實施例中，該電源 供應單兀之需求為士5V及士 12V，且其係同時連接上述之該 • 窗限比較單元1、該TTL邏輯脈波處理單元2、該單擊 複振器3、該數位控制單元4、該電路放大單元5、該時 序電路單元6、該遮沒訊號單元7、脈波產±器8及= 單元9，俾以提供上述各單元工作所需電力，並將上述之 固限比較單元1、丁 T L邏輯脈波處理單元2、單擊複振 器3及該計數單元9之組合界定為一窗限鑑別裝置八，而 i該數位控制單元4、電路放大單元5、時序電路單元6、 • 遮沒訊號單元7及該脈波產生器8則界定為一三跡放大裝 置B。 ^ 使用日守，該自限比較單兀1之上、下限位準訊號丄工 1、1 2 1可以為0〜5伏特間之任何值，其設定係由一只 擁有雙運算放大氣之IGLM747連接成增料1的電壓隨麵 益來達成，如附件1所示。 其次，利用TTL邏輯脈波處理單元2分析處理來自 9 200820937 窗限比較單元1的脈波訊號，由於該T T L邏輯脈波處理 單元2具有選擇開關整態（Integral mode)或差態 (Differential mode)的功能，當為整態時，係將超越下限 位準的訊號予以取出，反之，當為差態時，則僅將位於上 限位準比較器1 1及下限位準比較器1 2間的訊息予以擷 取並分析，如附件2。 當開始之輸出電壓為低電壓，由於該單擊複振器3之 電路是由一型號為NE555的I C組成，因此，該單擊複振 器3會持續維持低電壓，直到它受負脈衝觸發，輸出電壓 才會由低電壓換為高電壓，否則該單擊複振器3都會穩定 地處於低電壓的狀態。且輸出狀態為高電壓時並不穩定， 因為在觸發訊號的脈波結束後，輸出狀態仍會回復為低電 壓。加上該型號為NE555的I C對於每個輸入的觸發訊號 ，只產生一個輸出脈波，並配合該計數單元9，因此，可 以精確的控制輸出脈波存在的時間，如附件3與附件4所 示。 於時序電路單元6中，由該型號NE5 5 5之I C所 產生之脈衝，各輸入端狀態會隨時鐘脈衝6 1而改變，如 附件5所示。 再由窗限比較單元1取得上限位準訊號1 1 1、下限 位準訊號1 2 1及輸入訊號，分別經由緩衝級4 1、數位 200820937 開關4 2 ’將仅準訊號經由增益為1的和合放大器5 1組 口’後再級由1Q倍增㈣位準調節放大器5 2放大，其輸 出=號連接至不波器（Oscill〇scope)的垂直輸入端，該示 、 光幕卩可出現二掃描光跡線，如附件6所示；且該 數位開關4 2為-型號為CD4〇 6 6之I c，該數位開 關4 2的行為狀態則由時料路單元6之時序電路進行邏 輯控制田避輯為低位準0V時，該數位開關4 2處於導7 4 7 3 of 1 C) and - reverse gate 6 3 (such as model 7 4 0 I I - blanking signal unit 7, connected to the pulse wave to generate n8, is the woman receiving the pulse generator 8, The signal is amplified and converted into a negative signal, and then sent to the gate end of the oscilloscope. A pulse generator 8 generates a pulse signal to control the above-mentioned sequential circuit 6 and the blanking signal unit 7. 'One counting unit In this embodiment, the system "Hui click oscillating device 3 is electrically connected, and is arranged in a positive edge trigger (Positive 8 200820937 trigger) manner, and the counting unit 9 includes a The counting circuit 9 and a digital display unit 9 are connected to each other for counting and signal output. In the present embodiment, the counting circuit 9 1 is composed of an IC and a type of the cm〇S series type 5 4 5 1 1 4 5 18 IC, and the digital display 92 is a two-digit seven-segment display-power supply unit (not shown). In this embodiment, the power supply unit is required to be 5V. 12V, and it is connected to the above window threshold comparison unit 1, the TTL logic pulse processing unit 2, the click The vibrator 3, the digital control unit 4, the circuit amplifying unit 5, the sequential circuit unit 6, the blanking signal unit 7, the pulse wave generating device 8 and the = unit 9, are provided to provide the power required for the operation of each of the above units And the combination of the above-mentioned solid limit comparison unit 1, D-TL logic pulse processing unit 2, click oscillator 3 and the counting unit 9 is defined as a window limit discriminating device VIII, and i the digital control unit 4 The circuit amplifying unit 5, the timing circuit unit 6, the occlusion signal unit 7 and the pulse wave generator 8 are defined as a three-track amplifying device B. ^ Using the daily keeper, the self-limiting comparison unit 之上1 above and the lower limit Completion of the quasi-signal 1, 1, 2 1 can be any value between 0 and 5 volts, the setting is achieved by a voltage with the IGLM747 with dual operational amplification gas connected to the feed 1 with the benefits, as shown in Annex 1. Secondly, the pulse signal of the window limit comparison unit 1 from 9 200820937 is analyzed and processed by the TTL logic pulse processing unit 2, since the TTL logic pulse processing unit 2 has a selection switch integral state (Integral mode) or a differential state (Differential Mode) function, when it is in the whole state, The signal that exceeds the lower limit level is taken out. Otherwise, when it is in the differential state, only the message between the upper limit level comparator 1 1 and the lower limit level comparator 1 2 is extracted and analyzed, as shown in Annex 2. When the initial output voltage is low, since the circuit of the click oscillator 3 is composed of an IC of the type NE555, the click oscillator 3 continues to maintain a low voltage until it is triggered by a negative pulse. The output voltage will be changed from low voltage to high voltage, otherwise the click oscillating device 3 will be stably in a low voltage state. When the output state is high, it is unstable because the output state will return to low voltage after the pulse of the trigger signal ends. In addition, the IC of the model NE555 generates only one output pulse wave for each input trigger signal, and cooperates with the counting unit 9, so that the time of the output pulse wave can be accurately controlled, as shown in Annex 3 and Annex 4. Show. In the sequential circuit unit 6, the pulse generated by the I C of the model NE5 5 5, the state of each input will change with the clock pulse 61, as shown in Annex 5. Then, the window limit comparison unit 1 obtains the upper limit level signal 1 1 1 , the lower limit level signal 1 2 1 and the input signal, respectively, via the buffer stage 4 1 , the digit 200820937 switch 4 2 ', and only the quasi-signal is passed through the sum of 1 Amplifier 5 1 group port 'rear level is amplified by 1Q multiplication (four) level adjustment amplifier 52, and its output= sign is connected to the vertical input end of the Oscill〇scope, and the display and the light curtain can appear two scans. The light trace is as shown in the attachment 6; and the digital switch 42 is -I c of the type CD4〇6 6 , and the behavior state of the digital switch 42 is logically controlled by the sequential circuit of the time channel unit 6 When the avoidance is low level 0V, the digital switch 4 2 is in the guide
k(〇n)狀L反之為阻斷（〇ff)狀態，在導通狀態時，其間 阻抗約為7 5 Ω，準位調節放大器5 2的調節訊號範圍為士 5 V ° 當單波道掃描轉換成上述之三掃描光跡時，數位開關 4 2轉換瞬間的掃描光跡，必須用遮沒訊號單元7之遮沒 减來4除’於本實施例中，該遮沒訊號單元7之電路， 牛:所TF /亦即須將遮沒訊號送至示波器的樹極（以⑻ 方此在不波$之螢光幕顯現清晰的三光跡掃描。訊號之產 生仍將取自脈波產生器8，經由放大，並轉換成負值訊號 ，逕送至示波器的柵極，經由上述各組成構件可形成如附 件7之電路圖，其為整個系統的電路圖，如此，本發明可 顯示裝置C及電源 將窗限鑑別裝置A、三跡放大裝置β、 分別於麵包板上做測試，請參閱附件9 綜上所述’以本發明製作成果測量，如附件i 11 200820937 0所示輸入時，經本系統顯示在示波器上，則窗限鐘別裝 置之ifl號如附件1 1、附件1 2 ’而二跡放大裝置之訊號 請參閱附件1 3、附件1 4，所示當選擇開關為整態，將 所有超越下限位準的訊號予以取出顯示，如附件1 5所示 ’如選擇差態（Differential Mode)，則僅將位於上限位準 ， 與下限位準間的訊號取出，其結果如附件1 6所示。另三 跡放大裝置亦可以不同的波形輸入例如：三角波（附件工8 • )，正弦波（附件1 9 )，方波（附件2 0 )，均可適用於本發 明’亦具有相同之鑑別功能。 以上所述實施例之揭示係用以說明本發明，並非用以 限制本發明，故舉凡數值之變更或等效元件之置換仍應隸 屬本發明之範疇。 由以上詳細說明，可使熟知本項技藝者明瞭本發明的 . 確可達成前述目的，實已符合專利法之規定，爰提出專利 申請。 * 【圖式簡單綱】 第1圖係本發明之訊號處理方塊圖 【主要元件符號說明】 (習用部分） 益 (本發明部分） 窗限比較單元1 上限位準比較器1 1 上限位準訊號111 下限位準比較器12 12 200820937 下限位準訊號121 訊號輸入端13 TTL邏輯脈波處理單元2單擊複振器3 數位控制單元4 緩衝級41The k(〇n) shape L is the blocking (〇ff) state, and the impedance between them is about 7 5 Ω in the on state, and the adjustment signal range of the level adjustment amplifier 5 2 is ±5 V ° when the single channel scan When converting to the above three scanning traces, the scanning trace of the digital switch 42 is switched, and the mask of the blanking signal unit 7 must be subtracted by 4 in the present embodiment, the circuit of the blanking signal unit 7 , cow: TF / that is, the obscuration signal must be sent to the oscilloscope's tree pole (by (8), the clear three-light trace is displayed on the non-wave screen. The signal generation will still be taken from the pulse generator. 8, through amplification, and converted into a negative signal, the diameter is sent to the grid of the oscilloscope, through the above components can form a circuit diagram as the attachment 7, which is the circuit diagram of the entire system, thus, the present invention can display the device C and the power supply The window identification device A and the three-track amplification device β are respectively tested on the breadboard. Please refer to Appendix 9 for the above-mentioned measurement by the production result of the present invention, as shown in the attachment i 11 200820937 0, through the system Displayed on the oscilloscope, the window limit device The ifl number is as shown in Annex 1 1 and Annex 1 2 '. For the signal of the two-track amplification device, please refer to Annex 1 3, Annex 1 4, when the selection switch is in the whole state, all the signals beyond the lower limit level are taken out and displayed. As shown in Annex 1 5, if the differential mode is selected, only the signal between the upper limit level and the lower limit level is taken out. The result is shown in Annex 16. The other three track amplification devices can also be different. Waveform input such as: triangular wave (attachment 8 • ), sine wave (Attachment 19), square wave (Attachment 20), can be applied to the present invention 'also has the same authentication function. The disclosure of the above embodiment The present invention is not intended to limit the invention, and variations of the numerical values or substitutions of equivalent elements are still within the scope of the invention. From the above detailed description, those skilled in the art will be able to clarify the invention. It is indeed possible to achieve the above objectives, and it has already met the requirements of the Patent Law, and has filed a patent application. * [Simple diagram of the drawing] Figure 1 is a diagram of the signal processing block diagram of the present invention [Description of main component symbols] (customized part) (Part of the invention) Window limit comparison unit 1 Upper limit level comparator 1 1 Upper limit level signal 111 Lower limit level comparator 12 12 200820937 Lower limit level signal 121 Signal input terminal 13 TTL logic pulse wave processing unit 2 Click to reverberate 3 digital control unit 4 buffer stage 41
數位開關4 2 和合放大器5 1 時序電路單元6 正反器6 2 遮沒訊號單元7 計數單元9 數字顯示器9 2 電路放大單元5 位準調節放大器5 2 時鐘脈衝6 1 反及閘6 3 脈波產生器8 計數電路91 窗限鑑別裝置A 顯示裝罝C 三跡放大裝置B 13Digital switch 4 2 Combined amplifier 5 1 Sequential circuit unit 6 Positive and negative device 6 2 Occlusion signal unit 7 Counting unit 9 Digital display 9 2 Circuit amplification unit 5 Level adjustment amplifier 5 2 Clock pulse 6 1 Reverse gate 6 3 Pulse Generator 8 counting circuit 91 window limit discriminating device A display device C three-track amplifying device B 13