200820348 九、發明說明： 【發明所屬之技術領域】 _ 本發明係有關於一種製作金氧半導體(metal-oxide ^ semiconductor，以下簡稱為MOS)電晶體的方法，尤指一種 可有效改善瞬間增盈擴散(transient enhanced diffusion，以 下簡稱為TED)效應及短通道效應仏⑽⑽〗e|Yect)之製 作M0S電晶體之方法。 • 【先前技術】 隨著製程技術的進步以及對邏輯元件高速度與低耗電 的要求，MOS·電晶體的尺寸也隨之微縮至微米或奈米等級 以下之微細化尺寸，而伴隨著M0S電晶體微縮所產生短通 道效應，及其所造成的電晶體啟始電壓下降之問題，業界 一般以製作具有超淺接面（ultra shallow junction)的輕摻雜 汲極(lightly doped drain，LDD)來克服。 習知超淺接面形成技術是在完成MOS電晶體閘極製作 後’於閘極兩側矽基底的淺表面佈植入低能量離子，再施 以快速回火(rapid thermal annealing，以下簡稱為rta)以產 生最後的結合區輪廓(junction profile)。然而在縮小元件尺 寸的同時，源極、汲極與通道的摻雜原子濃度必須提高， 接面深度減小及摻雜原子濃度分佈形狀會有較顯著的變 化’因此習知超淺接面形成技術在90奈米技術已幾乎到達 6 200820348 了極限。當來到65與45奈米技術世代時，共植入 (co-implantation)搭配預非晶化離子植入 -(PM丽Phizati0n，以下簡稱為MI)製程雷射回火（L· 。歷aHng)等則被視為最有機會達到新世代超淺接面形成 技術需求之方法。其中共植入之概念為離子植入製程中因 換雜質撞擊石夕晶格而產生可觀的空隙缺陷（imerstitial defects)，這些空隙缺陷在快速回火時將成為硼瞬間擴散的 路& ’增加擴散的速度，即產生瞬間增益擴散(ted)效應。 • TED效應除加深接面外，也會使得側向換雜質分佈不陡 山肖，使得MOS電晶體反而遭遇嚴重的短通道效應。共植入 技術則被認為可改:善此一現象，例如施以碳離子共植入 時，由於碳會與空·隙缺陷形成鍵結，因此可降低因空隙缺 陷所造成的硼TED效應與硼簇（bor〇ncluster)的形成。 请參閱第1圖至第3圖，帛1圖至第3圖為一習知採用 籲共植入之方法形成超淺接面之輕摻雜汲極([〇〇)之p型 MOS電晶體。如第！圖所示，該方法係提供一基底剛， 基底100上則δ又置有一閘極介電層（gate dieiectric iayer) 1 〇2 與一閑極104。隨後對基底100進行一 PAI製程110,以銻 (Sb)或鍺(Ge)作為主要選擇，施以適當的能量與劑量使基底 1〇〇之矽晶格結構產生破壞，以形成一非晶化區域112。此 •非θ曰化的結構係用以降低侧的穿隨效應（channeling)與TED 效應。 7 200820348 請參閱第2圖。接下來對基底loo施行一共植入製程 ^ 120 ’將碳或氟以垂直基底1〇〇之角度植入基底100，隨後 ， 再施以P型摻雜質植入製程130，最後再進行一第一快逮 回火(RTA)製程140,完成P型電晶體之超淺接面之輕捧雜 汲極(LDD) 150之製作。請參閱第3圖，隨後於閘極1〇4 側邊形成偏位侧壁子（offset spacer) 160，並對基底1〇〇再施 以一 P型摻雜離子植入製程170以及一第二RTA製程 _ 180，以於偏位側壁子160兩侧之基底100内形成源極/汲 極 190 〇 然而，由於共植入製程120係以垂直基底1〇〇之角度植 入基底100,其在後續第一與第二RTA製程14〇、180中對 於P型摻雜質橫向擴散(lateral diffusion)之控制彳乃未臻理 想。因此，目前該技術領碱仍需要一種可有效抑制前述TED 效應以及橫向擴散的方法，以避免超淺接面輕摻雜汲極的 摻雜輪廓因擴散而產生改變。 【發明内容】 因此，本發明於此提供一種製作M0S電晶體的方法， 尤指一種可有效改善TED效應及短通道效益之製作M0S 電晶體之方法。 200820348 根據本發明之申請專利範圍，係提供一種製作“ 晶體之方法，該方法首先係提供一基底，且該基底上係T ， 含有一閘極結構。隨後進行一預非晶化(PAI)製程，以於談 - 閘極結構兩側之該基底内形成一非晶化區域；並進行—共 植入(co-implantation)製程，以於該非晶化區域内植入一共 植入摻雜質。接下來進行一第一離子植入製程與一第一快 速回火(RTA)製程，以於該非晶化區域内植入一第一推雜質 並活化該共植入摻雜質與該第一摻雜質，使該非晶化區域 _ 再結晶，而於該閘極結構兩側之該基底内分別形成一輕摻 雜汲極(LDD)。之後於該閘極結構之側壁形成一側壁子，以 及於該側壁子兩側之該基底内形成一源極/及極。 根據本發明之申請專利範圍，另提供一種製作1^〇8電 晶體的方法，該方法首先係提供一基底，該基底係包含有. 一閘極結構。之後進行一共植入製程，以於該閘極結構兩 _ 側之该基底内植入一共植入摻雜質，並形成一共植入摻雜 區。接下來進行一預非晶化製程，以於該閘極結構兩侧之 遠基底内形成一非晶化區域，以及進行一第一離子植入穿j 程，以於該非晶化區域内植入一第一摻雜質。隨後進行一 第一第一快速回火製程，以活化該共植入摻雜質與該第一 摻雜質，並使該非晶化區域再結晶，而形成一輕摻雜汲極， 以及於該基底内形成一源極/汲極。 200820348 根據本發明之申請專利範圍，更提供 晶體的方法，哕太氺昔土如 M〇S ^ -雜結構，該基底係包含有一 入# 2 區域；以及進行—第—離子植 進行晶化區域内植入一第'捧雜質。接下來 #雜質%Γ衣私以於該非晶化區域内再植入一共植入 摻雜質。㈣進行-第一快逮回火製程，以活化該共植入 摻雜質與該第-摻雜質，並使該非晶化 而 於5亥基底内形成一源極/汲極。 由於本發明所提供之製作聰電晶體之方法俜分別於 進行預非晶化製程之前、進 务係刀狀 灯乐雕于植入製程之前以及 進灯弟-離子獻製程之後進彳卜共植n因此於第 一快速回火製程之後，即可減少第—摻雜質橫向擴散與 TED效應。換句話說’本發_提供之方法係藉由共植入 製程有效控制第-摻雜質的擴散，以獲得良好的接合輪 廓，改善短通道效應。 【實施方式】 請參閱第4圖至第8圖，第4圖至第8圖係為本發明所 提供之製作MOS電晶體之方法之第一較佳實施例示意 圖。如第4圖所示，首先提供一基底2〇〇，基底可為 10 200820348 半導體晶圓、石夕覆絕緣晶圓（silicon-on-insulator，SOI wafer) 等，基底200已完成淺溝隔離(STI)製程以及井(well)的摻雜 ^ 製程，而且基底200上已形成有至少由一閘極介電層212 - 與一閘極214構成之閘極結構210。隨後進行一預非晶化 製程(PAI)製程220，PAI製程220可為一直角或斜角（angled) 之PAI製程，以於該閘極結構210兩側之基底200内形成 一非晶化區域222。 _ 請參閱第5圖。接下來進行一共植入(co-implantation) 製程230，以於該非晶化區域222内植入一共植入摻雜質 232。值得注意的是，該共植入摻雜質232係以一斜角離子 佈植製程植入基底200，亦即此共植入製程230係為一斜 角離子佈植製程，且該斜角0之範圍為0〜45度；而該共 植入摻雜質232係包含有碳、氟、或氮。而植入能量可依 植入位置而定，如3 KeV至20 KeV';劑量則可為lxl〇15 贏 至5χ1015個原子/cm3。 .請參閱第6圖。隨後進行一第一離子植入製程240，以 於非晶化區域222内植入一第一摻雜質242，且第一摻雜 質242與共植入摻雜質232植入於基底200之位置大致相 同。且當欲製作之MOS電晶體為P型電晶體時，第一摻雜 貧242包含有可以提供額外電洞的受體（acceptor)，例如硕 (B)、鎵(Ga)等三價元素；當欲製作之M0S電晶體為N型 200820348 電晶體時，第一摻雜質242則包含有可以提供額外電子的 施體(donor) ’例如填和珅等五價元素。隨後如第7圖所示， ’ 進行一第一快速回火(RTA)製程250，利用爐管（furnaCe)或 - 快速升溫處理（rapid thermal process，以下簡稱rtp )，於 1000〜1100°c之溫度下活化共植入摻雜質232與第一摻雜 質242，並使該非晶化區域222再結晶，而於非晶化區域 222内分別形成一輕摻雜汲極(1^〇)260。 • 請參閱第8圖，接下來於閘極結構210之侧壁形成一 侧壁子270,侧壁子270可為一氧化物氮化物-氧化物偏位 侧壁子（ΟΝΟ offset spacer)等。在完成側壁子270之製作 後，再於侧壁子270兩側之基底200中進行一第二離子植 入製程，以於側壁子270兩侧之基底200内形成一源極/没 極預定區域。隨後進行一第三RTA製程·.，以於源極/汲極預 卑區域内形成一源極/汲極280，該等步驟係為熟習該項技 φ 藝者以及通常知識考所熟知，故於此不再贅述。此外，亦 可依製程或產品需求，於完成源極/汲極280之製作後，移 除侧壁子270。至此完成本發明所提供之可有效改善ted 效應及橫向擴散之M0S電晶體製作方法。 請再參閱第5圖，值得注意的是，於本第一較佳實施例 中’更可於進行共植入製程230之後即進行一第二汉丁八製 程，利用爐管RTP提供一 1〇〇〇〜110(rc之高溫先行活化該 12 200820348 共植入摻雜質232，使得共植入摻雜質232先與空隙缺陷 形成鍵結。因此於後續製程中，更可降低因空隙缺陷造成 ^ 的TED效應。 另外，於本第一較佳實施例中，更可於進行共植入製程 230之如&加口袋型離子佈植（pocket implantation)製 程，以於非晶化區域220與基底2〇〇交界附近形成一口袋 型摻雜區。當然，此口袋型離子佈植製程亦可於共植入製 Φ程2如之後始進行，以抑制不正常的貫通（口丽仏化⑺％!!) 現象的發生。 • ·· 请參閲第9圖。第9圖係閘柘長度與啟始電壓下降 (roll-off)關係圖，其橫軸表示多晶矽閘極蝕刻後 ⑽er-etch-inspect，八叫臨界尺寸（cdticai dimensi〇n，CD)， 以微米（/i m)為單位，而縱軸表示啟始電壓以伏特（v〇lt) φ 為單位，其中菱形點係為習知M0S電晶體之量測值、圓形 點代表本第一較佳實施例之量測值、而方形點則代表標準 值。如第9圖所示，當習知多晶矽閘極長度越小時，越無 法控制短通道效應，M0S電晶體之啟始電壓亦隨之下降； 而當多晶矽閘極長度降到〇 〇3 # m時，習知M〇s電晶體之 啟始電壓已經下降到〇，也就是說，該M〇s電晶體根本無 .法使用。而根據本發明所提供之第一較佳實施例所得之 ’ M〇S電晶體，其啟始電壓可提高至015至〇·35，而符合期 13 200820348 待之‘準值’故可知本發明所提供之製作m〇s電晶體之方 法的確可有效改善TED效應以及短通道效應。 口月參閱第ίο圖至第12圖。第1〇圖至第12圖係為本發 =所提供之製作細電晶體之方法之第二較佳實施例示 意圖。如第1G圖所示，首先提供—基底·，基底3〇〇上 3至V由閘極介電層312與一閘極；314構成之閘極結 構310。&後進行一共植入製程32〇，以於此閘極結構训 =側之基底300内植入一共植入摻雜質322。值得注意的 是，該共植入摻雜質322係以一斜角離子佈植製程植入基 底300，亦即此共植入製程32〇係為一斜角離子佈植製程， 且邊斜角Θ之範圍為〇〜45度；而該共植入摻雜質係包含 有碳、氟.、或氮。而植入能量可依植入位置而定，如3 KeV 至20.KeV ·，劑量則可為1)<1〇15至5><1〇15個原子/(^3。 • *200820348 IX. Description of the invention: [Technical field to which the invention pertains] _ The present invention relates to a method for fabricating a metal-oxide semiconductor (hereinafter referred to as MOS) transistor, and more particularly to an effective improvement of instantaneous gain Transient enhanced diffusion (hereinafter referred to as TED) effect and short channel effect 仏(10)(10)〗 e|Yect) A method of fabricating a MOS transistor. • [Prior Art] With the advancement of process technology and the demand for high speed and low power consumption of logic components, the size of MOS·transistors has also been reduced to a micron size below the micron or nanometer level, accompanied by M0S. The short channel effect produced by transistor shrinkage and the resulting drop in transistor initiation voltage are commonly used in the industry to fabricate lightly doped drains (LDDs) with ultra shallow junctions. To overcome. The conventional ultra-shallow junction forming technique is to implant low-energy ions on the shallow surface of the substrate on both sides of the gate after the completion of the fabrication of the MOS transistor gate, and then apply rapid thermal annealing (hereinafter referred to as rta). To produce the final junction profile. However, while reducing the size of the components, the doping atom concentration of the source, the drain and the channel must be increased, the junction depth is reduced, and the shape of the dopant atomic concentration distribution is significantly changed. Therefore, the conventional ultra-shallow junction formation technique is The 90 nm technology has reached the limit of 6 200820348. When coming to the 65 and 45 nm technology generation, co-implantation with pre-amorphized ion implantation--(PM Li Phizati0n, hereinafter referred to as MI) process laser tempering (L·. calendar aHng ) is considered as the most promising way to meet the technical needs of the new generation of ultra-shallow junctions. Among them, the concept of co-implantation is to produce considerable gap defects (imerstitial defects) due to impurity-impacting collisions in the ion implantation process. These void defects will become the way of instantaneous diffusion of boron during rapid tempering. The speed of diffusion, that is, the instantaneous gain spread (ted) effect. • In addition to deepening the joint, the TED effect also makes the laterally-changed impurity distribution not steep, making the MOS transistor encounter a serious short-channel effect. Co-implantation technology is considered to be changeable: such a phenomenon, for example, when carbon ions are co-implanted, since carbon will bond with gaps, it can reduce the boron TED effect caused by void defects. Formation of boron clusters (bor〇ncluster). Please refer to FIG. 1 to FIG. 3 . FIG. 1 to FIG. 3 are a conventionally known method for forming a lightly doped gate ([〇〇] p-type MOS transistor with an ultra-shallow junction by means of a co-implantation method. . As the first! As shown in the figure, the method provides a substrate. On the substrate 100, a gate dielectric layer 1 〇 2 and a dummy electrode 104 are disposed. Subsequently, the substrate 100 is subjected to a PAI process 110, with strontium (Sb) or germanium (Ge) as the main selection, and appropriate energy and dose are applied to cause damage to the germanium lattice structure of the substrate to form an amorphization. Area 112. This • Non-θ 曰 structure is used to reduce the side channeling and TED effects. 7 200820348 Please refer to Figure 2. Next, a total implantation process is performed on the substrate loo ^ 120 'implanting carbon or fluorine into the substrate 100 at an angle of 1 Å perpendicular to the substrate, and then applying a P-type dopant implantation process 130, and finally performing a first A fast-recovery tempering (RTA) process 140 is completed to complete the production of the ultra-shallow junction of the P-type transistor. Referring to FIG. 3, an offset spacer 160 is formed on the side of the gate 1〇4, and a P-type dopant ion implantation process 170 and a second are applied to the substrate 1〇〇. The RTA process _ 180 forms a source/drain 190 in the substrate 100 on both sides of the offset sidewall 160. However, since the co-implant process 120 implants the substrate 100 at an angle of 1 Å perpendicular to the substrate, The subsequent control of the P-type dopant lateral diffusion in the first and second RTA processes 14A, 180 is not ideal. Therefore, at present, there is still a need for a method for effectively suppressing the aforementioned TED effect and lateral diffusion to avoid a change in the doping profile of the ultra-shallow junction lightly doped gate due to diffusion. SUMMARY OF THE INVENTION Accordingly, the present invention is directed to a method of fabricating a MOS transistor, and more particularly to a method of fabricating a MOS transistor that can effectively improve TED effects and short channel benefits. According to the patent application scope of the present invention, there is provided a method of fabricating a "crystal, which first provides a substrate, and the substrate T has a gate structure. Subsequently, a pre-amorphization (PAI) process is performed. In order to form an amorphized region in the substrate on both sides of the gate structure; and a co-implantation process is performed to implant a total implant dopant in the amorphized region. Next, a first ion implantation process and a first rapid tempering (RTA) process are performed to implant a first push impurity in the amorphization region and activate the co-implant dopant and the first doping Impurities, recrystallizing the amorphized region, and forming a lightly doped drain (LDD) in the substrate on both sides of the gate structure, and then forming a sidewall on the sidewall of the gate structure, and Forming a source/pole in the substrate on both sides of the sidewall. According to the scope of the invention, there is further provided a method for fabricating a transistor, the method first providing a substrate, the substrate Contains a gate structure. a pre-implantation process for implanting a total implant doping in the substrate on the two sides of the gate structure and forming a co-implanted doped region. Next, a pre-amorphization process is performed to the gate Forming an amorphization region in the far base on both sides of the pole structure, and performing a first ion implantation process to implant a first dopant in the amorphization region. a rapid tempering process to activate the co-implanted dopant and the first dopant, and recrystallize the amorphized region to form a lightly doped drain, and form a source in the substrate/ 200820348 According to the patent application of the present invention, there is further provided a method for crystals, such as a M〇S^-hetero structure, the substrate comprising an in #2 region; and performing a -ion ion implantation A crystallization impurity is implanted in the crystallization zone. Next, the impurity is implanted in the amorphized region to implant a total of doping. (4) Performing - the first fast tempering process to activate Co-implanting the dopant with the first dopant, and amorphizing the A source/drain is formed in the inner surface of the invention. After the ion-providing process, the symmetry of the first doping is reduced, and the TED effect can be reduced. In other words, the method provided by the present invention is effective by the co-implantation process. Controlling the diffusion of the first dopant to obtain a good junction profile and improving the short channel effect. [Embodiment] Please refer to Figures 4 to 8, and Figures 4 to 8 are the fabrications provided by the present invention. A schematic diagram of a first preferred embodiment of a method of MOS transistor. As shown in FIG. 4, a substrate 2 is first provided, and the substrate can be 10 200820348 semiconductor wafer, silicon-on-insulator , SOI wafer), etc., the substrate 200 has completed a shallow trench isolation (STI) process and a well doping process, and at least one gate dielectric layer 212 - and a gate 214 have been formed on the substrate 200 The gate structure 210 is constructed. A pre-amorphization process (PAI) process 220 is then performed. The PAI process 220 can be a pitch or angled PAI process to form an amorphized region in the substrate 200 on either side of the gate structure 210. 222. _ See Figure 5. Next, a co-implantation process 230 is performed to implant a total implant dopant 232 into the amorphized region 222. It is worth noting that the co-implanted dopant 232 is implanted into the substrate 200 by an oblique ion implantation process, that is, the co-implantation process 230 is an oblique ion implantation process, and the oblique angle is 0. The range is 0 to 45 degrees; and the co-implanted dopant 232 contains carbon, fluorine, or nitrogen. The implant energy can be determined depending on the implantation location, such as 3 KeV to 20 KeV'; the dose can be lxl〇15 to 5χ1015 atoms/cm3. Please refer to Figure 6. A first ion implantation process 240 is then performed to implant a first dopant 242 in the amorphization region 222, and the first dopant 242 and the co-implant dopant 232 are implanted in the substrate 200. The location is roughly the same. And when the MOS transistor to be fabricated is a P-type transistor, the first doping defect 242 includes an acceptor that can provide an additional hole, such as a trivalent element such as a master (B) or a gallium (Ga); When the MOS transistor to be fabricated is an N-type 200820348 transistor, the first dopant 242 contains a donor element such as a fill and a quinone which can provide additional electrons. Then, as shown in Fig. 7, 'a first rapid tempering (RTA) process 250 is performed, using a furnace tube (furnaCe) or a rapid thermal process (hereinafter referred to as rtp) at 1000 to 1100 °c. The doping 232 and the first doping 242 are co-implanted at a temperature, and the amorphized region 222 is recrystallized, and a lightly doped ruthenium (1 〇) 260 is formed in the amorphized region 222, respectively. . • Referring to Fig. 8, a sidewall 270 is formed on the sidewall of the gate structure 210. The sidewall spacer 270 can be an oxide nitride-oxide offset spacer or the like. After the fabrication of the sidewall spacers 270, a second ion implantation process is performed on the substrates 200 on both sides of the sidewall spacers 270 to form a source/defective predetermined region in the substrate 200 on both sides of the sidewall spacers 270. . A third RTA process is then performed to form a source/drain 280 in the source/bungee pre-week area, which is familiar to those skilled in the art and commonly known to the knowledge tester. This will not be repeated here. In addition, the sidewall 270 may be removed after the fabrication of the source/drain 280 is completed, depending on the process or product requirements. Thus, the MOS transistor manufacturing method provided by the present invention which can effectively improve the ted effect and lateral diffusion is completed. Please refer to FIG. 5 again. It should be noted that in the first preferred embodiment, a second Hanting eight process can be performed after the co-implantation process 230 is performed, and one tube is provided by the furnace tube RTP. 〇〇~110 (the high temperature of rc first activates the 12 200820348 to implant the doping 232, so that the co-implanted dopant 232 first forms a bond with the void defect. Therefore, in the subsequent process, the void defect is further reduced. In addition, in the first preferred embodiment, a co-implantation process 230 can be performed, such as a & pocket-type ion implantation process, to amorphize the region 220 with A pocket-type doping region is formed near the junction of the substrate 2 。. Of course, the pocket-type ion implantation process can also be performed after the co-implantation process 2 to prevent abnormal penetration (7) %!!) The phenomenon occurs. • ·· Please refer to Figure 9. Figure 9 is the relationship between the gate length and the starting voltage roll-off. The horizontal axis represents the polysilicon gate after etching (10) er-etch -inspect, eight called critical size (cdticai dimensi〇n, CD), in microns /im) is a unit, and the vertical axis indicates that the starting voltage is in units of volts (v〇lt) φ, wherein the diamond dots are measured values of a conventional MOS transistor, and the circular dots represent the first preferred embodiment. The measured value and the square point represent the standard value. As shown in Fig. 9, when the known polysilicon gate length is small, the less the short channel effect can be controlled, the starting voltage of the M0S transistor also decreases; When the polysilicon gate length is reduced to 〇〇3 # m, the starting voltage of the conventional M〇s transistor has dropped to 〇, that is, the M〇s transistor is not used at all. The 'M〇S transistor obtained in the first preferred embodiment provided can increase the starting voltage to 015 to 〇35, and meets the requirements of 13 200820348 to be 'quasi-valued', so that the production provided by the present invention can be known. The method of m〇s transistor can effectively improve the TED effect and the short channel effect. The month of the month refers to the first to the 12th. The first to the twelfth figure are the fine crystals produced by the present invention. A schematic diagram of a second preferred embodiment of the method. As shown in FIG. 1G, the substrate is first provided. The substrate 3 is connected to the gate structure 310 by a gate dielectric layer 312 and a gate electrode 314. 314 is followed by a total implantation process 32 〇 for the gate structure training side. A total implanted dopant 322 is implanted in the substrate 300. It is noted that the co-implanted dopant 322 is implanted into the substrate 300 by an oblique ion implantation process, that is, the co-implantation process is 32. The method is an oblique ion implantation process, and the bevel angle range is 〇~45 degrees; and the co-implanted doping system contains carbon, fluorine, or nitrogen, and the implantation energy can be implanted. Depending on the position, such as 3 KeV to 20.KeV, the dose can be 1) <1〇15 to 5><1〇15 atoms/(^3. • *
_ 叫參閱第11圖與第12圖。接下來對基底300進行一 PAI 呈330，PAI製程现亦可為一直角或斜角細抑旬之伙工 衣轾，，以於閘極結構310兩側之基底3〇〇内形成一非晶 化區域332。隨後如第12圖所示，進行一第一離子植入製 私340，以於非晶化區域332内植入一第一摻雜質料2，且 第摻雜質342與共植入摻雜質322植入於基底300之位 . 置大致相同。 200820348 隨後如前所述，進行一第一快速回火(RTA)製程，利用 爐管或RTP，於1000〜ll〇〇°C之溫度下活化共植入摻雜質 ， 322與第一摻雜質342，並使此非晶化區域332再結晶，而 、 於閘極結構310兩側之基底300内分別形成一輕摻雜彡及極 (LDD)。當欲製作之MOS電晶體為P型電晶體時，第一推 雜質342包含有可以提供額外電洞的受體，例如爛等物 質；當欲製作之MOS電晶體為N型電晶體時，第—推雜 質342則包含有可以提供額外電子的施體，例如磷和石申等 • 物質。接下來於閘極結構310之側壁形成一侧壁子，以及 於側壁子兩侧之基底300内進行第二離子摻雜製程與第三 RT A製程’以形成一源極/沒極。而該等側壁子係可依製程 或產品需求，於完成源極/汲極之製作後移除。該等製程係 .與第一較佳實施例相同，故於此不再贅述。 於本第二較佳實施例中，係可於進行共植入製程320 φ 後，立即進行一第二RTA製程，利用爐管或RTP提供一 1000〜ll〇〇C之高溫先行活化共植入摻雜質，使得共 植入摻雜質322先與空隙缺陷形成鍵結。因此於後續製程 中’更可降低因空隙缺陷造成的TED效應。 另外，於本第二較佳實施例中，亦可於進行共植入製程 320之前，增加一 口袋型離子佈植製程，以於非晶化區域 332與基底300交界附近形成一 口袋型摻雜區。當然，此 15 200820348 口发型離子佈植製程亦可於共植入製程320之後始進行， 以抑制不正常的貫通現象的發生。 • 清參閱第13圖至第16圖。第13圖至第16圖係為本發 明所提供之製作MOS電晶體之方法之第三較佳實施例示 意圖。如第圖所示，首先提供一基底400，基底400上 包含至少由—閘極介電層412與一閘極414構成之閘極結 構410酼後進行一預非晶化製程(PAI)製程420，PAI製程 φ ::可為―直角或斜角(雄句之伙1製程，以於該閘極 4物兩側之該基底働内形成一非晶化區域422。 .1 參閱第14圖與第15圖。接下來對_吉構楊兩側 =基底_進行一第—離子植人製程43G，以於非晶化區 域422内植入一第一摻雜f 432。當欲製作之丽電晶體 ^型電晶體時，第一掺雜f 432包含有爛等受體；當欲 籲製作之MOS電晶體為N型電晶體時，第—摻雜質似則 包含有磷和坤等施體。 隨後如第15圖所示，進行一共植入製程440,以於閘極 結構410兩側之基底400内植入—共植入播雜質442。值 得注意的是’共植人摻雜質442心—斜㈣子佈植製程 植入基底400 ’且該斜角β之範圍為〇〜45度；而該共植 入摻雜質係包含有碳、I、或氮。而植入能量可一植入位 16 200820348 置而疋，如3 KeV至20KeV;劑量則可為ιχ1〇ΐ5至5χ1〇15 個原子/cm3。 請參閱第16圖。進行一第一 RTA製程450，於1000〜 ll〇〇°C之溫度下活化第一摻雜質432與共植入摻雜質 442，並使非晶化區域422再結晶，而於閘極結構410兩側 之基底400内分別形成一輕摻雜汲極(LDD)460。 〆 接下來於閘極結構410之側壁形成一側壁子，以及於側 壁子兩側之基底400内進行第二離子摻雜製程與第二rta 製程，以形成一源極/汲極。而該等側壁子係可依製程或產 品需求，於完成源極/汲極之製作後移除。由於該等製程係 與第一較佳實施例相同，故於此不再贅述。同樣j；也，於本 第三較佳實施例中，亦可於進行共植入製程440之前，增 加一 口袋型離子佈植製程，以於非晶化區域422之間形成 一 口袋型摻雜區。當然，此口袋型離子佈植製程亦可於共 植入製程440之後始進行，以抑制不正常的貫通現象的發 生0 另外，本發明所提供之製作MOS電晶體之方法，係可 結合選擇性應變結構(selective strain scheme)技術，如用以 製作具有高張應力薄膜之NMOS電晶體或具有高壓應力薄 膜之PMOS電晶體，改善元件效能，更提昇M0S電晶體元件 17 200820348 的戰于邊移率與驅動電流。亦可結合嵌入式矽鍺源極/汲極 (recessed SiGe Source/darin)或嵌入式矽碳源極/汲極 • (recessed SiC Source/drain)結構，改善寄生電阻問題，增加 . 驅動電流與速度。 由於本發明所提供之製作MOS電晶體之方法係分別於 進行PAI製程之前、進行第一離子植入製程之前以及進行 第一離子植入製程之後進行一共植入製程，因此於RTA製 籲程之後’即可該等共摻雜質係可與空隙缺陷形成鍵結，而 避免第一摻雜質因空隙缺陷所造成的TED效應與橫向擴散 的發生。換句話說，本發明所提供之方法係藉由共植八製 程有效控制第一摻雜質的擴散，以獲得良好的接合輪廓， 改善短通道效應。 * . 以上所述僅為本發明之較佳實施例，凡依本發明申請專 φ利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第3圖係為習知採用離子共植入之方法形成超淺 二接面之:原極/’及極延伸區域之p型電晶體之示意圖。 第4圖至第8圖係為本發明所提供之製作電晶體之方 • 法之第一較佳實施例示意圖。 第9圖係閘極長度與啟始電壓下降㈣，圖。 18 200820348 之製作MOS電晶體之 第I ϋ圖至第12圖係為本發明所提供 方法之第二較佳實施例示意圖。 作MOS電晶體之 第13圖至第〗6圖係為本發明所提供之製 方法之第三較佳實施例示意圖。_ Refer to Figure 11 and Figure 12. Next, a PAI of 330 is performed on the substrate 300, and the PAI process can also be a uniform or a beveled corner, so as to form an amorphous layer in the substrate 3 on both sides of the gate structure 310. Area 332. Then, as shown in FIG. 12, a first ion implantation process 340 is performed to implant a first dopant material 2 in the amorphization region 332, and the first dopant 342 and the co-implant dopant The 322 is implanted in the position of the substrate 300. The settings are substantially the same. 200820348 Subsequently, as described above, a first rapid tempering (RTA) process is performed to activate the co-implanted dopant, 322 and the first doping at a temperature of 1000 〇〇 〇〇 ° C using a furnace tube or RTP. The 342 is recrystallized, and a lightly doped ytterbium and a drain (LDD) are formed in the substrate 300 on both sides of the gate structure 310. When the MOS transistor to be fabricated is a P-type transistor, the first push impurity 342 includes a receptor capable of providing an additional hole, such as a rotten substance; when the MOS transistor to be fabricated is an N-type transistor, the first - Push impurity 342 contains a donor that can provide additional electrons, such as phosphorus and stone. Next, a sidewall is formed on the sidewall of the gate structure 310, and a second ion doping process and a third RT A process are performed in the substrate 300 on both sides of the sidewall to form a source/depolarization. These sidewall sub-systems can be removed after the source/drain is completed, depending on the process or product requirements. These processes are the same as those of the first preferred embodiment, and thus will not be described again. In the second preferred embodiment, a second RTA process can be performed immediately after the co-implantation process 320 φ is performed, and a high-temperature first-time co-implantation of 1000~11〇〇C is provided by using a furnace tube or RTP. The dopant is such that the co-implanted dopant 322 first forms a bond with the void defect. Therefore, the TED effect caused by void defects can be reduced in subsequent processes. In addition, in the second preferred embodiment, a pocket-type ion implantation process may be added before the co-implantation process 320 to form a pocket-type doping near the boundary between the amorphized region 332 and the substrate 300. Area. Of course, this 15 200820348 oral ion implantation process can also be performed after the co-implantation process 320 to suppress the occurrence of abnormal penetration. • See Figures 13 through 16 for clarity. Figures 13 through 16 are schematic views of a third preferred embodiment of the method of fabricating a MOS transistor provided by the present invention. As shown in the figure, a substrate 400 is provided. The substrate 400 includes a gate structure 410 formed of at least a gate dielectric layer 412 and a gate 414, and then a pre-amorphization process (PAI) process 420 is performed. The PAI process φ :: can be a right angle or a bevel (the process of the male sentence 1), so that an amorphized region 422 is formed in the substrate 两侧 on both sides of the gate 4 . . . Figure 15. Next, a first-ion implanting process 43G is performed on the sides of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In the case of a crystal transistor, the first doping f 432 contains a ruined acceptor; when the MOS transistor to be fabricated is an N-type transistor, the first doping property includes a donor body such as phosphorus and kun. Subsequently, as shown in Fig. 15, a total implantation process 440 is performed to implant the implanted impurity 442 in the substrate 400 on both sides of the gate structure 410. It is worth noting that the 'co-implanted dopant 442 The heart-inclined (four) sub-planting process implants the substrate 400' and the bevel angle β ranges from 〇 to 45 degrees; and the co-implanted doping system contains carbon, I, or nitrogen. The energy can be placed at an implant level of 16 200820348, such as 3 KeV to 20 KeV; the dose can be ιχ1〇ΐ5 to 5χ1〇15 atoms/cm3. Please refer to Figure 16. Perform a first RTA process 450, The first dopant 432 is activated and co-implanted with the dopant 442 at a temperature of 1000 〇〇 ° C, and the amorphized region 422 is recrystallized, and formed in the substrate 400 on both sides of the gate structure 410, respectively. a lightly doped drain (LDD) 460. 〆 Next, a sidewall is formed on the sidewall of the gate structure 410, and a second ion doping process and a second rta process are performed in the substrate 400 on both sides of the sidewall. Forming a source/drain. The sidewalls can be removed after fabrication of the source/drain due to process or product requirements. Since the processes are the same as in the first preferred embodiment, Therefore, in the third preferred embodiment, a pocket-type ion implantation process can be added to form an amorphization region 422 before the co-implantation process 440 is performed. a pocket-type doped region. Of course, this pocket-type ion implantation process can also be used in the co-implantation process 440 Thereafter, the method of fabricating the MOS transistor provided by the present invention can be combined with a selective strain scheme technique, such as for fabricating a film having a high tensile stress. The NMOS transistor or the PMOS transistor with high-voltage stress film improves the device performance and enhances the edge shift rate and drive current of the MOS transistor component 17 200820348. It can also be combined with the embedded 矽锗 source/bungee (recessed) SiGe Source/darin) or embedded carbon source/drain (recessed SiC Source/drain) structure to improve parasitic resistance and increase drive current and speed. Since the method for fabricating the MOS transistor provided by the present invention is performed separately before the PAI process, before the first ion implantation process, and after the first ion implantation process, the RTA system is called after the RTA system. 'The co-doped systems can form bonds with void defects while avoiding the occurrence of TED effects and lateral diffusion due to void defects in the first dopant. In other words, the method provided by the present invention effectively controls the diffusion of the first dopant by co-planting eight processes to obtain a good joint profile and improve the short channel effect. The above is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the application of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 3 are schematic views showing a p-type transistor in which an ultra-shallow junction is formed by ion co-implantation: a primary pole/' and a pole extension region. 4 to 8 are schematic views showing a first preferred embodiment of the method for fabricating a transistor according to the present invention. Figure 9 shows the gate length and the starting voltage drop (4), figure. 18, 2008, the first embodiment of the present invention provides a schematic diagram of a second preferred embodiment of the method provided by the present invention. Fig. 13 through Fig. 6 of the MOS transistor are schematic views of a third preferred embodiment of the method of the present invention.
【主要元件符號說明】 100基底 104閘極 112非晶化區域 130 Ρ型摻雜質植入製程 150輕掺雜汲極(LDD) Π0離子植入數程 190源極/汲極 200基底 212閘極介電層 220預非晶化製裎 230共植入製程 240第一離子植入製程 250第一快速回火製程 270侧壁子 300基底 312閘極介電層 320共植入製程 閘極介電層 110預非晶化製程 120共植入製程 140第一快速回火製程 160 偏位側壁子 180第二回火製程 210 閘極結構 214閘極 222非晶化區域 232 共植入摻雜質 242第一摻雜質 260輕摻雜汲極(ldD) 280源極/沒極 310閘極結構 314 閑極 322 共植入摻雜質 19 200820348 J3U 預非晶化製程 332 340 第一離子植入製程 342 400 基底 410 412 閘極介電層 414 420 預非晶化製程 422 430 第一離子植入製程 432 440 共植入製程 442 450 第一快速回火製程 460 非晶化區域 第一摻雜質 閘極結構 閘極 非晶化區域 第一摻雜質 共植入摻雜質 輕摻雜汲極(LDD) 20[Main component symbol description] 100 substrate 104 gate 112 amorphization region 130 Ρ type dopant implantation process 150 lightly doped 汲 (LDD) Π 0 ion implantation range 190 source / bungee 200 substrate 212 gate Electrode layer 220 pre-amorphization system 230 co-implantation process 240 first ion implantation process 250 first fast tempering process 270 sidewall spacer 300 substrate 312 gate dielectric layer 320 co-implantation process gate dielectric Electrical layer 110 pre-amorphization process 120 co-implant process 140 first fast tempering process 160 offset sidewalls 180 second tempering process 210 gate structure 214 gate 222 amorphization region 232 co-implantation doping 242 first doped 260 lightly doped drain (ldD) 280 source / no pole 310 gate structure 314 idler 322 co-implanted doping 19 200820348 J3U pre-amorphization process 332 340 first ion implantation Process 342 400 Substrate 410 412 Gate Dielectric Layer 414 420 Pre-Amorphization Process 422 430 First Ion Implant Process 432 440 Co-implant Process 442 450 First Fast Tempering Process 460 Amorphized Region First Doping The first doping of the gate structure gate amorphization region is co-implanted with lightly doped light Heteroaryl drain (LDD) 20