200818253 UMCD-2006-0112 19814twf.doc/t 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體電路及其的形成方法且特別 是有關於一種半導體元件及其形成方法。 【先前技術】 在一般的半導體製程中，於金氧半電晶體製作完成之 後’會於基底上形成一層應力層，以增加電子或電洞在金 氧半電晶體的通道中的移動率(mobility)。在線寬為％奈 米以下的半導體製程中，對於p型金氧半電晶體來說，可 在基底上形成一層具有壓縮應力（compressive stress)的應 力層，以在P型金氧半電晶體中沿著通道方向形成壓縮應 力。而對於N型金氧半電晶體來說，可在基底上形成一層 具有拉伸應力(tensne stress)的應力層，以在N型金氧半電 晶體中沿著通道方向形成㈣應力。隨著壓縮應力或拉伸 應力的增加，f洞或電子在通道巾的移動率也隨之增加， 進而增加驅動電流(drive current)以提升元件效能。 料導體技㈣發展，對料導體元件效能 沿著通道方向形成的壓縮應力或拉伸應力= 洞在通道中的移動率，為目前十分重要且虽需解 圖6八至6B緣示習知一種增加電子或電洞在通道中的 私動率之半導體元件的剖面示意圖。 請參照圖6A ’ f知的做法是先在基底1()上形成金氧半 200818253 UMCD-2006-0112 19814twf.doc/t 電晶體20，並在金氧半電晶體2〇的閘極結構i3與源極/ 汲極區18上分別形成金屬矽化物層22與％。之後，[Technical Field] The present invention relates to an integrated circuit and a method of forming the same, and more particularly to a semiconductor device and a method of forming the same. [Prior Art] In a general semiconductor process, after the fabrication of a gold-oxygen semi-transistor, a stress layer is formed on the substrate to increase the mobility of electrons or holes in the channel of the MOS transistor. ). In a semiconductor process with a line width of less than % nanometers, for a p-type MOS transistor, a stress layer having a compressive stress can be formed on the substrate to be in the P-type MOS transistor. A compressive stress is formed along the channel direction. For N-type oxy-oxygen semiconductors, a stress layer having a tensile stress can be formed on the substrate to form (iv) stress along the channel direction in the N-type oxy-oxygen semiconductor. As the compressive stress or tensile stress increases, the mobility of the f-hole or electrons in the channel towel also increases, thereby increasing the drive current to improve component performance. Material conductor technology (4) development, the compressive stress or tensile stress formed by the material conductor element along the channel direction = the movement rate of the hole in the channel, which is very important at present, and it is necessary to solve the problem as shown in Fig. 6-8B. A schematic cross-sectional view of a semiconductor component that increases the rate of electron or hole in the channel. Referring to FIG. 6A, it is known that a gold oxide half 200818253 UMCD-2006-0112 19814 twf.doc/t transistor 20 is formed on the substrate 1 (), and a gate structure i3 is formed in the metal oxide half transistor 2 〇. Metal telluride layers 22 and % are formed on the source/drain regions 18, respectively. after that,
照圖6B ’在形成應力層之前，先進行—個侧製程，以= ，隙们4，使其寬度由S1 _成％，藉以使得後續形成的 應力層能更接近通道，_增加電子或電洞在通道中移動率 ，目的。然而’在進行餘刻製程時，金屬石夕化物層22與％ 是直接暴露於飯刻環境中，無任何的保護，因此，在進行賴 製程之後’尤其是過度姓刻後’金屬石夕化物層22與％將會遭 受蝕刻的破壞，以致片電阻無法達到所需。 曰曰 【發明内容】 本發明的目的就是在提供一種半導體元件及其製造方 法’其可以魏金射化物層在削減_壁時避免遭到 破壞。 ^ 本發明提出一種半導體元件的製造方法，此方法是先在基 底上形成一電晶體，其包括一閘極結構與一源極/汲極區，其 中閘極結構包括一閘極導體層、一閘介電層與一間隙壁，閘介 電層>M於閘極導體層與基底之間，間隙壁位於該閘極導體層之 側壁。接著，在電晶體的閘極導體層與源極/汲極區的表^上 形成一金屬矽化物層。之後，進行一表面處理步驟，以選擇性 地在金屬矽化物層上形成一保護層，此保護層之材質與閘極導 體層側壁上的空隙璧的材質不同。之後，以保護層為罩幕，移 除部分的間隙壁，以縮減間隙壁的寬度，使間隙壁與該金屬 化物層之間具有一空隙。其後，在基底上形成一應力層，覆蓋 間隙壁、保護層以及間隙壁與該金屬矽化物層之間的空隙。里 200818253 UMCD-2006-0112 19814twf.doc/t 依照本發明的實施例所述，上述閘極導體層與該源極/沒 極區的表面上形成該金屬矽化物的步驟包括在基底上形成一 層金屬層，接著，進行第一回火步驟，以使金屬層與閘極導體 層及源極/汲極區的表面反應，形成該金屬矽化物層，然後， 遥擇性移除未反應的金屬層，再進行第二回火步驟。 依照本發日㈣實施綱述，上述絲處理轉是在選擇 性移除未反應的該金屬層之步驟以及進行該第二回火步驟之 間進订的’或是在進行該第二回火步驟之後，移除部分間隙壁 之步驟之前進行的。 依知、本發明的實施例所述，上述表面處理步驟包括一氧 程錢氧化製程。氧化製程包括濕式氧化法或 卜。濕式氧化法可使用過氧化氮水溶液、臭氧水溶 二氧化法包減駄化或電裝 概法，可通人氧氣、臭氧、—氧化二氮或—氧 化鼠或其組合做為反應氣體。 化製述，上述表面處理步驟包括一氮 氣做為反纖體_彡纽化法，如通人錄和氫氣、或氨 鋅、㈣的實蘭所述’上述金4雜物包括鈦、钻、 述金屬之合錢其組合切化物。 層 化物層、x-保轉體元件’其包括一電晶體、一金屬石夕 -閘極结構ikt應力層。電晶體，位於基底上，其包括 、-閘介^ f極/祕區，其中閘極結構包括—閘極導體 %g共一間隙壁，閘介電層介於閘極導體層與基底 200818253 UMCD-2006-0112 19814twf.doc/t 之間，、間隙壁位於該閘極導體層之侧壁。金屬矽化物層，位於 源極/;及極區以及閘極導體層的表面上，源極/汲極區上之金屬 矽化物層與間隙壁之間具有一空隙。保護層，覆蓋金屬梦化物 層’但未覆蓋間隙壁。應力層，覆蓋間隙壁與保護層以及空隙。 依照本發明實酬所述，上述保制包括金屬氧化物、金 屬氮化物或金屬氮氧化物。 _ 依照本發明實施例所述，上述金屬矽化物包括鈦、鈷、鎳、 ’ m目、前述金屬之合金或其組合之秒化物。 依照本發明實施例所述，上述應力層包括—壓縮應力層或 一拉伸應力層。 本發明在進行削減間隙壁寬度的步驟之前，先進行一個表 面處理步驟’使金屬矽化物層的表面反應形成一層保護層，因 此’可避免金屬梦化物層在後續的削減間隙壁寬度的蚀刻製程 中遭受破壞。 < 為讓本發明之上述和其他目的、特徵和優點能更明顯易 % 懂’下文特舉較佳貫施例，並配合所附圖式，作詳細說明如下。 【實施方式】 圖1A至圖1D疋依照本發明實施例所繪示之一種半導體 、 元件的製造方法流程剖面圖。 請參照圖1A，在一基底1〇〇中形成一隔離結構1〇1，以 定義一主動區150。之後，在主動區15〇中形成一電晶體1〇2。 電晶體102包括一閘極結構1〇3與一源極/汲極區118。 基底100例如是整塊(bulk)為半導體的基底或是絕緣層上 有矽(SOI)的基底，如含有矽、磊晶矽、鍺、石夕:化錯、碳化石夕 200818253 UMCD-2006-0112 19814twf.doc/t 或其組合之基底。 電晶體102的形成方法例如是弁 的閘介電層辦與閘極導體層1〇 ^ 石夕層、氮氧化齋氮化聲或介電物疋乳化 如广層，層、二;介 携形成之。閘極 11?，十日r0C?次穋雜源極/及極區 或疋源極/汲極延伸區112。在本實施例中，以 極/>及極區112爽古穿明夕〇夕始—日日Λ /、才多木隹源 φ,ν.4Α 接者再於基底100中形成源極/¾㈣118 雜細汲祕116’或是源極/汲極接觸區ιΐ6。在本 只1中’以濃摻雜源極/汲極區116來說明之。間隙壁114 之材質例如是氧化々或是氮化梦。在形成間雜114之前，可 以在閘極導體層106的侧壁先形成一層襯層108，如圖认所 二或兩騎層1〇8與110，如圖2所示。請參照圖认，在 了了，例中，間隙壁114之材質為氮化矽，襯層108之材質可 所疋，化石夕。睛參照圖2，在另一實施例中，間隙壁114之材Figure 6B 'Before forming the stress layer, first perform a side process to =, the gap 4, so that its width is from S1 _%, so that the subsequently formed stress layer can be closer to the channel, _ increase electron or electricity The movement rate of the hole in the channel, the purpose. However, when performing the engraving process, the metallization layer 22 and % are directly exposed to the cooking environment without any protection. Therefore, after the Lai process, 'especially after excessive surnames' Layers 22 and % will suffer from etch damage so that sheet resistance is not achieved. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can prevent a damage of a Wei gold emitter layer when the wall is cut. The present invention provides a method of fabricating a semiconductor device by first forming a transistor on a substrate including a gate structure and a source/drain region, wherein the gate structure includes a gate conductor layer, The gate dielectric layer and a spacer, the gate dielectric layer > M is between the gate conductor layer and the substrate, and the spacer is located at a sidewall of the gate conductor layer. Next, a metal telluride layer is formed on the surface of the gate conductor layer and the source/drain region of the transistor. Thereafter, a surface treatment step is performed to selectively form a protective layer on the metal telluride layer, the material of the protective layer being different from the material of the voids on the sidewalls of the gate conductor layer. Thereafter, a protective layer is used as a mask to remove a portion of the spacer to reduce the width of the spacer to provide a gap between the spacer and the metallized layer. Thereafter, a stress layer is formed on the substrate to cover the spacer, the protective layer, and the gap between the spacer and the metal telluride layer. In accordance with an embodiment of the invention, the step of forming the metal telluride on the surface of the gate conductor layer and the source/nothotropic region comprises forming a layer on the substrate. a metal layer, followed by a first tempering step to react the metal layer with the surface of the gate conductor layer and the source/drain regions to form the metal halide layer, and then selectively remove unreacted metal Layer, followed by a second tempering step. According to the implementation of the fourth (4), the silk processing is performed between the step of selectively removing the unreacted metal layer and the step of performing the second tempering step or the second tempering After the step, the step of removing a portion of the spacer is performed. According to an embodiment of the invention, the surface treatment step comprises an oxygen oxidation process. The oxidation process includes a wet oxidation process or a wet process. The wet oxidation method can be carried out by using an aqueous solution of nitrogen peroxide, an ozone water-soluble two-oxidation method, or a gasification method, and can be used as a reaction gas by using oxygen, ozone, nitrous oxide or oxidized mice or a combination thereof. According to the description, the surface treatment step includes a nitrogen gas as a reverse fiber 彡 彡 彡 method, such as Tong Guan Lu and hydrogen, or ammonia zinc, (four), said the above-mentioned gold 4 impurities including titanium, drill, The combination of metal and its combined cut. The stratified layer, the x-preserving element, includes a transistor, a metal-stone-gate structure, and an ikt stress layer. The transistor is located on the substrate, and includes a gate electrode structure, wherein the gate structure comprises a gate conductor %g and a spacer wall, and the gate dielectric layer is interposed between the gate conductor layer and the substrate 200818253 UMCD Between -2006-0112 19814twf.doc/t, the spacer is located on the sidewall of the gate conductor layer. The metal telluride layer is located on the surface of the source/; and the polar region and the gate conductor layer, and has a gap between the metal telluride layer on the source/drain region and the spacer. The protective layer covers the metal dream layer' but does not cover the spacers. A stress layer covering the spacers and the protective layer and the voids. According to the present invention, the above-mentioned protection includes a metal oxide, a metal nitride or a metal oxynitride. According to an embodiment of the present invention, the metal halide includes a titanium compound of titanium, cobalt, nickel, 'm mesh, an alloy of the foregoing metals, or a combination thereof. According to an embodiment of the invention, the stress layer comprises a compressive stress layer or a tensile stress layer. The present invention performs a surface treatment step 'to react the surface of the metal telluride layer to form a protective layer before the step of reducing the gap width, so that the etching process of the metal dream layer can be avoided in the subsequent reduction of the spacer width. Suffered from damage. The above and other objects, features, and advantages of the present invention will become more apparent and understood. 1A to 1D are cross-sectional views showing a flow of a method for fabricating a semiconductor or an element according to an embodiment of the present invention. Referring to Figure 1A, an isolation structure 101 is formed in a substrate 1 to define an active region 150. Thereafter, a transistor 1〇2 is formed in the active region 15A. The transistor 102 includes a gate structure 1〇3 and a source/drain region 118. The substrate 100 is, for example, a bulk substrate or a substrate having germanium (SOI) on the insulating layer, such as a germanium, an epitaxial germanium, a germanium, a lithotripar, a chemical, a carbonized stone, 200818253 UMCD-2006- 0112 19814twf.doc/t or a combination thereof. The forming method of the transistor 102 is, for example, a gate dielectric layer of the germanium and a gate conductor layer, a layer of a cerium, a nitrogen oxide, or a dielectric emulsification such as a broad layer, a layer, and a second layer; It. Gate 11?, 10 days r0C? Doped source/pole or 疋 source/bend extension 112. In this embodiment, the pole/> and the polar region 112 are used to form the source/substrate in the substrate 100/, the 隹, .. 3⁄4(4)118 Miscellaneous 116' or source/dual contact area ιΐ6. This is described in the "only 1" by the heavily doped source/drain region 116. The material of the spacers 114 is, for example, cerium oxide or a dream of nitriding. Prior to the formation of the impurity 114, a liner 108 may be formed on the sidewall of the gate conductor layer 106, as shown in Figure 2, as shown in Figure 2. Referring to the figure, in the example, the material of the spacer 114 is tantalum nitride, and the material of the lining layer 108 can be smashed. Referring to Figure 2, in another embodiment, the material of the spacer 114
If氧化r夺，舰層108與110之材質可以分別是氧化石夕與氮 石夕、。通常，依照製程的需要，在形成襯層108之前，還可^ 閘極V體層1〇6的側壁先形成一個或兩個補償間隙壁(〇饱纣 =、Cer)(未緣示）。在此實施例中，是以圖1A來說明本發明之 半導體元件的製造流程。 " 200818253 UMCD-2006-0112 19814twf.doc/t 源極/汲極區118的摻雜例如是N型摻雜或是p型摻雜。 N型摻雜例如是碱坤；P型摻雜例如是删。纟—實施例中， 請參照圖1A，源極/没極區118的形成方法可以採用離子植入 方式’將摻雜直接植入於基底100之中，以形成淡摻雜源極/ 汲極區112與濃摻雜源極/汲極區116。在另一實施例中，請參 照圖2，源極/汲極區118的形成方法，可以在形成閑極導= 106之後，以蝕刻方式將閘極導體層1〇6兩侧預定形成源極/ 汲極區118的區域飿刻去除，以形成凹陷13〇，之後，先在凹 陷130中回填不同於基底1〇〇的其他材質層132，再進行離子 植入製程，⑽成祕賴極/蹄區112與濃雜源極/沒極 ，116。回填的材質層132的方法可以採用化學氣相沈積法或 是蟲晶的方式來完成之。在P型金氧半電晶體的實例中，回 ，的材質層132例如是魏鍺；在N型金氧半電晶體的實例 中’回填的材質層132例如是碳化石夕。 其後’在基底1〇〇上形成一層金屬層，金屬層㈣之 材質例如是鈦、姑、鎳、始、把、銦、前述金屬之合金或其組 合0 叫芩知、圖1B，進行回火製程，使金屬層12〇與閘極導體 =106以及源極/汲_ 118表面的石夕反應，以分別在問極導 體層1〇6以及源極/汲極區m形成金屬石夕化物層122盥124。 ==可以採用快速熱回火製程。回火的溫度和時間與所選 擇的金屬層120的材質特性有關。 、曾請爹照® 1C，選擇性移除未反應的金屬層12〇，使閑極 ¥體層106以及源極/汲極區118上的金屬石夕化物層122與124 200818253 UMCD-2006-0112 19814twf.d〇c/t 裸露出來。選擇性移除未反應的金屬層12〇的方法可以採用濕 式勉刻法’例如是以硫酸和雙氧水所組成的混合溶液（Sul也ricIf the oxidation is r, the materials of the ship layers 108 and 110 can be oxidized stone and nitrous oxide, respectively. Generally, in accordance with the needs of the process, before the formation of the liner 108, the sidewalls of the gate V body layer 1〇6 may first form one or two compensation spacers (not shown). In this embodiment, the manufacturing process of the semiconductor device of the present invention will be described with reference to Fig. 1A. " 200818253 UMCD-2006-0112 19814twf.doc/t The doping of the source/drain region 118 is, for example, N-type doping or p-type doping. The N-type doping is, for example, an alkalinity; the P-type doping is, for example, deletion. In an embodiment, referring to FIG. 1A, the method of forming the source/no-pole region 118 may be implanted directly into the substrate 100 by ion implantation to form a lightly doped source/drain. Region 112 and concentrated doped source/drain region 116. In another embodiment, referring to FIG. 2, the source/drain region 118 may be formed by etching the sidewalls of the gate conductor layer 1〇6 to form a source after the formation of the idle electrode=106. / The region of the drain region 118 is removed to form a recess 13 〇, after which the other material layer 132 different from the substrate 1 回 is backfilled in the recess 130, and then the ion implantation process is performed, and (10) Hoof area 112 and dense source/no pole, 116. The method of backfilling the material layer 132 can be accomplished by chemical vapor deposition or insect crystal. In the example of the P-type MOS transistor, the material layer 132 of the back is, for example, Wei Wei; in the example of the N-type MOS transistor, the backfill material layer 132 is, for example, carbon carbide. Thereafter, a metal layer is formed on the substrate 1 , and the material of the metal layer (4) is, for example, titanium, ruthenium, nickel, ruthenium, ruthenium, indium, an alloy of the foregoing metal or a combination thereof, which is called 芩, FIG. 1B, and is returned. The fire process causes the metal layer 12〇 to react with the gate conductor=106 and the source/汲_118 surface to form a metallization in the interrogation conductor layer 1〇6 and the source/drain region m, respectively. Layer 122盥124. == A fast thermal tempering process can be used. The temperature and time of tempering are related to the material properties of the selected metal layer 120. I have chosen to remove the unreacted metal layer 12〇 to make the free layer body layer 106 and the metal-lithium layer 122 on the source/drain region 118 and 124 200818253 UMCD-2006-0112 19814twf.d〇c/t barely exposed. The method of selectively removing the unreacted metal layer 12 可以 may employ a wet engraving method, for example, a mixed solution composed of sulfuric acid and hydrogen peroxide (Sul also ric
Acid Hydrogen Peroxide Mixture，SPM)、氨水和雙氧水所組 成的混合溶液（Ammonia Hydrogen Peroxide Mixture，ΑΡΜ) 或疋鹽酸和雙氧水所組成的混合溶液（Hydrochloric peroxide Mixture，HPM)做為蝕刻劑。 ' 其後，依據所形成的金屬矽化物層122與124材質的不 拳 同，可以再進行第二次的回火，以使所形成的金屬石夕化物層 =2與124具有更佳的特性，例如是更低的阻值或更好的熱穩 定性。第二次回火的製程可以採用快速熱回火製程。回火的溫 度和時間與所選擇的金屬層120的材質特性有關。 請繼續參照圖1C，為使後續形成的應力層發揮更好的應 力政果’通常，會在形成應力層之前，先進行一個蝕刻製程， 以削減，隙壁114的寬度W1，使後續形成的應力層能更接近 通道，藉以增加電子或電洞在通道中的移動率。然而，在進 • 刻製程時，若是金屬矽化物層122與^々直接暴露於钱刻 晨k中，無任何的保護，在進行姓刻製程之後，尤其是過度餘 • 〗後孟屬石夕化物層m與124將會遭受飿刻的破壞，以致片 、 電阻無法達到所需。本發明在進行削減間隙壁114寬度W1的 =驟之前，先進行一個表面處理步驟，可在金屬矽化物層122 與丨24的表面反應形成一層保護層126、128，避免金屬矽化 物層122與124在後續的製程中遭受破壞。 表面處理步驟可以是—氧化步驟、—氮化步驟或—I氧化 步驟，其可氧化、氮化或氮氧化金屬石夕化物層122與124的表 200818253 UMCD-2006-0112 198l4twf.d〇c/t 面，形成一層保護層126、128 保護層126、128可以發 理步驟所形賴 中，間隙壁114之材質為肩务功*队擇性在一貫施例 步驟，其可以氧化金屬=物以是， ===:練或_為氧=== j、，_氧化二氮或 形成金屬氮化物保護層126、128。气化牛、又 化法。乾織法树嶋氮===== =乳和氫氣、或氨氣做為反應氣體。在另一實施例中，= 2可:氧化矽，表面處理步驟可以是-氮氧化步驟， ，、了虱乳化金屬矽化物層122與124的表面，形成金屬 :偏蔓層126、128。氮氧化步驟可以採用乾式氮氧化= 乳化法可U在含氮及氧的錢魏巾例如是以 氮或一氧化氮做為反應氣體以進行氮氧化反應。 — 制請參照圖1D ’當保護層126、126形成之後，進行一 ^程’以削減間隙壁114的寬度W卜使所留下的寬度 乍的間隙壁114a與該金屬矽化物層之間具有一空隙 = 11 200818253 UMCD-2006-0112 19814twf.doc/t 链刻的過程中，保護層126、126可⑽絲幕贿護石夕化物 層m與m雜在侧的過程中遭受破壞，因此，本發明可 以银刻去除較多的赚壁114，使後續形成的應力層更^近通 道。削減間隙壁114寬度的姓刻製程可以採用濕式飯刻法、乾 式侧法或是氣相蚀刻法。在-實施例中，間隙壁m為氮化 .矽時，濕式侧法可以採甩熱碟g复做為姻劑；乾式姓刻法可 =將基底1GG的溫度維持在較高於所通人的蝴氣體的溫度 採用含有氟化氫氣體以及氣相的預氧化劑（predefined =z_gent)如概、臭氧、過氧化氯、過氯酸(hyp〇chi〇_ Ιια紐、氧、硫喊_做為侧氣體進行侧；氣相 叔可以絲底100的溫度維持在攝氏125度，通入益水氣 為氣體進行侧。料—實施例中，_壁114 ，濕式侧法可以採用氫驗做為蝴劑；乾式姓 ==，CF4的賴職刻。氣相罐可 114a刚上形成一層應力層129，以覆蓋間隙壁 本i曰""力層129為屢縮應力層，其可以在P型全氧 2 Γ/&通道方向形成i縮應力，以提升載 声，1 、里孟虱半電晶體的實例中，應力層129為拉伸 久IS:。半電晶體中沿著通道方向形成拉伸 了，升载子的移動率。由於間_ 114 #寬度被削減 金屬^度較窄，且在間隙壁⑽與 曰24之間形成空隙14〇,因此，應力層129可以 200818253 UMCD-2006-0112 19814twf.doc/t 較接近通道，發揮更大的應力效果。 請參照圖3以及圖1A至圖1D，本發 =需在削減間隙壁114寬度的步驟之;進行:即二 護金屬矽化物層122與124之效果。亦即 :皁保 ==時機，枝基底個上形成電《 層1〇6與源極/汲極區m上形成金屬石夕化物層⑵盘 步驟302以及步驟310之後，進行削減間隙壁114之寬度= 的步驟314與形成應力層129之步驟316之前。 、又 ιίί體地說，表面處理步驟312可以在:第二次回火的 亍，也可以在進行第二切火的步驟之後施行。 口月茶妝圖4以及圖1A至圖1D，在一實施 =步，3U可以在進行第二次回火的步驟之前施行。更二 進行步驟逝’在基底⑽上形成電晶體脱。接^ =3〇4，在基底議上形成金屬層12〇。之後 于第一次回火步驟，以形成金屬石夕化物層⑵與 之後:、n仃步驟遍’選擇性去除未反應的金屬層12〇。 理對驟312 ’對金屬石夕化物層122與124進行表面處 =屬槪物層122與124進行表面處理後，進 =^金屬石夕化物層122與124進行第二 以採用、、ϋ應力Λ129。在步驟312中’表面處理的方法可 的太、:…或乾式法。由於選擇性去除未反應的金屬層120 ^^通常是_選擇性濕式_法，因此，若是表面處 法抓用濕式法，則可以臨場Un-situ)同步進行，其製程方 13 200818253 XJMCD-2006-0112 19814twf.doc/t 便且快速。Acid Hydrogen Peroxide Mixture (SPM), a mixture of ammonia and hydrogen peroxide (Ammonia Hydrogen Peroxide Mixture), or a mixture of hydrochloric acid and hydrogen peroxide (HPM) as an etchant. Then, depending on the material of the metal telluride layers 122 and 124 formed, a second tempering can be performed to make the formed metallization layer = 2 and 124 have better characteristics. For example, lower resistance or better thermal stability. The second tempering process can be performed using a rapid thermal tempering process. The temperature and time of tempering are related to the material properties of the selected metal layer 120. Continuing to refer to FIG. 1C, in order to make the subsequently formed stress layer exert a better stress policy, generally, an etching process is performed to reduce the width W1 of the spacer 114 before the formation of the stress layer, so that the subsequent formation is performed. The stress layer can be closer to the channel to increase the mobility of electrons or holes in the channel. However, in the process of engraving, if the metal telluride layer 122 and ^々 are directly exposed to the money in the morning, there is no protection, after the process of surname engraving, especially after excessively. The layers m and 124 will suffer from engraving damage, so that the sheets and resistors are not as good as needed. In the present invention, before performing the step of reducing the width W1 of the spacer 114, a surface treatment step is performed to form a protective layer 126, 128 on the surface of the metal telluride layer 122 and the crucible 24 to avoid the metal telluride layer 122. 124 suffered damage in subsequent processes. The surface treatment step may be an oxidation step, a nitridation step or an -I oxidation step, which can oxidize, nitride or oxidize the metal lithium layer 122 and 124. 200818253 UMCD-2006-0112 198l4twf.d〇c/ The t-plane forms a protective layer 126, 128. The protective layers 126, 128 can be shaped by the processing step. The material of the spacer 114 is a shoulder-to-work function. In the consistent application step, the metal layer can be oxidized. Yes, ===: practice or _ is oxygen === j,, _ nitrous oxide or form metal nitride protective layers 126, 128. Gasification of cattle, and the law. Dry weave tree 嶋 nitrogen ===== = milk and hydrogen, or ammonia as a reaction gas. In another embodiment, = 2 may be: yttrium oxide, the surface treatment step may be a nitrogen oxidizing step, and the surface of the ruthenium metal halide layers 122 and 124 may be formed to form a metal: vine layer 126, 128. The nitrogen oxidation step may be carried out by dry nitrogen oxidation = emulsification method. In the nitrogen and oxygen-containing money, for example, nitrogen or nitrogen monoxide is used as a reaction gas for the nitrogen oxidation reaction. - Referring to FIG. 1D 'When the protective layers 126, 126 are formed, a process is performed to reduce the width of the spacers 114, so that the gaps 114a of the remaining width 乍 are provided between the spacers 114a and the metal telluride layer. A void = 11 200818253 UMCD-2006-0112 19814twf.doc/t During the engraving process, the protective layers 126, 126 can be damaged in the process of bridging the layer of m and m on the side, therefore, The invention can remove more earning walls 114 by silver engraving, so that the subsequently formed stress layer is closer to the channel. The process of cutting the width of the spacer 114 may be a wet cooking method, a dry side method or a vapor phase etching method. In the embodiment, when the spacer m is nitrided, the wet side method can be used as a refrigerant for the hot plate g; the dry type method can be used to maintain the temperature of the substrate 1GG higher than that of the pass. The temperature of the human butterfly gas is a pre-oxidant containing hydrogen fluoride gas and a gas phase (predefined = z_gent) such as ozone, chlorine peroxide, perchloric acid (hyp〇chi〇_ Ιια New Zealand, oxygen, sulfur shouting _ as the side The gas is carried out on the side; the temperature of the gas phase can be maintained at 125 degrees Celsius, and the water is supplied to the side of the gas. In the embodiment - the wall 114, the wet side method can be used as a butterfly. Agent; dry type surname ==, CF4's job. Gas phase can 114a just formed a layer of stress layer 129 to cover the gap wall i" "" force layer 129 is a contraction stress layer, which can be in P The type of all-oxygen 2 Γ/& channel direction forms i-shrinkage stress to enhance the acoustic load. 1. In the example of the Riememix semi-transistor, the stress layer 129 is a tensile long-term IS: the direction along the channel in the semi-transistor Forming the stretched, lifted carrier's mobility. Since the _114 #width is cut, the metal is narrower and the spacer (10) is The gap 14 is formed between the crucibles 24, so that the stress layer 129 can exert a greater stress effect closer to the channel in 200818253 UMCD-2006-0112 19814twf.doc/t. Please refer to FIG. 3 and FIG. 1A to FIG. = the step of reducing the width of the spacer 114; performing: the effect of the second metallization layer 122 and 124. That is, the soap protection == timing, the formation of electricity on the base of the branch "layer 1 〇 6 and source After forming the metal lithium layer (2) on the drain region m, the step 302 and the step 310 are performed, and the step 314 of reducing the width of the spacer 114 is performed before the step 316 of forming the stress layer 129. Further, the surface is The processing step 312 may be performed after the second tempering, or after the second cutting step. The moon and the moon makeup figure 4 and FIG. 1A to FIG. 1D, in an implementation=step, 3U may be performed The second tempering step is performed before the second step. The second step is performed to form a transistor on the substrate (10). The connection is ^=3〇4, and the metal layer 12 is formed on the substrate. After the first tempering step, Forming a metallization layer (2) and after: n仃 step through 'selectivity Except for the unreacted metal layer 12, after the surface of the metal lithium layers 122 and 124 is surface-treated, the surface layers 122 and 124 are surface-treated, and then the metal-lithium layers 122 and 124 are formed. Performing a second to employ, ϋ stress Λ 129. In step 312, the method of surface treatment may be too, ... or dry method. Since the selective removal of the unreacted metal layer 120 ^ ^ is usually _ selective wet _ The law, therefore, if the surface method is to use the wet method, it can be carried out simultaneously in the un-situ, and the process side 13 200818253 XJMCD-2006-0112 19814twf.doc/t is fast and fast.
请參照圖5以及圖认至圖m，在另一實施例中，表面處 理步，312可以在進行第二次回火的步驟313乂後施行。更具 體'也况、’疋先進行步驟3〇2，在基底應上形成電晶體1〇2。 接著，進行步驟304，在基底1〇〇上形成金屬層120。之後， ，行步驟306,進行第—次回火步驟，以形成金屬⑪化物層 舁124。―然後，進行步驟3〇8，去除未反應的金屬層12〇。其 後’進行步驟313，對金屬石夕化物層122與124進行第二次回 讀程。之後，進行步驟312，對金屬石夕化物層122與124進 订表面處理。驗，進行步驟314，削減間隙壁I〗# W1 ’之後’再進行步驟316，形成應力層n 、 本發明之半導體元件製造方法中，因為在形成應力層之前 先進灯了削減間隙壁寬度的步驟，因此，應力層與通道之 距離減知可提高沿著通道方向的壓縮應力或拉伸應^，、 故可有效增加電子或電洞在通道巾的㈣率。: 打削減_壁寬度的步驟之前，先進行—悔喊理步 金屬石夕化物層的表面反應形成—層保護層，因此，， 石夕化物層在後續的削減間隙壁寬度的侧製程 =屬 【圖式簡單說明】 、議壤。 圖1A至圖1D是依照本發明一實施例所緣示之 體元件的製造方法流程剖面圖。 種+蛉 圖2疋依照本發明另一實施例所綠示之一 的製造方法之部分圖。 種體讀 圖3是依照本發明一實施例所繪示之一種半導體元件的 14 200818253 UMCD-2006-0112 19814twf.doc/t 製造方法的流程圖。 圖4是依照本發明另一實施例所繪示之一種半導體元件 的製造方法的流程圖。 圖5是依照本發明又一實施例所繪示之一種丰導 的製造方法的流程圖。 圖6A至6B繪示習知一種增加電子或電洞在通道中的 • 移動率之半導體元件的剖面示意圖。 • 【主要元件符號說明】 10、100 :基底 20、102 :電晶體 13、 103 :閘極結構 14、 114 :間隙壁 22、24、122、124 :金屬矽化物層 101 :隔離結構 104 ··閘介電層 • 106 :閘極導體層 108、110 :襯層 • 1·淡推雜源極/没極區、源極/；；及極延伸區 116 ·》辰播雜源極/》及極區 118 ·源極/没極區 120 :金屬層 126、128 ··保護層 129 :應力層 130 :凹陷 15 200818253 UMCD-2006-0112 19814twf.doc/t 132 :材質層 140 :空隙 150 ·主動區 S卜S2、W卜W2 :寬度 302〜316 :步驟 16Referring to Figure 5 and to Figure m, in another embodiment, the surface treatment step 312 can be performed after the second tempering step 313. More specific, then, step 3〇2, and a transistor 1〇2 is formed on the substrate. Next, in step 304, a metal layer 120 is formed on the substrate 1 . Thereafter, in step 306, a first tempering step is performed to form a metal 11 layer 舁124. ― Then, proceed to step 3〇8 to remove the unreacted metal layer 12〇. Thereafter, step 313 is performed to perform a second readback of the metallization layers 122 and 124. Thereafter, in step 312, the metallization layers 122 and 124 are subjected to a surface treatment. In step 314, after the spacers I # # W1 ' is reduced, step 316 is further performed to form the stress layer n. In the semiconductor device manufacturing method of the present invention, the step of reducing the spacer width by the advanced lamp before forming the stress layer is performed. Therefore, the distance between the stress layer and the channel can be reduced to increase the compressive stress or tensile force along the channel direction, so that the electron or hole can be effectively increased in the channel area. : Before the step of reducing the width of the wall, the surface layer of the repentant metallurgical layer is formed to form a protective layer. Therefore, the side process of the Shiyake layer in the subsequent reduction of the gap width is [Simple description of the map], talk. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1A through 1D are cross-sectional views showing the flow of a method of manufacturing a body member according to an embodiment of the present invention. Fig. 2 is a partial view showing a manufacturing method of one of greens according to another embodiment of the present invention. 3 is a flow chart of a manufacturing method of a semiconductor device 14 200818253 UMCD-2006-0112 19814 twf.doc/t according to an embodiment of the invention. 4 is a flow chart showing a method of fabricating a semiconductor device in accordance with another embodiment of the present invention. FIG. 5 is a flow chart showing a manufacturing method of a rich guide according to still another embodiment of the present invention. 6A to 6B are schematic cross-sectional views showing a conventional semiconductor element for increasing the mobility of an electron or a hole in a channel. • [Main component symbol description] 10, 100: substrate 20, 102: transistor 13, 103: gate structure 14, 114: spacers 22, 24, 122, 124: metal telluride layer 101: isolation structure 104 · Gate dielectric layer • 106: gate conductor layer 108, 110: lining • 1· faintly source/poleless region, source/;; and pole extension region 116 · "Chen broadcast source/" Polar region 118 · Source/polarity region 120: Metal layer 126, 128 · Protective layer 129: Stress layer 130: Sag 15 200818253 UMCD-2006-0112 19814twf.doc/t 132 : Material layer 140: Void 150 · Active Area S Bu S2, W Bu W2: Width 302~316: Step 16