TW200816659A - A receiver for reducing intersymbol interference of a channel and compensating for signal gain loss, and method thereof - Google Patents

Abstract

Example embodiments are directed to a receiver for reducing ISI of at least one data transmission channel and compensating for signal gain loss, and method thereof. A receiver may include a high pass filter and a Schmitt trigger controlled by a plurality of first control signals and a plurality of second control signals. The plurality of first control signals and the plurality of second control signals may be used to shift a first trigger voltage and a second trigger voltage of the Schmitt trigger. A method of reducing intersymbol interference and compensating for signal gain loss of a receiver connected to at least one data transmission channel is also provided.

Description

200816659 IX. Description of the Invention: [Technical Field of the Invention] Example embodiments relate to an electronic circuit, for example, to a receiver for reducing mark interference (ISI) in a data transmission channel and compensating for signal gain loss And its method. ~ [Prior Art] • As the operating speed of semiconductor wafers increases, the data transfer rate can also increase. The data input/output rate can also be increased due to the limitation on the number of pins in the semiconductor wafer. Isi can cause degradation in signal quality in non-linear components of the data transmission channel. Figure 1 illustrates an example of a circuit for a conventional data transmission channel. Referring to Figure i, the signal A output by the transmitter 110 can be transmitted to the receiver 13A via the channel 12A. Receiver 130 can include a signal B that can pass through channel 12 and a reference voltage

Vref compares comparator 132 and an amplifier 134 that amplifies the output signal of comparator 132. 2A, 2B and 2C illustrate example waveforms of signals transmitted through the data transmission channel of Fig. i. Figure 2A illustrates an example signal A output from the transmitter 110 of Figure 1. Figure 2B illustrates an example signal b through the channel 12 of the drawing. Figure % says - The example of the amplifier of Figure 1 outputs the signal CO. The output of amplifier 134, #号 can have the "eye" characteristic as illustrated in Figure 3. Referring to Figure 3, there may be two eyes in the signal C〇, and the jitter noise can be widely distributed between the two eyes. This jitter noise can be caused by ISI. A signal shaper circuit as disclosed in U.S. Patent No. 5,565,8,12, is incorporated to remove jitter noise caused by ISI of the data transmission channel. See 122081.doc 200816659 FIG. 4, the signal shaper circuit can include a high pass filter 221 (which can include a switched capacitor to receive an input signal ΙΝ), a comparator 222, a capacitor 223, and a Schmitt. Trigger 224. The high pass filter 221 can include two similarly constructed gain stages a & b with a nominal gain of about 1 〇 and a time constant of about 50 sample periods. The second gain stage B can be followed by a comparator 222. The gain stage can have a balanced fully differential structure. This example architecture improves power supply parasitic rejection and immunity. The amplifier can be designed in such a way that its common mode operating point can be stabilized. Comparator 222 can have differential inputs and single-ended outputs provided by gain stages A and B, and can provide a first approximation of the incoming digital signals. Capacitor 223 can be added to the output of comparator 222 to limit its high frequency response. The Schmitt trigger Μ* restores the logic level. The combination of comparator 222 and Schmitt trigger reduces very fast noise spikes which can be additionally sampled and misinterpreted. The signal shaper circuit illustrated in Figure 4 can have the frequency response characteristics illustrated in Figure 5. Referring to Fig. 5, in order to receive an input signal IN modulated at a specific frequency, noise in a frequency band other than the modulation frequency can be removed. The noise from the lower frequency band can be removed by controlling the cutoff frequency of the switched capacitor, and the Schmitt trigger 224 can be used to remove noise from the higher frequency band. That is, the signal shaper circuit illustrated in Figure 4 can improve the signal-to-noise ratio (SNR) of the signal. The characteristics of the data transmission channel can vary with frequency. (For example, 'Figure 4 The signal shaper circuit described can vary with the channel characteristics of the description, and the ugly U cup can be determined by the frequency. The loss of 12208l.d〇 can be mitigated by the loss of the data transmission channel (8) and the video rate. (200816659 Loss of the receiver can help mitigate some of the harmful effects. [Inventive] Example embodiments relate to one for reducing at least one a receiver and method for marking interference and compensating for signal gain loss within a data transmission channel. Ο u According to an example embodiment, the receiver may include a high-pass chopper, and a Schmitt trigger, Controlled by the plurality of first control signals and the plurality of second control signals, the plurality of first control signals and the plurality of second control signals can be used to shift one of the first trigger voltages of the Schmitt trigger a trigger voltage. The high pass filter can be configured to receive a first input signal through the first channel, and the Schmitt trigger can be configured to respond to the plurality of first control signals and the complex The second control signal compares the first signal from the high pass filter with a first supply voltage and generates a first output signal and a second output signal. The method includes: a controller configured to generate the plurality of first control signals and the plurality of second control signals; and an amplifier configured to receive the first output signal and the second output signal and Generating an output signal of the receiver. The Schmitt trigger may include a first resistor and a second resistor, a first NMOS transistor to a fourth (10) transistor, and a first flip-flop voltage controller and a second a trigger voltage controller. The first resistor and the second resistor may have a first power supply to which the second power source can be applied. The first NM〇S transistor may have a connection to the first resistor a second terminal: the second output signal of the second output signal, and the first signal from the high-pass filter can be applied to the gate of the 一 明 k ^ to the gate. The second NMOS transistor can have 122081. Doc 200816659

- connected to a second terminal of the second resistor to output the drain of the number, and (d) - a supply voltage to which the gate can be applied. The second NMOS transistor can have a drain connected to the second material of the first resistor, and the first output signal can be applied to the gate. The fourth NMOS transistor can have a drain connected to the second terminal of the second resistor, and the second output signal can be applied to one of the gates. The first trigger voltage controller is connectable to the source of the first NM〇s transistor and the second NMOS transistor and to the ground voltage source, and is controllable by the plurality of second control signals. The second flip-flop voltage controller is connectable to the third NMOS transistor and the source of the wNM 〇s transistor and the ground voltage source and can be controlled by the plurality of first control signals. The first flip-flop voltage controller may include: a plurality of current sources connected to the first NMOS transistor and the source of the second NM 〇s transistor; and a plurality of NMOS transistors each having a respective Connected to one of the plurality of current sources and the ground voltage source. The gate of one of the plurality of NM〇s transistors can receive one of the plurality of second control signals, respectively. The second flip-flop voltage controller may include: a plurality of current sources connected to the third NMOS transistor and the sources of the fourth NMOS transistor; and a plurality of NMOS transistors each connected to the respective One of the plurality of current sources and the ground voltage source. The gate of each of the plurality of NMOS transistors can respectively receive one of the plurality of first control signals. The high pass filter can include a capacitor and a resistor. The capacitor can be 122081.doc 200816659 having the first input signal through the first channel can be applied to one of the first terminals. The resistor is connectable to a second terminal of the capacitor and a source of the first supply voltage. The signal of the second terminal of the capacitor can be changed to the first signal from the high pass filter. Ο

The first supply voltage can be a termination voltage applied to the first channel. The pass filter may be further configured to receive a first input signal through a second channel, and the Schmitt trigger may be further configured to respond to the plurality of first control signals and the plurality of The second control signal compares a second signal from the clear-back filter to a first supply voltage. For a second input signal, the Schmitt trigger can include a first resistance state and a first resistor. The first NMOS transistor to the fourth transistor=and the first flip-flop voltage controller and the second flip-flop voltage controller, the first resistor and the second resistor may have a power supply voltage applicable to the: terminal The HNMOS transistor may have a drain connected to the first terminal of the first resistor to output the second output signal, and the first signal from the high pass filter may be applied to one of the gates. The second NMOS transistor can have a second component connected to the first resistor to output a <4 first-output signal, and the second signal from the high-pass chopper can be applied thereto - Gate. The third N-picture transistor can have a drain connected to the second terminal of the first resistor, and the first output 1 can be applied to one of the drains. The fourth NMOS transistor may have a drain connected to the second resistor of the second resistor, and the second output 4 may be applied to one of the gates. (3⁄4. Gu Chu. The gate of the brother-trigger voltage controller can be connected to 122081.doc 200816659 to 5 Xuanyuan an NMOS transistor and the source of the second NMOS transistor and a ground voltage source, and can be Controlled by a plurality of second control signals, the second trigger voltage controller is connectable to the third NMOS transistor and the source of the fourth NMOS transistor and the ground voltage source, and can be the plurality of first control signals The first trigger voltage controller may include: a plurality of current sources connected to the first first NMOS transistor and the second NMOS transistor; and a plurality of NMOS transistors Each of the plurality of NMOS current sources is coupled to one of the plurality of 〇 current sources and the ground voltage source. The gate of each of the plurality of NMOS transistors can receive one of the plurality of second control signals, respectively. The second trigger voltage controller may include: a plurality of a current source connected to the second source of the second NMOS transistor and the fourth NM〇s transistor; and a plurality of NMOS transistors each connected to one of the plurality of current sources and The ground voltage source, the gate of each of the plurality of nm〇s transistors r + may be purely one of the plurality of plurality of first control signals. The high pass filter may include a first capacitor and a second a capacitor and a first and a second resistor. The first capacitor may have a first terminal to which the first input signal of the first pass can be applied. The first resistor can be connected to a second terminal of the first capacitor and a source of the first power voltage. The second capacitor may have the second input signal through the second channel applicable to the first terminal. The second resistor may be connected a signal to the second terminal of the second capacitor and the source of the first power voltage 122081.doc 200816659 the second terminal of the container may be the first signal from the high pass filter, and the first The signal of the second terminal of the two capacitors can be changed from The first power supply voltage may be a termination voltage applied to each of the at least one (four) - a receiver for connecting to at least one data transmission The method for reducing the internal marker interference and compensating for the signal gain loss may include: receiving at least one input signal through a corresponding channel; generating a first output signal by using a high pass filter in response to the at least one input signal; generating a plurality of a first control signal and a plurality of second control signals for shifting a first trigger voltage and a second trigger voltage of a Schmitt trigger; by responding to the plurality of first control signals and the plurality of The second control signal compares the first output signal with a first power supply voltage to generate a second output signal and a third output signal; and generates the receiving in response to the second output signal and the third output signal One of the output signals. Therefore, the receiver can use the high pass filter and the Schmitt trigger controlled by the first control k number and the second control signal to compensate for the ISI and signal gain loss of a data transmission channel. [Embodiment] Example embodiments detailed in the text are disclosed herein. However, the specific structural and functional details disclosed herein are merely representative of the described embodiments. However, the example embodiments may be embodied in many alternate forms and should not be construed as being limited to the embodiments set forth herein. Accordingly, while example embodiments are capable of various modifications and alternatives, the examples are shown by way of example in the drawings and will be described in detail herein. The examples are to be construed as being limited to the details of the embodiments of the example embodiments. Throughout the description of the figures, the same numbers refer to the same elements. Ο Ο It should be understood that 'although the terms second, etc. may be used herein to describe various elements', such elements should not be limited by the terms. These terms are only used to distinguish between components. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the example embodiments. As used herein, the term "and/or" includes any of the associated items or any combination of all and all combinations 0 should be understood when an element is referred to as "connected, or" When connected to another component, it may be directly connected or coupled to another component, or an intervening component may be present. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intervening elements. Other terms used to describe the relationship between the elements should be interpreted in the same manner (eg, "Between,, and, directly between.···, "proximity" and "directly adjacent", etc.). The terminology used herein is for the purpose of the description and the embodiments As used herein, the singular and "the" are also intended to include the plural. It should be further understood that the term "comprising" and / or "comprises" or "an" or "an" Features, Integers, Steps 122081.doc -12- 200816659 Steps, Operations: The presence or addition of components, components, and/or groups thereof. '' In some alternative embodiments, the functions/acts may not occur in the order described in the figures. For example, two figures that are continually displayed depending on the functionality/actions described may in fact be performed substantially concurrently or may sometimes be performed in the reverse order. ^ Item 7 illustrates a receiver 730 in accordance with an example embodiment. Referring to Fig. 7, the signal A output from the transmitter 71A in the 仏7 mode can be transmitted via the channel. Transfer to the receiver 730. Receiver 730 can include a high pass filter 740, a control RC 75(), a Schmitt trigger 760, and an amplifier 770. The pass filter 740 can include a capacitor 742 having a first terminal that can receive the signal b through the channel 720, and a resistor 744 coupled to the second terminal of the valley 742 and the first supply voltage source. The controller 750 can generate a first control signal x[m:〇]& second control signal γ[η:〇] to control the first trigger voltage Vth_〇 and the second trigger voltage Vth of the Schmitt trigger 76〇 One 1. The Schmitt trigger 760 can respond to the first control signal X[m: 〇] and the second control signal γ[η: 〇] and output the high-pass filter 740 to the first power supply voltage V-term. The comparison is made and the output signals OUT and /OUT can be generated. Amplifier 770 amplifies the output signal of the Schmitt trigger 760, the number 0UT& /0UT, and produces the output signal D of the receiver 730. The first supply voltage V_term can be the termination voltage of the channel 720. FIG. 8 is a circuit diagram of the Schmitt trigger 760 illustrated in FIG. Referring to FIG. 8, the Schmitt trigger 760 can include a first resistor 801 and a second resistor 802. The power supply voltage VDD can be applied to the first terminals of the first resistor 801 and the second resistor 802. The second terminal of the first resistor 8〇1 can be connected to the drain of the NMOS transistor 803 and the third NMOS transistor 805 of the 122081.doc-13-200816659. The signal at the second terminal of the first resistor 801 can be changed to the second output signal /OUT of the Schmitt trigger 760. The second terminal of the second resistor 802 can be connected to the drains of the second NMOS transistor 804 and the fourth NMOS transistor 806. The signal at the second terminal of the second resistor 802 can be changed to the first output signal OUT of the Schmitt trigger 760'. - The sources of the first NMOS transistor 803 and the second NMOS transistor 804 are connectable to the first flip-flop voltage controller 810. The first flip-flop voltage control buffer 8 10 can include a plurality of current sources 8 11 to 8 15 connected to the sources of the first NMOS transistor 803 and the second NMOS transistor 804, and are respectively connected to the plurality of current sources. A plurality of NMOS transistors 821 to 825 of 811 to 815. The gates of the NMOS transistors 821 to 825 can respectively receive the second control signal Υ[η:0]. The gate of the third NMOS transistor 805 can be connected to the first output signal OUT of the Schmitt trigger 760, and the gate of the fourth NMOS transistor 806 can be connected to the second output signal of the Schmitt trigger 760 / OUT. The third NMOS transistor 805 and the fourth NMOS transistor 806 can latch the output signal C of the high pass filter 740 illustrated in FIG. The sources of the third NMOS transistor 805 and the fourth NMOS transistor 806 are connectable to the second flip-flop voltage controller 830. The second flip-flop voltage controller 830 can include a plurality of current sources 831, 832, and 833 connected to the sources of the third NMOS transistor 805 and the fourth NMOS transistor 806, and connected to the plurality of current sources 831, 832, respectively. And a plurality of NMOS transistors 841, 842 and 843 of 833. The gates of NMOS transistors 841, 842, and 843 can receive the first control signal X[m:0], respectively. 122081.doc -14- 200816659 Figure 9 illustrates the operation of the Schmitt trigger 760. Referring to FIG. 9, as the number of signals at the logic high level in the _th control signal X[m: 〇] and the second control signal γ[η: 〇] increases, the first flip-flop voltage Vth - 〇 and the second The flip-flop voltage Vth-1 can be shifted to a high level. x Fig. 1A is an example timing diagram for explaining the operation of the receiver 73A illustrated in Fig. 7. Referring to Figure 10, the signal A output from the transmitter 71 is changeable to pass through the channel 720 and can pass through the high pass filter 74 and become the signal c. The first flip-flop voltage 一0 and the second flip-flop voltage v讣” can control whether the high-pass filter 740 has a logic low level or a logic high level, and the output signal C can be output as the output signal 接收 of the receiver 730. Figures 11A and 11B illustrate an example ''eye'" of the signal b through the channel 72 illustrated in Figure 7 and the output signal D of the receiver 730 illustrated in Figure 7. 11A and 11B show that there may be less jitter noise in the eye of the output signal 接收 of the receiver 73〇 compared to the eye of the output signal C0 of the conventional receiver 130 illustrated in the figure (FIG. 11B). Explained). Figure 12 illustrates an example frequency response characteristic of receiver 730 illustrated in Figure 7. Referring to Figure 12, to receive a signal b modulated at a particular frequency, the signal gain of the receiver 730 is varied by the high pass filter 74 of the receiver 730, and the Schmitt trigger 760 can be first controlled by the signal x[m: And the second control signal Υ[η:0] control to compensate for the signal gain loss depending on the characteristics of the data transmission channel. FIG. 13 illustrates an example receiver 1330 of differential signaling type in accordance with an example embodiment. Referring to Figure 13, the first differential signal a and the second differential signal /A output from the transmitter 1310 can be transmitted to the receiver 133A via the channel pair 1320. The receiver 130 can include: a high pass filter 1340 that receives the first differential signal b and the second differential signal /B through the channel pair 1320; - a controller 1350 that produces a first control a signal x[m:0] and a second control signal Υ[η:0]; and a Schmitt trigger 136〇 responsive to the first control signal X[m:0] and the second control signal γ[η :0] The output signals C and /C of the high pass filter 134 are compared with the first supply voltage V-term and the output signals - 〇υτ and /〇υτ are generated. The output signals OUT and /OUT of the Schmitt trigger 1360 can be output as the output signal D of the receiver 1330 via the amplifier 1370. The high pass filter 1340 can include a first capacitor 1341 having a first terminal that receives a first differential signal B through one of the channel pairs 1320; a first resistor 1342 coupled to the first capacitor a second terminal of 1341 and a source of a first power supply voltage V_term; a second capacitor 1343 having a first terminal receiving a second differential signal /B through the other of the pair of channels 13 20; A second resistor 1344 is coupled to the second terminal of the second capacitor 1343 and a source of the first supply voltage v_term. The Schmitt trigger 1360 can be similar to the Schmitt trigger 760 illustrated in FIG. However, the output signal C of the first capacitor 1341 of the high pass filter 1340 can be connected to the gate of the first-NM0S transistor 803 of the Schmitt trigger 760 illustrated in FIG. 8, and the high pass chopper 1340 The output signal /C of the two capacitor 1343 can be coupled to the gate of the second NMOS transistor 804 of the Schmitt trigger 760 illustrated in FIG. To receive the differential signals B and /B transmitted through the channel pair 1320 in a differential signaling mode, the high pass filter 1340 and the Schmitt trigger 1360 can be at the first control signal X[m:0] and the second control signal Y. The signal gain of the receiver 122081.doc -16 - 200816659 1330 is changed under the control of [n:〇]. Therefore, the signal gain loss of the apparent channel pair 132〇 can be compensated for. Having thus described the example embodiments, it will be apparent that the example embodiments can be varied in many ways. Such variations are not to be interpreted as a departure from the spirit and scope of the example embodiments, and all such modifications are intended to be included in the scope of the following claims. . BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example circuit of a conventional data transmission channel. 2A, 2B and 2C illustrate example waveforms of signals transmitted through the data transmission channel illustrated in FIG. Figure 3 illustrates an example eye characteristic of the output signal of the amplifier illustrated in Figure 1. Figure 4 illustrates an example conventional signal shaper circuit. Figure 5 illustrates an example frequency response characteristic of the signal shaper circuit illustrated in Figure 4. U Figure 6 illustrates an example signal gain loss based on specific channel characteristics. FIG. 7 illustrates an example receiver in accordance with an example embodiment. FIG. 8 is an example circuit diagram of the Schmitt trigger illustrated in FIG. 7. Fig. 9 is a view showing an example of the operation of the Schmitt trigger illustrated in Fig. 7. σ Figure 10 is an example timing diagram showing the operation of the receiver illustrated in Figure 7. Figure 11A and Figure 11B show an example output signal of the receiver illustrated by the eye diagram of the channel illustrated in Figure 7 and the receiver illustrated in Figure 7. Figure 12 illustrates an example frequency response of the receiver illustrated in Figure 7. Figure 13 illustrates an example receiver of differential signaling type in accordance with an example embodiment. [Main component symbol description]

Ο 110 Transmitter 120 Channel 130 Receiver 132 Comparator 134 Amplifier 221 High Pass Filter 222 Comparator 223 Capacitor 224 Schmitt Trigger 710 Transmitter 720 Channel 730 Receiver 740 High Pass Filter 742 Capacitor 744 Resistor 750 Controller 760 Schmitt trigger 770 amplifier 801 first resistor 122081.doc • 18 - 200816659 802 second resistor 803 first NMOS transistor 804 second NMOS transistor 805 third NMOS transistor 806 fourth NMO, S transistor ^ 810 First Trigger Voltage Controller • 811, 812, 813, 814, 815 Current Sources 821, 822, 823, 824, 825 NMOS Transistor 830 Second Trigger Voltage Controller 831, 832, 833 Current Source 841 , 842 , 843 NMOS transistor 1310 transmitter 1330 example receiver 1340 high pass filter 1341 first capacitor 1342 first resistor (J 1343 second capacitor 1350 controller β 1360 Schmitt trigger 1370 amplifier A signal / gain stage /A signal B signal / gain stage / B signal 122081.doc -19- 200816659 c /c

CO

D

IN

OUT

. /OUT

VDD ζ ) V—term

Vth_0 Vth_l X[m:0] Y[n:0]

U signal signal output signal output signal input signal output signal output signal power supply voltage first power supply voltage first trigger voltage second trigger voltage first control signal second control signal 122081.doc -20-

Claims (1)

200816659 X. Patent application scope: l A receiver for reducing the gain loss of at least the data transmission channel, comprising: a high-pass filter for interference and compensation signals; and a Schmitt trigger, which is composed of a plurality of first Two control signal control. The system 仏 及 及 及 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Trigger voltage. 3. The receiver of claim 2, the first input signal of the first channel is passed through the bean; and the first through the m-waveper is configured to receive the Schmitt trigger configured in response to The plurality of first control sounds: and _ second control signals will come from one of the high pass filters, second words: compared with: the first power supply voltage, and generate a first output 仏 ah and a second output signal . 4. The receiver of claim 3, further comprising: - a controller configured to generate the plurality of first control signals and the plurality of second control signals; and an amplifier configured to Receiving the first __ output signal and the second output signal, and generating an output signal of the receiver. 5. The receiver of claim 4, wherein the Schmitt trigger comprises: a first resistor and a second resistor having a second power supply applied to the first terminal; a first NM〇 An S transistor having a first die connected to the first resistor 122081.doc 200816659 to output a drain of the second output signal, and the first signal from the mushroom is applied thereto a first NMOS transistor having a drain connected to a second terminal of the second resistor to output the second output signal, and the first power voltage applied to one of the gates; a third NMOS transistor having a drain connected to the first resistor and a first output signal applied to one of the gates; 〇 a fourth NMOS a transistor having a drain connected to the second terminal of the second resistor, and the second output signal is applied to one of the gates; a first flip-flop voltage controller coupled to the first The NM〇S transistor and the source of the second NMOS transistor are connected a voltage source, and controlled by the plurality of second control signals; and a second flip-flop voltage controller connected to the third NMOS, the source of the crystal and the fourth NMOS transistor, and the ground voltage source, And being controlled by the plurality of first control signals. 6. The receiver of claim 5, wherein the first trigger voltage controller package comprises: a plurality of current sources connected to the first NMOS transistor and the second NMOS transistor And a plurality of NMOS transistors each connected to one of the plurality of current sources and the ground voltage source, the gates of each of the plurality of transistors respectively receiving the plurality of second controls 122081.doc • 2 - 200816659 in the signal. The receiver of claim 5, wherein the second trigger voltage controller comprises: a plurality of current sources 'connected to the third NMOS transistor and the sources of the fourth NMOS transistor; and a plurality of NMOS a transistor, each of which is respectively connected to one of the plurality of current sources and the ground voltage source, and the gates of each of the plurality of NM〇s transistors Ο 8· 〇 9. 10. respectively receive the gate One of a plurality of first control signals. The receiver of claim 4, wherein the high pass filter comprises: a capacitor having a first input signal applied through the first channel to one of the first terminals; and a resistor coupled to the capacitor And a second terminal and a source of the first power voltage, wherein a signal of the second terminal of the child capacitor becomes the first signal from the high-pass wave. The receiver of claim 4, wherein the first supply voltage is a termination voltage applied to the first channel. The receiver of claim 4, wherein the high pass filter is further configured to receive a second input signal through a second channel; and the sigma trigger is further configured to respond to the plurality of A control signal and the plurality of second control signals compare a second signal from the high pass filter with the first supply voltage. The receiver of claim 10, wherein the Schmitt trigger comprises: 122081.doc 200816659 a first-resistor and a second resistor having a first terminal to which a power supply voltage is applied; a first NMOS a transistor having a drain connected to a second terminal of the first resistor to output the second output signal, and a first signal from the same filter applied to one of the gates; a first NMOS transistor having a drain connected to the second resistor=a second terminal to output the first output signal, and a second signal from the Shangtong filter applied to the gate a third NMOS transistor having a drain connected to the second terminal of the first resistor, and a first output signal applied to one of the gates; a fourth NMOS transistor a drain connected to the second terminal of the second resistor, and the second output signal is applied to one of the gates; a trigger voltage controller connected to the first NMOS capacitor And the source of the first NMOS transistor and a grounding current a source, and controlled by the plurality of second control signals; and a first flip-flop voltage controller connected to the third NM〇s electrical body and the source of the fourth NMOS transistor and the ground voltage The source is controlled by the plurality of first control signals. The receiver of claim 11, wherein the first trigger voltage controller comprises: a plurality of current sources connected to the first NM〇s transistor and the sources of the second NMOS transistor And 122081.doc 200816659 a plurality of NMOS transistors each connected to one of the plurality of current sources and the ground voltage source, the gates of each of the plurality of NM〇s transistors being respectively received One of the plurality of second control signals. 13. The receiver of claim 11, wherein the second flip-flop voltage controller comprises a plurality of current sources connected to the third NMOS transistor and the sources of the fourth NMOS transistor ;and 〇稷 a plurality of NMOS transistors, each of which is respectively connected to one of the plurality of electrical sources and the ground voltage source, the gates of each of the plurality of transistors respectively receiving the plurality of first One of the control signals. 14. The receiver of claim 1, wherein the high pass filter comprises: a first capacitor having a first input signal applied through the first channel to one of the first terminals; 'connecting to a second terminal of the first capacitor and a source of the first supply voltage; a capacitor-having capacitor having a second input signal applied to the first terminal through the first channel And a second resistor H connected to the second terminal of the second capacitor and the source of the first power voltage, wherein the second terminal of the first capacitor, the signal of the first branch The first signal from the board of the board is considered to be, and the one of the second terminals of the second unit becomes the second number 122081.doc 200816659 15 from the high pass filter. The receiver of claim 1, wherein the first power voltage is a termination voltage applied to each of the at least one channel ♦. 16. A method of reducing at least _ mark interference within a data transmission channel and compensating for signal gain loss, comprising: receiving at least one input signal through a corresponding channel; responding to the at least one input signal using a high pass filter Generating a first output signal; Ο = complex = a first control signal and a plurality of second control signals for the first trigger voltage and one second trigger system of the special trigger =:: a plurality of first control signals and the plurality of second control terminals - the output signal is boosted by a first power supply; r generates a second round of φ > the electrical voltage is compared with the turn of the "number and one The third output signal is responsive to the first 贶, and the w music output signal and the one of the 15 rounds of the round signal. The output is generated by 4 〇 122081.doc