200816630 九、發明說明： 【發明所屬之技術領域】 種 *發明相關於-種時脈控制裝置與相 可降低能量消耗之時脈_裝置與相法。s 【先前技術】 随著科技的發展，可攜帶式資訊產品已經變成許多商 務人士或-般民眾的必備用品，例如行動電話、個人數位 助理(Personal Digital Assistant，pDA)、筆記型電腦，或是 其匕各式可攜帶式電子裝置等。對於可攜帶式電子裝^而 言，除了各種操作上的功能需求外，使用者最重視的就是 它的連續使用時間或待機時間，因此通常會針對可攜帶$ 電子裝置設計一些省電機制，當系統進入閒置狀態達到一 預定時間後，可攜帶式電子裝置會適時地降低一些内部電 路元件的操作頻率以減少能量消耗，進而延長其連續使用 時間和待機時間。 無論是可攜帶式電子裝置或其它電腦系統，除了可藉由 改變硬體設計之省電方法外（例如使用較省電的處理器）， 亦可藉由簡易且低成本的軟體技術來達到省電目的。在先 前技術中，系統一般於一正常模式下運作，當系統閒置達 一預定時間後，此時會進入一省電模式。以電腦系統為例， 在進入省電模式後電腦系統會陸續啟動螢幕保護程式或關 200816630 閉螢幕及硬碟，以進入待命及休眠模式等省電模式，以減 少電腦系統之電力消耗。至於電腦系統之間置與否，通常 • 端視電腦系統中之鍵盤或滑鼠等資料輸出/入裝置有否於 預定時間内被使用者所按觸而定。 請參考第！圖，第丄圖為先前技術中—時脈控制方法 之流程圖。第1圖之流程圖包含下列步驟： 步驟100 :開始。 步驟110 :採用第-時脈訊號為系統時脈訊號；執行步 驟 120 〇 步驟no:麟系統是否進入省電模式：若系統進入省 電模式，執行步驟130;若系統未進入省電 模式，執行步驟110。 步驟130:採用第二時脈訊號為系統時脈訊號；執行步 驟 110。 步驟140:判斷系統是否被喚醒：若系統被喚醒，執行 步驟，右系統未被喚醒，執行步驟130。 請參考第2圖，第2圖為執行第丨圖之時脈控制方法 時之訊號圖。在第2圖中，第一時脈訊號、第二時脈訊號、 系統時脈訊號、省電訊號，以及喚醒訊號之波形分別由 sCLK1、sCLK2、sSYSTEM、sPOWER—D0WN，以及 Swake仰來表示。 • 如第2圖所示，第一時脈訊號之頻率高於第二時脈訊號^之 7 200816630 頻率。當系統在時_ T1欲進人省電模式時，此時會產生 省電« sPOWER—D0WN ;當在時間點η接收到喚醒訊號 • SwA^E二時，系統會離開省電模式。當系統在正常模式下運 作柃’系統時脈訊號8^訂而採用頻率較高之第一時脈訊號 Scua ;當系統在省電模式下運作時，先前技術會採用頻率200816630 IX. Description of the invention: [Technical field to which the invention pertains] * The invention relates to a clock-inducing device and a phase-reducing energy-saving clock-device and phase method. s [Prior Art] With the development of technology, portable information products have become a must-have for many business people or ordinary people, such as mobile phones, Personal Digital Assistant (pDA), notebook computers, or There are various portable electronic devices and the like. For the portable electronic device, in addition to various operational functional requirements, the user pays most attention to its continuous use time or standby time, so usually some power saving mechanism is designed for the portable electronic device. After the system enters the idle state for a predetermined period of time, the portable electronic device can timely reduce the operating frequency of some internal circuit components to reduce energy consumption, thereby extending the continuous use time and standby time. Whether it is a portable electronic device or other computer system, in addition to changing the hardware design of the hardware design (for example, using a more power-efficient processor), it can also be achieved by simple and low-cost software technology. Electrical purpose. In the prior art, the system generally operates in a normal mode, and when the system is idle for a predetermined period of time, it enters a power saving mode. Taking the computer system as an example, after entering the power saving mode, the computer system will start the screen saver program or turn off the 200816630 closed screen and hard disk to enter the power-saving mode such as standby and sleep mode to reduce the power consumption of the computer system. Whether the computer system is connected or not, usually • Whether the data output/input device such as the keyboard or mouse in the computer system is touched by the user within a predetermined time. Please refer to the first! The figure is a flow chart of the prior art-clock control method. The flowchart of Figure 1 contains the following steps: Step 100: Start. Step 110: using the first-clock signal as the system clock signal; performing step 120 〇 step no: whether the system enters the power-saving mode: if the system enters the power-saving mode, step 130 is performed; if the system does not enter the power-saving mode, execute Step 110. Step 130: The second clock signal is used as the system clock signal; step 110 is performed. Step 140: Determine whether the system is woken up: If the system is woken up, execute the step, and the right system is not awake, and step 130 is performed. Please refer to Figure 2, which is a signal diagram when the clock control method of the second diagram is executed. In Figure 2, the waveforms of the first clock signal, the second clock signal, the system clock signal, the power saving signal, and the wake-up signal are represented by sCLK1, sCLK2, sSYSTEM, sPOWER_D0WN, and Swake, respectively. • As shown in Figure 2, the frequency of the first clock signal is higher than the frequency of the second clock signal ^ 7 200816630. When the system is in time _ T1 wants to enter the power saving mode, the power saving « sPOWER — D0WN will be generated at this time; when the wake-up signal is received at the time point η • SwA ^ E 2, the system will leave the power saving mode. When the system is operating in the normal mode, the system clock signal is set to use the first clock signal Scua with a higher frequency; when the system is operating in the power saving mode, the prior art uses the frequency.
Ssystem ; 田接收到喚醒訊號sWAKEUI^^，系統會離開省電模式而重 新在正^模式下運作，此時先前技術會再度採用頻率較高 之第一時脈訊號SCLK1來作為系統時脈訊號Ssystem。 在先前技術中’當系統在省電模式下運作時，會採用 頻率較低之時脈訊號來作為系統時脈訊號 ，因此可達到省 電的效果，然而頻率較低之時脈訊號仍會消耗系統的能量。 【發明内容】 本發明提供一種可控制一系統在正常/省電模式下運作 之時脈控制裝置，其包含一微處理器，其係依據一系統時 脈來運作，並用來輸出一省電訊號；一閘控時脈裝置，用 來依據一時脈訊號和一延遲致能訊號來輸出該系統時脈； 一第一延遲裝置，用來依據該省電訊號和該時脈訊號來輸 出一除能訊號；一第二延遲震置，用來依據該省電訊號、 該時脈訊號和一喚醒致能訊號來輸出該延遲致能訊號；一 時脈產生裝置，用來依據該除能訊號或該喚醒致能訊號來 200816630 輸出^中斷輸出該時脈訊號；以及-唤醒裝置，用來依據 -喚醒訊號來輪出該_致能訊號。 本發明另提供—㈣脈控財法，其包含 號來輸出—系統於—正常模式下運作時所需之-系統時rr °扎號，在該糸統欲進入一省電模式時輸出-省電訊號；在 接收到該省電訊號後關_時脈訊號以停止輸出該系統時 脈訊號；在該系較從該省電模式進人紅倾式時輸出 一喚醒致能簡；在接收到該切致能訊號後恢復輸出該 時脈訊號；以及在恢復輸_時脈訊號達-預定時間後依 據該時脈訊號來輪出該系統時脈訊號。 【實施方式】 請參考第3圖，第3圖之功能方塊圖說明了本發明中控 制系統運作之一時脈控制裝置30。時脈控制裝置3〇包含 一微處理器31、一閘控時脈(Gatedcl〇ck)元件32、一第一 延遲單元33、一第二延遲單元34、一時脈產生單元35、 一喚醒單元36、一中斷單元37，以及一即時計時器喚醒信 號產生器（Real-time Clock Generator，RTC)38。微處理器 31依據一系統時脈訊號Ssystem來運作，當系統欲進入省 電模式時’微處理器3 1會產生一省電訊號Sp〇WER_DOWN ’ 並將省電訊5虎Sp〇wER_DOWN傳至第一延遲单元33和第^一延 遲單元34。閘控時脈元件32可依據一時脈訊號Sclock和 9 200816630 延遲致能§fL號SDEALY_ENABLE來產生系統時脈訊號 Ssystem，並將系統時脈訊號Ssystem傳至微處理器31和中 斷單元37。第一延遲裝置33耦接於微處理器31和時脈產 生單元35,可依據省電訊號SP0WER_D0WN和時脈訊號sCLOCK 來產生一除能訊號Sdisable，並將除能訊號sDISABLE傳至時 脈產生單元35。第二延遲裝置34耦接於微處理器31、閘 控時脈元件32、、喚醒單元36、和時脈產生單元35，可 依據省電訊號sPOWER—down、喚醒致能訊號swakeup enable 和時脈訊號SCL0CK來產生延遲致能訊號sdealy_enable，並 將延遲致能訊號SDEALY-ENABLE傳至閘控時脈元件32。喚醒 早元3 6可依據一外部唤醒訊號swAKeup_ext或即時計時器 喚醒信號產生器38所產生之内部喚醒訊號8佩灯1；1>_11^來 產生一唤醒致能訊號SWAKEUP_ENABLE。中斷單元37可依據 系統時脈訊號Ssystem對唤醒致能訊號sWAKEUP_ENABLE取樣 以產生一中斷訊號SDISRUPT。時脈產生單元35可依據喚醒 致能訊號S WAKEUP_ENABLE 或除能訊號SdISABLE來輸出訊號： 當接收到喚醒單元36所產生之喚醒致能訊號 SwAKEUP』NABLE 時， 時脈產生單元35會輸出時脈訊號 Sclock ;當接收到第一延遲裝置33所產生之除能訊號 Sdisable 日夺， 時脈產生單元35會中斷時脈訊號sCLOCk的輸 出。 請參考第4圖，第4圖為本發明時脈控制裝置3〇運作 200816630 時之訊號圖。第4圖顯示了時脈訊號SCLOCK、系統時脈訊 號Ssystem、省電訊號SPOWERJDOWN、延遲致能訊號 ’ SDEALY—ENABLE、外部喚醒訊號SWAKEUP_EXT/内部喚醒訊號 S WAKEUP_INT，以及中斷訊號SDISRUPT之波形。橫軸代表時間 點，時間點T1代表系統進入省電模式的時間點，而時間點 T6代表系統離開省電模式的時間點。 首先說明當系統從正常模式進入省電模式時時脈控制 裝置30的運作。假使系統在時間點τι時欲進入省電模式， 此時微處理器31會產生省電訊號Sp〇WER—D〇WN，第二延遲 單元34在接收到省電訊號§p〇wER_D〇後會輸出相對應的 延遲致此訊號SDEALY—ENABLE至閘控時脈元件32。接著，第 L遲單元33在接收到省電訊號sp〇wer d〇wn後會輸出相 對應的除能訊號Sdisable至時脈產生單元35，因此時脈產 生單元35會於時間點T2時中斷時脈訊號Scl〇ck的輸出。 由於第二延遲裝置34係依據省電訊號Sp〇wER—d_和時脈 訊號sCL0CK來產生延遲致能訊號enable，在本發明 中，第二延遲單元34之動作會早於第一延遲單元幻，如 此第二延魏置34可在時脈產生單元35停止輸出時脈訊 號SCL0CK之前產生延遲致能訊號％__四雌。由於閑控 時脈件32係依據時脈訊號&⑽來產生之系統時脈訊 號sSYSTEM ’當時間，點T2時脈訊號I·的輸出中斷時， 此時閘控時脈元件32亦從第二延遲單元34接收到相對應 11 200816630 的延遲致能訊號sDEALY ENA則，告知此時系統欲進入省電 模式，因此閘控時脈元件32會關閉系、统時脈訊號SsysTEM。 接下來說明當系統從省電模式進入正常模式時時脈控 制裝置30的運作。當系統欲離開省電模式時，需要一喚醒 訊號來重新啟動各元件的運作。喚醒訊號可為一外部喚醒 訊號SWAKEUP_EXT或由即時計時器喚醒信號產生器％所產 生的内部喚醒訊號SWAKEUP_INT。當唤醒單元36於時間點 T3收到外部喚醒訊说sWAKEUP-EXT或内部唤醒訊號 SwAKEUP—INT時，會產生相對應之喚醒致能訊號 SWAKEUP—ENABLE。在接收到喚醒致能訊號SWAKEUp εν·ε 後，時脈產生單元35會於時間點T4時開始再度輸出時脈 訊號SCL0CK至閘控時脈元件32及第二延遲單元34。在接 收到奐醒致冑b sfL號SWAKEUp_ENABLE及時脈產生單元$ 5恢復 輸出之時脈訊號Scl〇ck後，第二延遲單元34可延遲訊號 輸出，亦即在接收到時脈產生單元35傳來之時脈訊號 Sclock後，第二延遲單元34並不會立即開啟延遲致能訊號 SdEALY—ENABLE，而是等到時脈訊號SCL〇CK穩定後，才會於 日守間點T5開啟延遲致能訊號sDEALY_ENABLE。此時，閘控時 脈元件32可開始依據時脈訊號sCL0CK來輸出訊號，於時 間點T6時開始恢復輸出在正常模式下運作時所需之系統 時脈訊號Ssystem。接著，中斷單元37會於時間點T7時輸 出中斷訊號SDISRUPT至微處理器31。最後，在接收到中斷 12 200816630 訊號s DISRUPT 後， 微處理器31會於時間點T8時關閉省電 ‘ 訊號S POWER DOWN， 此時系統會完全脫離省電模式。 請參考第 5圖，第5圖為本發明之時脈控制裝置30運 作時之流程圖 。第5圖之流程圖包含下列步驟： 步驟500 : 開始。 步驟510 : 採用一時脈產生單元所產生之時脈訊號來 作為系統時脈訊號；執行步驟520。 步驟520 : 判斷系統是否進入省電模式：若系統進入省 電模式，執行步驟530 ;若系統未進入省電 模式，執行步驟510。 步驟530 : 關閉時脈產生單元；執行步驟540。 步驟540 : 判斷系統是否被喚醒：若系統被喚醒，執行 步驟550;若系統未被喚醒，執行步驟530。 步驟550 : 致能時脈產生單元；執行步驟560。 步驟560 : 在時脈產生單元之輸出穩定後，採用時脈產 生單元所產生之時脈訊號來作為系統時脈 訊號；執行步驟570。 步驟570 : 中斷喚醒系統；執行步驟580。 步驟580 : 離開省電模式。 在本發明中，當系統進入省電模式後，會於步驟530 13 200816630 中關閉時脈產生單元35以中斷時脈訊號Scl〇ck之輸出， 因此能更進一步降低能量消耗。當系統欲離開省電模式 ^ 時，本發明並不會立即恢復時脈訊號SCL0CK之輸出，而是 等到時脈產生單元35之輸出穩定後，才會採用時脈產生單 元所產生之時脈訊號SCLOCK來作為系統時脈訊號 Ssystem，再使系統完全脫離省電模式。 请參考第6圖’第6圖為本發明第一實施例中喚醒單 元36之功能方塊圖。本發明第一實施例之唤醒單元36包 含一或閘（OR Gate)62，當接收到外部喚醒訊號swAKEup ΕχτSsystem; The field receives the wake-up signal sWAKEUI^^, the system will leave the power-saving mode and operate again in the positive mode. At this time, the prior art will again use the first clock signal SCLK1 with higher frequency as the system clock signal Ssystem. . In the prior art, when the system is operating in the power saving mode, the lower frequency clock signal is used as the system clock signal, so that the power saving effect can be achieved, but the lower frequency clock signal still consumes. The energy of the system. SUMMARY OF THE INVENTION The present invention provides a clock control apparatus that can control a system to operate in a normal/power saving mode, and includes a microprocessor that operates according to a system clock and is used to output a power saving signal. a gate-controlled clock device for outputting the system clock according to a clock signal and a delay enable signal; a first delay device for outputting a power dissipation according to the power-saving signal and the clock signal a second delay, configured to output the delayed enable signal according to the power save signal, the clock signal, and a wake-up enable signal; a clock generation device configured to use the disable signal or the wake-up signal The enable signal is sent to the 200816630 output ^ interrupt to output the clock signal; and - the wake-up device is used to turn the _ enable signal according to the - wake-up signal. The invention further provides - (4) pulse control financial method, which includes the number to output - the system needs to operate in the normal mode - the system rr ° tie number, when the system wants to enter a power saving mode output - province a signal signal; after receiving the provincial power signal, the _clock signal is turned off to stop outputting the system clock signal; when the system is red-tilted from the power saving mode, a wake-up enable is output; upon receiving After the severing signal, the clock signal is resumed; and the system clock signal is rotated according to the clock signal after the __ clock signal is restored for a predetermined time. [Embodiment] Referring to Fig. 3, a functional block diagram of Fig. 3 illustrates one of the clock control devices 30 of the control system operation of the present invention. The clock control device 3 includes a microprocessor 31, a gated clock component 32, a first delay unit 33, a second delay unit 34, a clock generation unit 35, and a wake-up unit 36. An interrupt unit 37, and a real-time timer generator (RTC) 38. The microprocessor 31 operates according to a system clock signal Ssystem. When the system wants to enter the power saving mode, the microprocessor 3 1 generates a power saving signal Sp〇WER_DOWN and transmits the power saving 5 tiger SpSwER_DOWN to the first A delay unit 33 and a first delay unit 34. The gated clock component 32 can generate the system clock signal Ssystem according to a clock signal Sclock and 9 200816630 delay enable §fL number SDEALY_ENABLE, and transmit the system clock signal Ssystem to the microprocessor 31 and the interrupting unit 37. The first delay device 33 is coupled to the microprocessor 31 and the clock generating unit 35, and generates a disabling signal Sdisable according to the power saving signal SP0WER_D0WN and the clock signal sCLOCK, and transmits the disabled signal sDISABLE to the clock generating unit. 35. The second delay device 34 is coupled to the microprocessor 31, the gated clock component 32, the wake-up unit 36, and the clock generation unit 35, and can be based on the power-saving signal sPOWER-down, the wake-up enable signal swakeup enable, and the clock. The signal SCL0CK generates a delayed enable signal sdealy_enable and transmits the delayed enable signal SDEALY-ENABLE to the gated clock component 32. The wake-up early element 3 6 can generate a wake-up enable signal SWAKEUP_ENABLE according to an external wake-up signal swAKeup_ext or an internal timer wake-up signal generated by the wake-up signal generator 38 to generate a wake-up signal 1;1>_11^. The interrupting unit 37 can sample the wake-up enable signal sWAKEUP_ENABLE according to the system clock signal Ssystem to generate an interrupt signal SDISRUPT. The clock generating unit 35 can output a signal according to the wake-up enable signal S WAKEUP_ENABLE or the disable signal SdISABLE: when receiving the wake-up enable signal SwAKEUP “NABLE generated by the wake-up unit 36”, the clock generation unit 35 outputs a clock signal. Sclock; when receiving the disabling signal Sdisable generated by the first delay device 33, the clock generating unit 35 interrupts the output of the clock signal sCLOCk. Please refer to FIG. 4, which is a signal diagram of the clock control device 3 of the present invention operating at 200816630. Figure 4 shows the waveforms of the clock signal SCLOCK, the system clock signal Ssystem, the power saving signal SPOWERJDOWN, the delay enable signal 'SDEALY-ENABLE', the external wake-up signal SWAKEUP_EXT/internal wake-up signal S WAKEUP_INT, and the interrupt signal SDISRUPT. The horizontal axis represents the time point, the time point T1 represents the time point when the system enters the power saving mode, and the time point T6 represents the time point when the system leaves the power saving mode. First, the operation of the clock control device 30 when the system enters the power saving mode from the normal mode will be described. If the system wants to enter the power saving mode at the time point τι, the microprocessor 31 will generate the power saving signal Sp〇WER_D〇WN, and the second delay unit 34 will receive the power saving signal §p〇wER_D〇. The corresponding delay of the output causes this signal SDEALY_ENABLE to gate the clock element 32. Then, after receiving the power saving signal sp〇wer d〇wn, the Lth delay unit 33 outputs the corresponding disable signal Sdisable to the clock generation unit 35, so that the clock generation unit 35 is interrupted at the time point T2. The output of the pulse signal Scl〇ck. Since the second delay device 34 generates the delay enable signal enable according to the power saving signal Sp〇wER_d_ and the clock signal sCL0CK, in the present invention, the second delay unit 34 acts earlier than the first delay unit. Therefore, the second delay setting 34 can generate the delayed enable signal %__ four females before the clock generating unit 35 stops outputting the clock signal SCL0CK. Since the idle control clock component 32 is based on the system clock signal sSYSTEM generated by the clock signal & (10), when the output of the point T2 clock signal I· is interrupted, the gate clock component 32 is also The delay unit 34 receives the delay enable signal sDEALY ENA corresponding to 11 200816630, and informs that the system wants to enter the power saving mode at this time, so the gate clock component 32 turns off the system clock signal SsysTEM. Next, the operation of the clock control device 30 when the system enters the normal mode from the power saving mode will be described. When the system wants to leave the power saving mode, a wake-up signal is needed to restart the operation of each component. The wake-up signal can be an external wake-up signal SWAKEUP_EXT or an internal wake-up signal SWAKEUP_INT generated by the instant timer wake-up signal generator %. When the wake-up unit 36 receives the external wake-up message sWAKEUP-EXT or the internal wake-up signal SwAKEUP_INT at the time point T3, a corresponding wake-up enable signal SWAKEUP_ENABLE is generated. After receiving the wake-up enable signal SWAKEUp εν·ε, the clock generation unit 35 starts to output the clock signal SCL0CK to the gated clock element 32 and the second delay unit 34 again at the time point T4. After receiving the clock signal Scl〇ck of the SWAKEUp_ENABLE clock generation unit $5 to resume output, the second delay unit 34 may delay the signal output, that is, after receiving the clock generation unit 35. After the clock signal Sclock, the second delay unit 34 does not immediately turn on the delay enable signal SdEALY_ENABLE, but waits until the clock signal SCL〇CK is stable, then the delay enable signal is turned on at the day guard point T5. sDEALY_ENABLE. At this time, the gated clock component 32 can start to output a signal according to the clock signal sCL0CK, and at the time point T6, resume the output of the system clock signal Ssystem required to operate in the normal mode. Next, the interrupt unit 37 outputs the interrupt signal SDISRUPT to the microprocessor 31 at the time point T7. Finally, after receiving the interrupt 12 200816630 signal s DISRUPT, the microprocessor 31 will turn off the power saving ‘ signal S POWER DOWN at the time point T8, and the system will completely deviate from the power saving mode. Please refer to FIG. 5, which is a flow chart of the clock control device 30 of the present invention. The flowchart of Figure 5 contains the following steps: Step 500: Start. Step 510: The clock signal generated by the clock generation unit is used as the system clock signal; step 520 is performed. Step 520: Determine whether the system enters the power saving mode: if the system enters the power saving mode, step 530 is performed; if the system does not enter the power saving mode, step 510 is performed. Step 530: Turn off the clock generation unit; perform step 540. Step 540: Determine whether the system is woken up: if the system is woken up, step 550 is performed; if the system is not awake, step 530 is performed. Step 550: Enable the clock generation unit; perform step 560. Step 560: After the output of the clock generation unit is stabilized, the clock signal generated by the clock generation unit is used as the system clock signal; step 570 is performed. Step 570: Interrupt the wake-up system; perform step 580. Step 580: Leave the power saving mode. In the present invention, when the system enters the power saving mode, the clock generation unit 35 is turned off in step 530 13 200816630 to interrupt the output of the clock signal Sc1 〇 ck, thereby further reducing energy consumption. When the system wants to leave the power saving mode ^, the present invention does not immediately restore the output of the clock signal SCL0CK, but waits until the output of the clock generating unit 35 is stable, and then uses the clock signal generated by the clock generating unit. SCLOCK is used as the system clock signal Ssystem, and then the system is completely out of the power saving mode. Please refer to Fig. 6', which is a functional block diagram of the wake-up unit 36 in the first embodiment of the present invention. The wake-up unit 36 of the first embodiment of the present invention includes an OR gate 62 when receiving an external wake-up signal swAKEup Εχτ
或是由即時計時器喚醒信號產生器38所產生的内部喚醒 訊號S WAKEUPJNT 其中之一時，喚醒單元36可產生相對應 之致能訊號SwAKEUPJENABLE。 清參考苐7圖’弟7圖為本發明第二實施例中喚醒單 元36之功能方塊圖。本發明第二實施例之唤醒單元36包 含一或閘62和一彈跳抑制(De-bounce)電路64。彈跳抑制 電路64可接收外部喚醒成號SwAKEUP—EXT和即時計時器唤 醒信號產生器38所產生之即時計時器時脈訊號Sclk RTC， 處理外部喚醒訊號SWAKEUP-EXT以降低雜訊，並輸出處理後 之外部喚醒訊號Swakeup—EXT’至或閘62。當接收到外部唤 醒訊號S WAKEUP-ΕΧΤ或疋由即時计時器喚醒信號產生器3 8 所產生的内部唤醒訊號SwAKEUP—INT其中之一時，喚醒單元 14 200816630 36可產生相對應之致能訊號Swakeup_enable: 0 請參考第8圖，第8圖為本發明第三實施例中喚醒單 元36之功能方塊圖。本發明第三實施例之喚醒單元36係 依據一外部喚醒訊號sWAKEUP-EXT來產生相對應之致能訊號 SwAKEUP—ENABLE，其包含一可程式密碼暫存器組81、一移位 暫存器組82，和一比較器83。假設系統耦接於一協同處理 器（Coprocessor)85、一串列介面控制器84，及複數個串列 介面（Serial Interface)裝置86(第8圖僅顯示兩個串列介面 裝置），協同處理器85可透過串列介面控制器84和複數個 串列介面裝置86溝通。在正常模式下，晶片8〇為主裝置 (Master)而協同處理器85為副裝置（Slave)，晶片80之喚醒 單元36可透過串列介面控制器84來控制複數個串列介面 裝置86之運作。當欲進行喚醒程序以離開省電模式時，協 同處理器85為主裝置而晶片80為副裝置，此時會透過一 串列介面輸出外部唤醒訊號Swakeup—ext至喚醒單元3 6，此 串列介面可為I2C(Inter-Integrated Circuit)介面，其可透過 一串列資料(Serial Data，SDA)匯流排和一串列時脈(Serial Clock，SCL)匯流排來傳遞外部喚醒訊號SwAKEup找了。串 列介面控制器84可和喚醒單元36整合為單一晶片8〇。可 程式密碼暫存器組81内存有相關於每一串列介面裝置86 之裝置識別碼(Device ID)，移位暫存器組82在接收到外部 喚醒訊號S WAKEUP_EXT後’ 會將串列資料處理以輸出至比較 15 200816630 器83，比較器83則會依據可程式密碼暫存器組81内存之 資料和外部喚醒訊號S WAKEupjgxT來產生相對應之喚醒致能 成5虎 SwAKEUP—ENABLE。 本發明第一實施例之喚醒單元36不需内部時脈即可運 作，但雜訊免疫力較差。本發明第二實施例之喚醒單元36 舄要内部時脈才能運作（sCLK—RTC)，但雜訊免疫力較佳。本 發明第三實施例之喚醒單元36利用SCL匯流排來控制移 位暫存态組82，因此不需内部時脈即可運作，同時可程式 ，碼暫存器組81具有記憶功能，即使關閉系統時脈也不會 影響正常運作。本發明第三實施例係利用常用的通訊協定 來執行外部喚醒，不但不需使用内部時脈，同時亦能避免 因雜訊所造成之誤動作。 第6圖至第8圖所示之喚醒單元36僅為本發明之實施 例:並不侷限本發明之範嘴。在本發明中，當系統進入省 =模式後，會關閉時脈訊號以降低能量消耗。當系統欲離 Μ電模式時，本發明並*會立即採科脈訊號來作為系 ^時脈訊號’而是㈣時脈《之輸出穩定後，才會採用 ^脈訊號來作為系統時脈訊號，再使“完全脫離^電模 本發明不但在進人省電模式後可更進-步降低 里 且系統在模式切換後即可立即地正常運作。 200816630 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利乾圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 先前技術中一時脈控制方法之流程圖。 第3 :::仃第1圖之時脈控制方法時之訊號圖。 第二為太t明中Ί時脈控制裝置之功能方塊圖。 第7=第第中喚醒單一 第8圖為本發明第三實二:：醒，之功能方塊圖。 中吳醒單元之功能方塊圖。 【主要元件符號說明】 30 時脈控制裝置31 32閑控時脈元件33、34微處理器 時脈產生單元3: 3^料元 37中斷單元 幻、醒早几 64彈跳抑制電路81 82移位暫存器組83 85 協同處理器 ％ 38 曰本 SC】 即日谓時器喚醒信號產生器 或閘 可程式密碼暫存器組 比較器 串列介面裝置 SCL 串列時脈匯流: SDA串列資料匯流排 200816630 100-140 、 500-580 T1-T8 步驟 時間點 18When the instant timer wakes up one of the internal wake-up signals S WAKEUPJNT generated by the signal generator 38, the wake-up unit 36 can generate a corresponding enable signal SwAKEUPJENABLE. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 is a functional block diagram of a wake-up unit 36 in a second embodiment of the present invention. The wake-up unit 36 of the second embodiment of the present invention includes an OR gate 62 and a bounce suppression (De-bounce) circuit 64. The bounce suppression circuit 64 can receive the external wake-up signal SwAKEUP_EXT and the instant timer clock signal Sclk RTC generated by the instant timer wake-up signal generator 38, process the external wake-up signal SWAKEUP-EXT to reduce the noise, and output the processed The external wake-up signal is Swakeup-EXT' to or gate 62. When receiving the external wake-up signal S WAKEUP-ΕΧΤ or one of the internal wake-up signals SwAKEUP-INT generated by the instant timer wake-up signal generator 38, the wake-up unit 14 200816630 36 can generate a corresponding enable signal Sakeup_enable Please refer to FIG. 8. FIG. 8 is a functional block diagram of the awake unit 36 in the third embodiment of the present invention. The wake-up unit 36 of the third embodiment of the present invention generates a corresponding enable signal SwAKEUP_ENABLE according to an external wake-up signal sWAKEUP-EXT, which includes a programmable password register group 81 and a shift register group. 82, and a comparator 83. It is assumed that the system is coupled to a coprocessor 85, a serial interface controller 84, and a plurality of serial interface devices 86 (Fig. 8 shows only two serial interface devices), and cooperative processing The device 85 can communicate with the plurality of serial interface devices 86 via the serial interface controller 84. In the normal mode, the chip 8 is the master and the coprocessor 85 is the slave. The wake-up unit 36 of the chip 80 can control the plurality of serial interface devices 86 through the serial interface controller 84. Operation. When the wake-up procedure is to be performed to leave the power-saving mode, the coprocessor 85 is the master device and the chip 80 is the slave device. At this time, the external wake-up signal Swakeup_ext is output to the wake-up unit 3 through a serial interface. The interface can be an Inter-Integrated Circuit (I2C) interface, which can be used to transmit an external wake-up signal SwAKEup through a Serial Data (SDA) bus and a Serial Clock (SCL) bus. The serial interface controller 84 can be integrated with the wake-up unit 36 into a single chip. The programmable password register group 81 has a device identification code (Device ID) associated with each serial interface device 86. After receiving the external wake-up signal S WAKEUP_EXT, the shift register group 82 will list the data. Processing is output to the comparison 15 200816630 device 83, and the comparator 83 generates a corresponding wake-up enablement according to the data in the memory of the programmable password register group 81 and the external wake-up signal S WAKEupjgxT into 5 tigers SwAKEUP-ENABLE. The awake unit 36 of the first embodiment of the present invention can operate without an internal clock, but the noise immunity is poor. The wake-up unit 36 of the second embodiment of the present invention requires an internal clock to operate (sCLK-RTC), but the noise immunity is better. The waking unit 36 of the third embodiment of the present invention controls the shift temporary state group 82 by using the SCL bus bar, so that the internal clock can be operated without being required, and at the same time, the code register group 81 has a memory function even if it is turned off. The system clock will also not affect normal operation. The third embodiment of the present invention utilizes a common communication protocol to perform external wake-up, which not only does not require the use of internal clocks, but also avoids malfunctions caused by noise. The wake-up unit 36 shown in Figures 6 through 8 is merely an embodiment of the present invention: it is not limited to the scope of the present invention. In the present invention, when the system enters the province = mode, the clock signal is turned off to reduce energy consumption. When the system wants to leave the power-on mode, the present invention will immediately use the pulse signal as the system clock signal 'but (4) the clock "the output is stable, then the pulse signal is used as the system clock signal. Therefore, the invention can be completely removed from the electric mode. The invention can be operated in a step-by-step manner after the power saving mode is entered, and the system can operate normally immediately after the mode switching. 200816630 The above is only the preferred embodiment of the present invention. For the embodiments, the equivalent changes and modifications made by the patent application according to the present invention are all within the scope of the present invention. [Simplified Schematic] Flow chart of a clock control method in the prior art.信号 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图:Wake up, the function block diagram. The function block diagram of the Zhongwu wake-up unit. [Main component symbol description] 30 clock control device 31 32 idle clock components 33, 34 microprocessor clock generation unit 3: 3 Yuan 37 interrupt unit phantom, wake up early 64 bounce suppression 81 82 Shift register group 83 85 Coprocessor % 38 SC本 SC] Instant timer wake-up signal generator or gate programmable password register group comparator serial interface device SCL serial clock convergence: SDA Serial data bus 200816630 100-140, 500-580 T1-T8 Step time point 18