200815970 九、發明說明： 【發明所屬之技術領域】 本發明係指一種NAND快閃記憶體裝置儲存與啟動程序技術。 此裝置運用了兩階段重置(Reset)訊號的傳遞，達到利用齡腸快 閃、體開機的目的。同時提供内建固態磁碟機的功能，可以大 大地增加嵌入式系統(Embedded System)的完整性，並節省系統成 本0 【先前技術】 目鈾快閃έ己憶體在運用上可分成反或閘快閃記憶體（N0R Flash)及反及閘快閃記憶體（NAND Flash)。其中N〇R快閃記憶 體一般又稱之Code F1 ash ’由於NOR F1 ash是屬於線性定址(L丨nea; addressing)的非揮發性記憶體，微處理器可以直接執行記憶體中 程式^，不需先將程式碼讀到系統記憶體中，使用相當容^，所 以目前市面上大部分的嵌入式系統以N〇R Flash作為開機的媒 =，但是相對之下N0R比NAND快閃記憶體其密度不高且價格昂 貴，所以無法很經濟地利用nor來儲存大量的使用者資料。、NMD 一般稱之為Data Flash，其特點則能提供較高的單位密度，並達 到高儲存密度與經濟實惠的目的，且_)的讀寫速度也相當的快 速。由於NAND快閃記憶體的單元大小遠小於隨，且 的^程更為簡單，因此成本相對的也較低。另外就容量而言，以 i則Γ^ΐβΜΝΙ)『Μ的容量都已經達到1-4G位元組的高容 來更疋不斷的向上提升。目前所有的隨身裝置產品中，以 快閃記憶體的佔有率最大。由此可以看出苴 有 力。但是其_D _己憶體類似於硬碟是屬於區^止 输瞧快敝鍾揭⑽讀職機存取 市：：:由,處理器執行。此部分的處裡不是狠容易， S 糸統的儲存媒介還是以膽快閃記憶體為 Ν〇ί快閃記f體需求’我們希望以麵快閃記憶體取代 6 200815970 【發明内容】 發明人發現先前的問題後，多方的蒐集資料，並藉著在此領 域多年上的研究，經過多次的測試以及實驗，故發明了此種快閃 體裝置與其啟動處理的技術架構。200815970 IX. Description of the Invention: [Technical Field] The present invention relates to a NAND flash memory device storage and startup program technology. This device uses the transmission of a two-stage reset signal to achieve the purpose of using the intestines to flash quickly and body. At the same time, the function of the built-in solid-state disk drive can greatly increase the integrity of the embedded system and save the system cost. [Prior Art] Gate flash memory (N0R Flash) and anti-gate flash memory (NAND Flash). The N〇R flash memory is also commonly called Code F1 ash 'Because NOR F1 ash is a non-volatile memory belonging to linear addressing (L丨nea; addressing), the microprocessor can directly execute the program in the memory ^, It is not necessary to first read the code into the system memory, so it is quite suitable. Therefore, most embedded systems on the market use N〇R Flash as the boot media=, but N0R is more than NAND flash memory. Its density is not high and expensive, so it is not economical to use nor to store a large amount of user data. NMD is generally called Data Flash. Its characteristics provide high unit density, high storage density and economical efficiency, and _) read and write speed is also quite fast. Since the cell size of the NAND flash memory is much smaller than that of the NAND flash memory, the cost is relatively simple, so the cost is relatively low. In addition, in terms of capacity, the capacity of i is Γ^ΐβΜΝΙ), and the capacity of Μ has reached the high capacity of 1-4G bytes. Among all current portable devices, the market share of flash memory is the largest. This shows that 苴 is powerful. However, its _D_remembering body is similar to the hard disk which belongs to the area ^ 瞧 瞧 瞧 ( (10) Reader access City::: by, the processor executes. This part of the place is not easy, S 糸 的 的 的 还是 还是 胆 胆 胆 Ν〇 Ν〇 快 快 快 快 快 快 快 快 快 快 需求 需求 体 体 体 体 体 体 体 体 体 ' 体 体 ' ' ' ' ' ' ' ' ' 2008 2008 2008 2008 2008 After the previous problems, the multi-party collected data, and through many years of research in this field, after many tests and experiments, invented the technical architecture of this flash device and its startup processing.
此發明係利用NAND快閃記憶體取代N0R快閃記憶體，其架構 士第一圖所示，可以利用NAND快閃記憶體，同時具備有開^以及 >料儲存的功月b。糸統使用兩階段重置啟動的方式，第一階段的 重置啟動訊號(170)由外部(使用者)產生，當_D快閃記憶體控 制器完成一些開機所需要的程式載入到SRAM(15〇)，便會產^第: 階段重置啟動訊號（180)，通知CPU執行SRAM中的程^，完成二 個簡單的開機動作。 本發，的使用可以應用在任何需要具有資料儲存功能的系統 上，降低系統的成本，提供更高的儲存容量。並且可以使用在各 種不同的NAND快閃記憶體，當某一薇家ΝΑΝΙ)快閃 是有瑕鱗，可以迅速的用另外—家的画㈣記憶 在生產管理與γ幾乎不會有任何改變。此架構切家 不同的微處理g，只要將SRAM的位㈣對制微處的開機位 址即可，可以選擇任何的微處理器。 閃記憶體控制器（11G)、DMA控制器⑽）以及麵( 顆1C’降低成本’而且也不會影響系統嶋 【實施方式】 並加面的目的和功效，本發明的方法以及流程利用緣圖 態却十發明利用微處理（Micro Controller)靜 _D)F1動機存取記紐（_)、_快閃記憶 步驟如圖三_ ’當外部4置滅啟動時，猶會傳送到快 7 200815970 閃記憶體控制器上的重置啟動腳位（170)，快閃記憶體控制器收到 訊號後，内部的控制邏輯會讀取第一個磁區的資訊讀出此耿_快 閃記憶體的壞執資訊，以及開機程序的區塊大小。得到這些資^ 之後，快閃記憶體控制器便會將NANDFlash上的開機程序载入^ SRAM( 150)中，然後 NAND Flash Controller 便會發出一個 Reset 訊號給 Micro Control ler( 100)，Micro Contn>l ler 便會勃轩 ςρam 中的程式碼，完成開機的基本流程。 讀取資料的過程如圖五所示，首先得到此NAND Flash所有壞 區塊的資訊以及開機程序的起始的區塊和長度，然後由起始區^ 逐在下頃取。當頃取的區塊是壞區塊時’便跳過此區塊，反之， 若是好區塊，便會讀取此區塊的開機程式到SRAM中。重複以上的 讀取動作，直到已讀取區塊的長度等於程式區塊的長度為止。 在一般資料儲存的部分，由於MND Flash的儲存方式是以一 個區塊（Block)為主要的儲存單元，因此當長期讀寫同一位置區 塊時，則不可避免的會遇到區塊因長時間的讀寫造成的損壞、^ 料錯亂的問題或是無法保證寫入資料的正確性等缺點，故本發明 在此裝置中，於啟動程式碼的NAND中加入了自動錯誤修正碼 (Error Correction Code ; ECC)和電氣抹平（Wear 收 理論等技術。透過Wear leveling麟可以使得倾的抹除可以 平均分佈在_ Flash的每個區塊，並不會侷限在某些内， =成區域性的損，的現象。所以主要加人上述的兩項技術目的 疋為了要延長使用昜命、提升快閃記憶體的可靠度。 【圖式簡單說明】 第一圖：快閃記憶體基本裝置圖。 第二圖：單一 1C示意圖。 第三圖：控制器啟動流程圖。 弟四圖·· NAND快閃記憶體内部資料配置。 第五圖：讀取開機程式碼的流程'。 200815970 【主要元件符號說明】 200:系統位址線。微處理器内部匯流排位址線。 210:系統資料線。微處理器内部匯流排資料線。如果是8位元 的微處理器，則此資料線將會有8條。 220 ·快閃記憶體控制線。控制快閃記憶體的訊號，如 CLE(Command Latch Enable) - ALE(Address Latch Enable) 以及 R/B(Ready/Busy)等等。 230:快閃記憶體資料線。dma控制器透過此資料線讀取或是寫 入資料到NAND快閃記憶體。 ' • 十、申請專利範圍： 1·本發明提供外部工具程式、可規劃開機程式及固態磁碟區的 大小。 2·本發明以NAND取代NOR與NAND的功能，並以其内建驅動程 式實體來模擬磁碟機，運用於嵌入式系統(Embedded System)。 3·本發明於NAND Flash内運用自動修正錯誤碼（Error Correction Code ; ECC)、電氣抹平（Wear leveling)和驅 動程式（Device driver)的功能，可使嵌入式系統具有高可 靠度。 4·本發明是以s〇C型態的CPU不須透過Internal ROM，即可提 供開機功能。 5·如圖一所示，嵌入式系統架構以及啟動程序。 6·如同專利範圍第1 -5項所述，此嵌入式系統利用快閃記憶體 儲存及啟動處理技術，適用於任何使用快閃記憶體的記憶裝 置，例如：隨身碟（USB Pendrive 1.1 /2· 0 )、PMP Player、 Slid State Disk、記憶卡和 MP3 Player 等。 9The invention replaces the N0R flash memory with NAND flash memory, and the architecture of the first figure shows that the NAND flash memory can be utilized, and the power month b with the opening and the storage of the material is provided. The system uses a two-stage reset start mode. The first stage reset start signal (170) is generated by the external (user). When the _D flash memory controller completes some of the programs required for booting, it is loaded into the SRAM. (15〇), it will produce ^: The stage resets the start signal (180), notifies the CPU to execute the process in the SRAM, and completes two simple boot actions. The use of this, can be applied to any system that needs to have data storage function, reducing the cost of the system and providing higher storage capacity. And can be used in a variety of different NAND flash memory, when a certain Weijia ΝΑΝΙ) flash is a scale, you can quickly use another - home painting (four) memory in production management and gamma will hardly change. This architecture is different from the micro-processing g. As long as the SRAM bit (four) is used to make the boot address of the micro-location, any microprocessor can be selected. The flash memory controller (11G), the DMA controller (10), and the surface (the 1C' reduces the cost) and does not affect the system 嶋 [embodiment] and the purpose and function of the surface, the method and the process of the present invention Figure 10 shows the use of micro-processor (Micro Controller) static _D) F1 motivation access note (_), _ flash memory step as shown in Figure 3 _ 'When external 4 is off, it will still be transferred to fast 7 200815970 The reset enable pin (170) on the flash memory controller, after the flash memory controller receives the signal, the internal control logic reads the information of the first magnetic zone to read the 耿_flash memory. The bad information of the body, as well as the block size of the boot program. After obtaining these resources, the flash memory controller will load the boot program on the NANDFlash into the SRAM (150), and then the NAND Flash Controller will send a Reset signal to the Micro Controller (100), Micro Contn> l ler will be the code in the ς ς ς am ram, complete the basic process of booting. The process of reading the data is shown in Figure 5. First, the information of all the bad blocks of the NAND Flash and the starting block and length of the boot process are obtained, and then the starting area ^ is taken down. When the block that is taken is a bad block, the block is skipped. Otherwise, if it is a good block, the boot program of the block is read into the SRAM. Repeat the above read operation until the length of the read block is equal to the length of the program block. In the general data storage part, since the storage mode of MND Flash is based on a block (Block) as the main storage unit, when the same location block is read and written for a long time, it is inevitable that the block will be encountered for a long time. In the device, the automatic error correction code (Error Correction Code) is added to the NAND of the startup code. ; ECC) and electrical smoothing (Wear theory and other techniques. Through Wear leveling Lin can make the dump erase can be evenly distributed in each block of _ Flash, and will not be limited to some, = regional The phenomenon of damage, so mainly add the above two technical purposes in order to extend the use of life and improve the reliability of flash memory. [Simplified diagram] The first picture: the basic device diagram of flash memory. The second picture: a single 1C schematic diagram. The third picture: the controller startup flow chart. The fourth picture · NAND flash memory internal data configuration. The fifth picture: the process of reading the boot code '. 20081 5970 [Main component symbol description] 200: System address line. Microprocessor internal bus address line. 210: System data line. Microprocessor internal bus data line. If it is an 8-bit microprocessor, This data line will have 8. 220 · Flash memory control line. Control flash memory signals, such as CLE (Command Latch Enable) - ALE (Address Latch Enable) and R / B (Ready / Busy) Etc. 230: Flash memory data line. The dma controller reads or writes data to the NAND flash memory through this data line. ' • X. Patent application scope: 1. The present invention provides an external tool program. Plan the boot program and the size of the solid state disk area. 2. The present invention replaces the functions of NOR and NAND with NAND, and emulates the disk drive with its built-in driver entity for use in an embedded system (Embedded System). The invention utilizes the functions of Automatic Correction Code (ECC), Wear Leveling and Device Driver in NAND Flash to make the embedded system have high reliability. Is s〇C type The CPU of the state does not need to pass through the Internal ROM to provide the boot function. 5. As shown in Figure 1, the embedded system architecture and the boot program. 6. As described in items 1 - 5 of the patent scope, this embedded system utilizes fast Flash memory storage and boot processing technology for any memory device using flash memory, such as: USB flash drive (USB Pendrive 1.1 /2· 0), PMP Player, Slid State Disk, memory card and MP3 Player. 9