doc/006 200814296 九、發明說明： 【發明所屬之技術領域】 _發明是有關於一種靜態隨機存取記憶體，且特別是 有關於一種雙埠靜態隨機存取記憶體之記憶胞。 【先前技術】 大部分的數位電子產品内部都配置型態不一之記憶 體。以電腦而言，其内部所配置之隨機存取記憶體之製造 成本將影響電腦的售價。圖丨是說明傳統雙埠靜態隨機存 取記憶體之記憶胞電路圖。請參照圖丨，p型電晶體τη 與N電晶體T12串接於電源電壓Vcc與接地電壓Vss之間 而構成第一反閘。P型電晶體T14與汉型電晶體丁13亦串 接於電源電壓Vcc與接地電壓Vss之間而構成第二反閘。 此第一反閘與第二反閘交互串接而組成資料閂鎖單元。 士於§己憶胞ι〇〇中，當要對資料閂鎖單元寫入位元資料 日守’即可經由字線WLA之控制而使N型電晶體T15與T18 導通，接著將位元資料與互補位元資料分別經由位元線 BLA、電晶體T15以及互補位元線BLAB、電晶體T18而 寫入資料閂鎖單元中。另外，亦可經由字線WLB之控制 而使^型電晶體T16與T17導通，然後將位元資料與互補 位兀資料分別經由位元線BLB、電晶體T16以及互補位元 線BLBB、電晶體Τ17而寫入資料閂鎖單元中。當要讀出 。己饭胞1〇〇之位元資料時，即可經由字線WLA之控制而 使N型電晶體T15與T18導通，接著分別經由電晶體丁15、 5 doc/006 200814296 位元線BLA以及電晶體T18、互補位元線BLAB而讀出位 元資料與互補位元資料。另外，亦可經由字線WLB之控 制而使N型電晶體T16與T17導通，然後分別經由電晶體 T16、位元線BLB以及電晶體T17、互補位元線bLBB而 讀出位元資料與互補位元資料。 一般而言，影響靜態隨機存取記憶體成本的關鍵因素 在於晶片面積。因為靜態隨機存取記憶體之每一個記憶胞Doc/006 200814296 IX. Description of the invention: [Technical field to which the invention pertains] The invention relates to a static random access memory, and more particularly to a memory cell of a double-twist static random access memory. [Prior Art] Most digital electronic products are internally configured with different types of memory. In the case of a computer, the manufacturing cost of the internal random access memory will affect the price of the computer. Figure 丨 is a circuit diagram illustrating the memory cell of a conventional double-twist static random access memory. Referring to the figure, the p-type transistor τη and the N-electrode T12 are connected in series between the power supply voltage Vcc and the ground voltage Vss to constitute a first reverse gate. The P-type transistor T14 and the Han-type transistor D13 are also connected in series between the power supply voltage Vcc and the ground voltage Vss to constitute a second reverse gate. The first reverse gate and the second reverse gate are serially connected to form a data latching unit. In the § 忆 胞 〇〇 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The complementary bit data is written into the data latch unit via the bit line BLA, the transistor T15, and the complementary bit line BLAB and the transistor T18, respectively. In addition, the transistor T16 and T17 can be turned on by the control of the word line WLB, and then the bit data and the complementary bit data are respectively passed through the bit line BLB, the transistor T16, and the complementary bit line BLBB, the transistor. Τ17 is written into the data latch unit. When you want to read out. When the bit cell data of the rice cell is 1 ,, the N-type transistor T15 and T18 can be turned on by the control of the word line WLA, and then via the transistor D5, 5 doc/006 200814296 bit line BLA and electricity respectively. The crystal T18 and the complementary bit line BLAB read the bit data and the complementary bit data. In addition, the N-type transistors T16 and T17 can also be turned on by the control of the word line WLB, and then read and complemented by the transistor T16, the bit line BLB, the transistor T17, and the complementary bit line bLBB, respectively. Bit data. In general, the key factor affecting the cost of SRAM is the die area. Because each memory cell of static random access memory
主要由電晶體所組成，例如圖丨之記憶胞1〇〇即由8個電 晶體所組成。對靜態隨機存取記憶體而言，於記憶胞中愈 多的電晶體將會佔據愈多的晶片面積，進而降低元件聚隽 度並增加其製造成本。 木 【發明内容】 胞，目的就是提供—種料靜祕機存取記憶 達到郎省晶片面積與降低成本之功效。 在敌上述及其他目的，本發明提出—種料靜態隨機 胞，包括第-字線、第二字線、第—位元線1 第五二以!二：第:開關、第三開關、第四開關、 綠甘第，、開關。第一開關之控制端輕接至第—丰 f笛Γ 端祕至第—位元線。第二開關之控制端麵接 之一予線’其第一端耦接至第二位元線。第 2 第-電壓，而；=:，第三開關之第-端耦接至 ^。弟四開關之控制端_至第二關之第二端，第t 6 200814296 ….一A.d〇c/〇Q6 二端•接至第—開關之第二端，第四開關之第二端 弟二電壓。第五開關之控制端耦接至第一開關第 二端，楚 ^ :山/弟五開關之第一端耦接至第一電壓，第五開關之第 一接至第一開關之第二端。第六開關之控制端福接至 :關^第二端，第六開關之第一端耦接至第二開關之 一端，第六開關之第二端耦接至第二電壓。 p、左她ί發明因僅以6個開關（例如電晶體）組成雙埠靜態 存取記憶胞，因此達到節省晶片面積與降低成本之功 效0 為讓本發明之上述和其他目的、特徵和優點能更明顯 ，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 二圖2疋依照本發明實施例說明一種雙璋靜態隨機存取 f憶胞之電路®。雙埠靜態隨機存取記憶胞2GG包括第-J 子線WU、第二字線WL2、第一位元線BU、第二位元 線BL2、第一開關S1、第二開關幻、第三開關％、第四 開關=4、第五開關S5以及第六開關％。在此，第一開關 =、、,第二開關S2、第四開關S4與第六開關S6*n型金 氧半(NMOS)電晶體，而第三開關S3與第五開關％是p 型金氧半(PMOS)電晶體。上述各個p型電晶體與n型電 晶體可以是各種結構及製程所稱的p型或N型電晶體，例 7 晶體與單晶矽電晶體It is mainly composed of a transistor. For example, the memory cell of the figure is composed of 8 transistors. For SRAM, the more transistors in the memory cell will occupy more wafer area, which in turn reduces component convergence and increases manufacturing costs. [Inventive content] The purpose of the cell is to provide the ability to access the memory of the seed material and to achieve the effect of the chip area and cost reduction of the Lang province. In the above mentioned and other purposes, the present invention proposes a seed static random cell, including a first word line, a second word line, a first bit line 1 and a fifth two to! Two: the first switch, the third switch, the first Four switches, green Gandi, and switches. The control end of the first switch is lightly connected to the first to the first bit line. The control terminal of the second switch is connected to the line 'the first end of which is coupled to the second bit line. The second first - voltage, and ==: the first end of the third switch is coupled to ^. The control terminal of the fourth switch _ to the second end of the second switch, the t 6 200814296 .... an Ad〇c / 〇 Q6 two end • connected to the second end of the first switch, the second end of the fourth switch Two voltages. The control end of the fifth switch is coupled to the second end of the first switch, and the first end of the fifth switch is coupled to the first voltage, and the first end of the fifth switch is connected to the second end of the first switch . The control terminal of the sixth switch is connected to: the second end, the first end of the sixth switch is coupled to one end of the second switch, and the second end of the sixth switch is coupled to the second voltage. p, left she ί invented the effect of saving wafer area and reducing cost by forming a double-turn static access memory cell with only 6 switches (for example, a transistor). The above and other objects, features and advantages of the present invention are achieved. It will be more apparent that the preferred embodiments are described below in conjunction with the drawings and are described in detail below. [Embodiment] FIG. 2 illustrates a circuit 璋 of a static random access f memory cell according to an embodiment of the present invention. The double-埠 static random access memory cell 2GG includes a -J sub-line WU, a second word line WL2, a first bit line BU, a second bit line BL2, a first switch S1, a second switch phantom, and a third switch %, fourth switch = 4, fifth switch S5, and sixth switch %. Here, the first switch =, ,, the second switch S2, the fourth switch S4 and the sixth switch S6*n type gold oxide half (NMOS) transistor, and the third switch S3 and the fifth switch % are p type gold Oxygen half (PMOS) transistor. Each of the above p-type transistors and n-type transistors may be a p-type or N-type transistor called a variety of structures and processes, and examples 7 crystals and single crystal germanium transistors.
200814296doc/006 如非晶矽薄膜電晶體、多晶矽薄膜電 等。本發明不應以此為限。 第開關si之控制端輕接至第一字、線，其第一 端輛接至第一位元線〗。楚-pq H ： S2之控制端耦接至 第一子線WL2,其第一端減至第二位元線犯。第三開 關S3之控制端_至第二開關S2之第二端。第三開關幻 之第-端祕至第-賴（例如是電源電壓Μ)，其第 二端祕至第-開關S1之第二端。第四開關S4之控制端 與第-端分別輕接至第三開關S3之控制端與第二端。第 四開關S4之第二端輕接至第二電壓（例如是接地電壓200814296doc/006 Such as amorphous germanium film transistor, polycrystalline germanium film, etc. The invention should not be limited thereto. The control end of the first switch si is lightly connected to the first word and the line, and the first end of the switch is connected to the first bit line. Chu-pq H: The control terminal of S2 is coupled to the first sub-line WL2, and the first end is reduced to the second bit line. The control terminal _ of the third switch S3 is to the second end of the second switch S2. The third switch phantom-end to the first-to-first (for example, the power supply voltage Μ), the second end of which is to the second end of the first switch S1. The control end and the first end of the fourth switch S4 are respectively connected to the control end and the second end of the third switch S3. The second end of the fourth switch S4 is lightly connected to the second voltage (for example, the ground voltage
Vss)。第五開關S5之控制端耦接至第一開關&之第二 端。第五開關S5之第-端減至第—電壓，其第二端耗 接至第二開關S2之第二端。第六開關弘之控制端與第一 端分別耦接至第五開關S5之控制端與第二端。第六開關 S6之第二端耦接至第二電壓。 請參照圖2，第三開關S3與第四開關S4串接於第一 電壓與第二電壓之間而構成第一反閘。第五開關S5與第 六開關S6亦串接於第一電壓與第二電壓之間而構成第二 反閘。第一反閘之輸出端與第二反閘之輸入端耦接至第一 開關S1之第二端。第一反閘之輸入端與第二反閘之輸出 端耦接至第二開關S2之第二端。 當要對雙埠靜態隨機存取記憶胞200寫入位元資料 時，即可經由第一字線WL1控制第一開關S1使其導通， 接著將位元資料經過第一位元線BL1、第一開關S1而傳Vss). The control end of the fifth switch S5 is coupled to the second end of the first switch & The first end of the fifth switch S5 is reduced to the first voltage, and the second end thereof is consumed to the second end of the second switch S2. The control end and the first end of the sixth switch are respectively coupled to the control end and the second end of the fifth switch S5. The second end of the sixth switch S6 is coupled to the second voltage. Referring to FIG. 2, the third switch S3 and the fourth switch S4 are connected in series between the first voltage and the second voltage to form a first reverse gate. The fifth switch S5 and the sixth switch S6 are also connected in series between the first voltage and the second voltage to form a second reverse gate. The output end of the first reverse gate and the input end of the second reverse gate are coupled to the second end of the first switch S1. The input end of the first reverse gate and the output end of the second reverse gate are coupled to the second end of the second switch S2. When the bit data is to be written to the binary random random access memory cell 200, the first switch S1 can be controlled to be turned on via the first word line WL1, and then the bit data is passed through the first bit line BL1. Passing a switch S1
Joc/006 200814296 达至弟-反閘之輸出端與第二反閘之輪人端。此位元資料 改變第-反閘與第二反閘的輸出狀態而將此位元資 料閃鎖於第一反閘與第二反閘中。另外，亦可經由第二字 二=2控制第二開關82使其導通，然後將反相位元㈣ 經過弟二位元線BL2、第二開關S2而傳送至第一反間之 輸入端與第二反閘之輸出端，進而強行改變第—反問斑第 二反閘的輸錄態㈣此反相低:轉 第二反閘中。 布 當要讀出記憶胞200之位元資料時，即可經由第 = 之控制而使第—開關S1導通，接著經由第一開關 Si二苐-位元線BL1而讀出位元資料。另外，亦可經由第 二予線脱2之控制而使第二開關S2導通，然後經由第一 開關32、第二位元線BL2而讀出反相位元資料。、由弟一 綜上所述，本發明因僅以6個開關（例如電晶 成雙埠靜態隨機存取記憶胞，因此達到節省晶片面積 低成本之功效。 、〃 υ 雖然本發明已以較佳實施例揭露如上，然其並非用以 =本發明，任何„此技藝者，在不脫縣發明之 ^圍内’當可作些許之更動與潤飾，因此本發明 耗圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1是說明傳統雙埠靜態隨機存取記憶體之記 路圖。 。^ 9 200814296:d。義 圖2是依照本發明實施例說明一種雙埠靜態隨機存取 記憶胞之電路圖。 【主要元件符號說明】 100 :傳統雙埠靜態隨機存取記憶體之記憶胞 200 ·•依照本發明實施例之雙埠靜態隨機存取記憶胞 BL1、BL2、BLA、BLAB、BLB、BLBB :位元線 S1〜S6 :開關 T11〜T18 :電晶體Joc/006 200814296 reaches the output of the brother-reverse gate and the second reverse gate. This bit data changes the output state of the first-reverse gate and the second reverse gate and flashes the bit data in the first reverse gate and the second reverse gate. In addition, the second switch 82 can be controlled to be turned on via the second word two=2, and then the reverse phase element (4) is transmitted to the input end of the first anti-interval via the second bit line BL2 and the second switch S2. The output end of the second reverse gate, and then forcibly changes the input state of the second reverse gate of the first-reverse spot (4). The reverse phase is low: the second reverse gate is turned. When the bit data of the memory cell 200 is to be read, the first switch S1 can be turned on by the control of the =, and then the bit data is read via the first switch Si 苐-bit line BL1. Alternatively, the second switch S2 may be turned on by the control of the second extension 2, and the inverted phase metadata may be read via the first switch 32 and the second bit line BL2. According to the above, the present invention achieves the effect of saving wafer area and low cost by using only six switches (for example, electro-crystal into a double-turn static random access memory cell), 〃 υ although the present invention has been The preferred embodiment discloses the above, but it is not used for the present invention, and any of the skilled artisans can make some changes and retouchings in the "inside of the invention", so the present invention is attached to the situation. The definition of the scope of the patent application shall prevail. [Simplified Schematic] Figure 1 is a diagram illustrating the traditional double-click static random access memory. ^ 9 200814296: d. Figure 2 is an illustration of an embodiment of the present invention. A circuit diagram of a double-埠 static random access memory cell. [Main component symbol description] 100: memory cell of conventional double-static static random access memory 200 • Double-click static random access memory cell BL1 according to an embodiment of the present invention , BL2, BLA, BLAB, BLB, BLBB: bit line S1~S6: switch T11~T18: transistor
Vcc :電源電壓Vcc: power supply voltage
Vss :接地電壓 WL卜 WL2、WLA、WLB :字線Vss : ground voltage WL WL2, WLA, WLB: word line