200812220 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種運异放大為’特別是關於一種低飄 移電壓（offset)運算放大恭及其降低飄移電壓的方法。 【先前技術】 在運算放大器及其在比較器電路的應用中，飄移電壓 是一個很重要的規格，尤其是在需要高解析度的應用中。 圖1顯示一傳統的折疊疊接式（foided-cascode)運算放大器 1〇〇，其中差動輸入對102包含M0S電晶體mi及M2及 偏壓電流源106，NM0S電晶體Ml及M2分別受控於輸 入電壓V-及V+而導通電流II及12，PM0S電晶體M3及 M4受控於偏壓Biasl而分別導通電流13及14，電流13被 分流為電流12及15，而電流14被分流為電流η及17，鏡 射電路104包含由NM0S電晶體Μ7、Μ8、Μ9及Μ10組 成的豐接電流鏡，用以鏡射電流15產生電流16至運算放 大裔100的輸出Vo。不管是比較器還是運算放大器，其飄 移電壓有很大一部份是來自製程飄移或電路設計不良所 造成的非理想特性，以圖1的運算放大器100為例，當電 壓V+及V-相等時，在理想狀態下，電流n等於電流12， 又電晶體M3及M4具有相同的閘源極電壓，故電流13亦 等於電流14 ’而電流15等於電流16，所以電流16應該等 於電机17,但右電路本身設計不當或元件因製程飄移造成 不匹配，將使上述情況不成立，造成電流16不等於電流 200812220 π ’這就是飄移電壓產生的原因。 為了更清楚說明飄移電壓的影響，以下用簡單的方塊 圖說明。圖2顯示一運算放大器200，其輸出Vo迴授至反 相輸入，而其非反相輸入則接地GND，在理想狀態下，運 算放大器200的輸出Vo應為0，但是，如果運算放大器 2〇〇具有飄移電壓Vos時，運算放大器200可以等效視為 一電壓源202及一理想運算放大器204，電壓源202供應 飄移電壓Vos至理想運算放大器204的輸入，使得運算放 大器200的輸出v〇不為〇而是vos，因而影響到運算放大 器200的準確度。 圖3顯示一比較器300，其反相輸入及非反相輸入分 別連接電壓V-及V+，在理想狀態下，比較器300輸出v〇 的轉態點應該是在電壓V-等於電壓V+的位置，即v+-V-=0 的位置，如圖4所示，但是，如果比較器3〇〇具有飄移電 壓Vos時，比較器300可以等效視為一可供應飄移電壓v〇s 的電壓源302連接一理想比較器304，如此一來，電壓V+ 不用大於電壓V_，只要比電壓V-低於一個飄移電壓v〇s， 比較器300的輸出Vo就會由低態Vol轉為高態Voh，如圖 5所示’反之’電壓V-不僅要大於電壓v+，還要大超過 一個飄移電壓Vos，比較器300的輸出Vo才會由高態Voh 轉為低態Vol ’因而嚴重影響到比較器3〇〇的準確度。 以往要消除飄移電壓都使用所謂的自動歸零（aut0 zeroing)技術，該技術主要是利用兩個階段中電容及開關 的作用來消除飄移電壓。圖6顯示將自動歸零技術應用在 200812220 運算放大器200時的電路架構，其中開關swi連接在運 算放大器200的輸出Vo及電容C1之間，開關SW2連接 在輸入電壓Vi及電容C1之間，開關SW3連接在運算放 大器200的非反相輸入及接地GND之間，電容ci 一端連 接在開關SW1及SW2，另一端則連接運算放大器200的 非反相輸入，其中，開關SW1及SW3受控於信號Φ1，開 關SW2受控於信號φ 2。在儲存模式時，信號φ 1控制開 關SW1及SW3導通，信號φ2控制開關SW2截止，因而 形成如圖7所示的電路，此時，電容（J1儲存飄移電壓v〇s， 接著切換至正常模式，信號φ 1控制開關SW1及SW3截 止，信號Φ2控制開關SW2導通，因而形成如圖8所示的 電路，此時，儲存在電容C1中的飄移電壓Vos將與運算 放大器200的飄移電壓v〇s互相抵消，達到消除飄移電壓 Vos的效果。 圖9顯示將自動歸零技術應用在比較器300時的電路 架構，其中，開關SW1連接在電壓V-及比較器300的反 相輸入之間，開關SW2連接在電壓V+及電容C2之間， 開關SW3連接在比較器300的反相輸入及電容C2之間， 開關SW4連接在比較器300的非反相輸入及接地GND之 間，開關SW5連接在比較器300的輸出Vo及反相輸入之 間，電容C2連接在開關SW5及比較器300的非反相輸入 之間，其中，開關SW3、SW4及SW5受控信號φ 1，開關 SW1及SW2受控信號Φ2。在儲存模式時，信號Φ 1控制 開關SW3、SW4及SW5導通，而信號Φ2控制開關SW1 200812220 及SW2截止’因而形成如圖10所示的電路， 電壓Vos將被儲存在電容C2中，接英 此日^ ’飄移 戈有，切換至正當 信號Φ 1控制開關S W3、S W4及ς , 巾嗅式， 人截止， 控制開關SW1及SW2導通，因而形成如圖u戶》唬Φ2 路，此時’儲存在電容C2中的鲰移電壓*將，的電 300的飄移電壓V〇s互相抵消，達到消除飄比較器 效果。 ^ V〇s的 應用在ic内部的電容通常有三種，即電〜 層多晶矽（doubie poiy；)電容以及金屬絕緣弟各、雙 (Metal_Insulator-Metal; MIM)電容，其中雙層多日夕^金屬 MIM電容都需要額外的光罩，而M〇s電容單^ 電容及 容值也是三種電容中最大的，換言之，M〇s電容的電 積及成本都較少，然而MOS電容在應用上一定而的面 接地或接至電源，是以，雖然自動歸零技術可以报 消除飄移電壓，但在此技術中必須使用浮接(fl〇ating)二= 容，不能使用一端接地或接至電源的M〇s電容，使得成 本無法降低。 因此，一種能使用MQS電容降低除飄移電壓的運算 放大器，乃為所冀。 【發明内容】 本發明的目的之一，在於提出一種低飄移電壓運算放 大器及其降低飄移電壓的方法。 本發明的目的之一，在於提出一種能使用M〇s電容 200812220 降低飄移電壓的運算放大器及方法。 根據本發明，一種低飄移電壓運算放大器包括一 M〇s 電容，用來儲存一飄移消減電壓，該M0S電容耦接至該 運算放大器中的電流源，使得在該運算放大器正常操作 時，該飄移消減電壓被用來調整該源電流的大小，因而降 低該運算放大器的飄移電壓。 根據本發明，一種降低運算放大器飄移電壓的方法包 括預先儲存一飄移消減電壓在一 M0S電容上，當該運算 双人器在止常操作時，將該飄移消減電壓施加至該運算敌 大器中的電流源，藉以調整該源電流的大小，因而降低該 運算放大器的飄移電壓。 在該運算放大器無負載的情況下，對其輸入一參考電 壓，以求取其失衡產生的該飄移消減電壓，並儲存至該 MOS電容上，因而使該飄移消減電壓包含該運算放大器的 飄移效應在内。 【實施方式】 圖12係本發明的第一實施例，其為一 n輸入折疊疊 接架構的運算放大器400 ,其中，PMOS電晶體M3受控 於一偏壓Biasl以導通電流13，PMOS電晶體M4則根據 電壓Vc導通電流14，開關SW5連接在pm〇S電晶體M4 的閘汲極之間，PMOS電容408連接在電源電壓VDD及 PMOS電晶體M4的閘極之間，差動輸入對402分別從電 流13及14中汲取電流12&n，鏡射電路4〇4包含由NM〇s 200812220 電晶體M7、M8、M9及MlO組成疊接電流鏡，用以鏡射 電流15產生電流16至運算放大器400的輸出v〇。在差動 輸入對402中，偏壓電流源406連接在NMOS電晶體Ml 及M2以及接地GND之間，開關sW1連接在NMOS電晶 體Ml的閘極及電壓V_之間，開關SW2連接在NMOS電 晶體Ml的閘極與電壓Vref之間，開關SW3連接在NMOS 電晶體M2的閘極與電壓Vref之間，開關SW4連接在 NMOS電晶體M2的閘極及電壓V+之間。 在儲存模式時，開關SW2、SW3及S—W5被信號φ 1 導通，開關SW1及SW4被信號Φ2截止，如圖13所示， 並使運算放大器的輸出Vo浮接，差動輸入對402中NMOS 電晶體Ml及M2的閘極連接至相同的電壓Vref，而NMOS 電晶體M4接成二極體，由於運算放大器400的輸出Vo 並未連接負載，因此電流17將被強迫等於電流16,又PMOS 電晶體M4的汲極連接至其閘極，是以，PMOS電晶體M4 閘極上的電壓Vc將自動調整以調節電流14，直至電流14 與電流II及17達到平衡。若原本的非理想特性使電流16 較理想值大，則電壓Vc將較低，而電流17也將跟著變大， 反之，若原本的非理想特性使電流16較理想值小，則電壓 Vc將較大，而電流17也將跟著變小。P]V[〇s電容408係 用以儲存電源電壓VDD與PMOS電晶體M4閘極上的電 壓Vc之間的差值(VDD_vc)，此差值是一個飄移消減電 壓。當運算放大器400操作在正常模式時，開關SW2、SW3 及SW5被信號φ 1截止，開關swi及SW4被信號φ 2導 200812220 通如圖14所不，差動輸入對402巾NMOS電晶體Ml 及M2的閘極分別連接電壓v及v+以導通電流η及12， PMOS電容408儲在的麵#、企、上&广 _。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 [Prior Art] In an operational amplifier and its application in a comparator circuit, drift voltage is an important specification, especially in applications requiring high resolution. 1 shows a conventional folded-cascode operational amplifier 1B, wherein the differential input pair 102 includes MOS transistors mi and M2 and a bias current source 106, and the NM0S transistors M1 and M2 are respectively controlled. During the input voltages V- and V+, the currents II and 12 are turned on. The PM0S transistors M3 and M4 are controlled by the bias Biasl to turn on the currents 13 and 14, respectively, and the current 13 is shunted into currents 12 and 15, and the current 14 is shunted into The currents η and 17, the mirror circuit 104 includes a condensed current mirror composed of NMOS transistors Μ7, Μ8, Μ9, and Μ10 for mirroring the current 15 to generate a current 16 to calculate the output Vo of the amplified 100. Regardless of whether it is a comparator or an operational amplifier, a large part of its drift voltage is due to non-ideal characteristics caused by process drift or poor circuit design. Take the operational amplifier 100 of Figure 1 as an example. When the voltages V+ and V- are equal. In an ideal state, the current n is equal to the current 12, and the transistors M3 and M4 have the same gate-source voltage, so the current 13 is also equal to the current 14' and the current 15 is equal to the current 16, so the current 16 should be equal to the motor 17, However, if the right circuit itself is not properly designed or the component is mismatched due to process drift, the above situation will not be established, and the current 16 is not equal to the current 200812220 π 'This is the cause of the drift voltage. In order to more clearly illustrate the effects of the drift voltage, the following is illustrated by a simple block diagram. 2 shows an operational amplifier 200 whose output Vo is fed back to the inverting input and whose non-inverting input is grounded to GND. In an ideal state, the output Vo of the operational amplifier 200 should be 0, but if the operational amplifier 2〇 When the 〇 has a drift voltage Vos, the operational amplifier 200 can be equivalently regarded as a voltage source 202 and an ideal operational amplifier 204. The voltage source 202 supplies the drift voltage Vos to the input of the ideal operational amplifier 204, so that the output of the operational amplifier 200 is not It is vos, which affects the accuracy of the operational amplifier 200. 3 shows a comparator 300 whose inverting input and non-inverting input are respectively connected to voltages V- and V+. In an ideal state, the transition point of the comparator 300 output v〇 should be at a voltage V- equal to the voltage V+. The position, that is, the position of v+-V-=0, is as shown in FIG. 4, but if the comparator 3〇〇 has the drift voltage Vos, the comparator 300 can be equivalently regarded as a voltage that can supply the drift voltage v〇s. The source 302 is connected to an ideal comparator 304. As a result, the voltage V+ is not greater than the voltage V_. As long as the specific voltage V- is lower than a drift voltage v〇s, the output Vo of the comparator 300 is changed from the low state Vol to the high state. Voh, as shown in Figure 5, the 'opposite' voltage V- is not only greater than the voltage v+, but also greater than a drift voltage Vos, the output Vo of the comparator 300 will be changed from the high state Voh to the low state Vol' thus seriously affecting Comparator 3〇〇 accuracy. In the past, the so-called auto-zeroing (aut0 zeroing) technique was used to eliminate the drift voltage. This technique mainly uses the functions of capacitors and switches in two stages to eliminate the drift voltage. 6 shows the circuit architecture when the auto-zero technique is applied to the 200812220 operational amplifier 200. The switch swi is connected between the output Vo of the operational amplifier 200 and the capacitor C1, and the switch SW2 is connected between the input voltage Vi and the capacitor C1. SW3 is connected between the non-inverting input of the operational amplifier 200 and the ground GND. One end of the capacitor ci is connected to the switches SW1 and SW2, and the other end is connected to the non-inverting input of the operational amplifier 200, wherein the switches SW1 and SW3 are controlled by the signal. Φ1, the switch SW2 is controlled by the signal φ 2. In the storage mode, the signal φ 1 controls the switches SW1 and SW3 to be turned on, and the signal φ2 controls the switch SW2 to be turned off, thereby forming a circuit as shown in FIG. 7. At this time, the capacitor (J1 stores the drift voltage v〇s, and then switches to the normal mode. The signal φ 1 controls the switches SW1 and SW3 to be turned off, and the signal Φ2 controls the switch SW2 to be turned on, thereby forming a circuit as shown in FIG. 8. At this time, the drift voltage Vos stored in the capacitor C1 and the drift voltage v of the operational amplifier 200 〇 s cancel each other out to achieve the effect of eliminating the drift voltage Vos. Figure 9 shows the circuit architecture when the auto-zero technique is applied to the comparator 300, wherein the switch SW1 is connected between the voltage V- and the inverting input of the comparator 300, The switch SW2 is connected between the voltage V+ and the capacitor C2. The switch SW3 is connected between the inverting input of the comparator 300 and the capacitor C2. The switch SW4 is connected between the non-inverting input of the comparator 300 and the ground GND, and the switch SW5 is connected. Between the output Vo of the comparator 300 and the inverting input, the capacitor C2 is connected between the switch SW5 and the non-inverting input of the comparator 300, wherein the switches SW3, SW4 and SW5 control the signal φ 1, the switches SW1 and S W2 controlled signal Φ2. In the storage mode, signal Φ 1 controls switches SW3, SW4, and SW5 to be turned on, and signal Φ2 controls switches SW1 200812220 and SW2 to turn off. Thus, a circuit as shown in FIG. 10 is formed, and voltage Vos is stored in Capacitor C2, connected to the UK this day ^ 'Floating shift has, switch to the legitimate signal Φ 1 control switch S W3, S W4 and ς, towel scent, people cut off, control switches SW1 and SW2 turn on, thus forming the figure唬 Φ2, at this time, the 'transfer voltage* stored in the capacitor C2 will cancel the drift voltage V〇s of the electric 300 to eliminate the effect of the floating comparator. ^ V〇s application of the capacitor inside the ic There are usually three types, namely, electrical ~ layer polysilicon (doubie poiy;) capacitors and metal-insulated, double (Metal_Insulator-Metal; MIM) capacitors, in which double-layer multi-day metal MIM capacitors require an additional mask, and M〇 s capacitor single ^ capacitor and capacitance is also the largest of the three types of capacitors, in other words, M 〇 s capacitors have less electricity and cost, but MOS capacitors in the application of a certain surface ground or connected to the power supply, so, although Automatic zeroing technology can report Eliminate the drift voltage, but in this technology, you must use floating 二 = , 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 One of the objects of the present invention is to provide a low drift voltage operational amplifier and a method for reducing the drift voltage. One of the objects of the present invention is to provide a method that can be used. M〇s Capacitor 200812220 Operational amplifier and method for reducing drift voltage. According to the present invention, a low drift voltage operational amplifier includes an M〇s capacitor for storing a drift subtraction voltage, the MOSS capacitor being coupled to a current source in the operational amplifier such that the shift occurs during normal operation of the operational amplifier The subtraction voltage is used to adjust the magnitude of the source current, thereby reducing the drift voltage of the operational amplifier. According to the present invention, a method for reducing an operating amplifier drift voltage includes pre-storing a drift subtraction voltage on a MOS capacitor, and applying the drift subtraction voltage to the operational enemy device when the computing doubler is operating normally. A current source is used to adjust the magnitude of the source current, thereby reducing the drift voltage of the operational amplifier. When the operational amplifier is unloaded, a reference voltage is input thereto to obtain the drift-reduction voltage generated by the imbalance, and is stored on the MOS capacitor, thereby causing the drift-reduction voltage to include the drift effect of the operational amplifier Inside. [Embodiment] FIG. 12 is a first embodiment of the present invention, which is an operational amplifier 400 of an n-input folded-stacked architecture, in which a PMOS transistor M3 is controlled by a biasing Biasl to turn on a current 13, a PMOS transistor. M4 turns on the current 14 according to the voltage Vc, the switch SW5 is connected between the gate and the drain of the pm〇S transistor M4, and the PMOS capacitor 408 is connected between the power supply voltage VDD and the gate of the PMOS transistor M4, and the differential input pair 402 Currents 12 & n are drawn from currents 13 and 14, respectively, and mirror circuit 4〇4 includes a stacked current mirror composed of NM〇s 200812220 transistors M7, M8, M9, and M10 to mirror current 15 to generate current 16 The output of operational amplifier 400 is v〇. In the differential input pair 402, the bias current source 406 is connected between the NMOS transistors M1 and M2 and the ground GND, the switch sW1 is connected between the gate of the NMOS transistor M1 and the voltage V_, and the switch SW2 is connected to the NMOS. Between the gate of the transistor M1 and the voltage Vref, the switch SW3 is connected between the gate of the NMOS transistor M2 and the voltage Vref, and the switch SW4 is connected between the gate of the NMOS transistor M2 and the voltage V+. In the storage mode, the switches SW2, SW3 and S_W5 are turned on by the signal φ 1 , and the switches SW1 and SW4 are turned off by the signal Φ 2 , as shown in FIG. 13 , and the output Vo of the operational amplifier is floated, and the differential input pair 402 The gates of the NMOS transistors M1 and M2 are connected to the same voltage Vref, and the NMOS transistor M4 is connected to the diode. Since the output Vo of the operational amplifier 400 is not connected to the load, the current 17 is forced to be equal to the current 16, and The drain of PMOS transistor M4 is connected to its gate so that the voltage Vc across the gate of PMOS transistor M4 is automatically adjusted to regulate current 14 until current 14 is balanced with currents II and 17. If the original non-ideal characteristic makes the current 16 larger than the ideal value, the voltage Vc will be lower, and the current 17 will also become larger. Conversely, if the original non-ideal characteristic makes the current 16 smaller than the ideal value, the voltage Vc will Larger, and the current 17 will also become smaller. P]V[〇s capacitor 408 is used to store the difference (VDD_vc) between the power supply voltage VDD and the voltage Vc on the gate of the PMOS transistor M4, which is a drift-reduction voltage. When the operational amplifier 400 is operating in the normal mode, the switches SW2, SW3, and SW5 are turned off by the signal φ 1, and the switches swi and SW4 are turned on by the signal φ 2 by 200812220 as shown in FIG. 14 , and the differential input pair 402 wipes the NMOS transistor M1 and The gate of M2 is connected to voltages v and v+ respectively to turn on currents η and 12, and PMOS capacitor 408 is stored in face #, 企,上 &广;
帝仔的飄移蝻減電壓抵消電源電壓VDP 的-部分’因此供應至PM0S電晶體M4的閘極偏壓Vc 已經包含飄移因子在内，使得PM0S電晶體M4導通的電 流14已經補償了飄移所造成的影響。換言之，由於在儲存 模式時針對電流16及17之間的不匹配情形調整pM〇s電 晶體M4—閘極上的偏壓Vc，故能降低偏移電壓。在最佳狀 況F，可以達到零偏移電壓的效果，也缺完成去除偏移 效應。 一般來說，電容難免都有漏電流問題，在某些電容的 漏電流很大的情況下，將使儲存在M〇S電容中的飄移消 減電壓衰減，導致降低偏移電壓的效果也降低。圖15係 本發明的第二實施例，假設運算放大器4〇〇中的pM〇s電 晶體M4在實際積體電路的製作上係由多個pM〇s電晶體 組成’因此，為了降低PMOS電容408漏電流的影響，可 以將PMOS電晶體M4中部分PMOS電晶體502的閘極接 至偏壓Bias 1或其他偏壓，如圖15所示，另一部分pm〇S 電晶體504則連接PMOS電容408，如此可保證PMOS電 晶體M4中有部份的PMOS電晶體502不受PMOS電容408 的漏電流影響而正常工作，同時有一部份的PMOS電晶體 504可以用來降低偏移電壓，而且可以根據應用的情況調 整PMOS電晶體502及504兩部分的比例。在其他實施例 中，也可以藉由增加一與PMOS電晶體M4並聯而其閘極 11 200812220 係連接至偏壓Biasl或其他偏壓的電晶體，來防止因PMOS 電容408漏電流而造成的影響。 圖16係本發明的第三實施例，其為一 P輸入折疊疊 接架構的運算放大器600，其中，NMOS電晶體M9連接 在NMOS電晶體M7及接地GND之間，受控於偏壓Biasl 以導通電流13，NMOS電晶體M10連接在NMOS電晶體 M8及接地之間，受控於電壓Vc以導通電流14，NMOS 電容608連接在NMOS電晶體M10的閘極及接地GND之 間，開關SW5連接在NMOS電晶體Μΐϋ的閘汲極之間， 鏡射電路604包含由PMOS電晶體M3、Μ4、Μ5及Μ6 組成的疊接電流鏡，用以鏡射電流15產生電流16至運算 放大器500的輸出Vo，在差動輸入對602中，電流源606 的一端連接至PMOS電晶體Ml及M2，另一端則連接電 源電壓VDD，開關SW1連接在PMOS電晶體Ml的閘極 及電壓V_之間，開關SW2連接在PMOS電晶體Ml的閘 極及電壓Vref之間，開關SW3連接在PMOS電晶體M2 的閘極及電壓Vref之間，開關SW4連接在PMOS電晶體 M2及電壓V+之間，PMOS電晶體Ml及M2根據其閘極 上的電壓導通電流11及12。同樣地，在儲存模式時，運 异放大器600的輸出Vo浮接，開關SW2、SW3及SW5 導通而開關SW1及SW4截止，使差動輸入對602的PMOS 電晶體Ml及M2的閘極連接相同的電屢vref，而nm〇S 電晶體Ml0接成二極體以自動調節其閘極上的電壓vc， 進而使電流14與電流12及Γ7達到平衡。由於此實施例中 12 200812220 的NMOS電容608的一端接地，因此其上儲存的飄移消減 電壓等於NM0S電晶體M10閘極上的偏壓Vc。在正常模 式時，開關SW2、SW3及SW5截止而開關SWi及SW4 導通，使差動輸入對602中的PMOS電晶體M1及M2分 別連接電壓V·及V+，NMOS電容608則供應電壓Vc至 NMOS電晶體M10的閘極。 同樣的，為了降低NMOS電容608漏電流的影響，可 以將部^ NMOS電晶體M10的閘極連接至偏壓或 其他偏壓，或者增加一與NM0S電晶體Mi〇並聯而其閘 極連接至偏壓Bias 1或其他偏壓的電晶體。 雖然在上述實_巾用切存飄移消減電壓的M〇s 電容概及_在電路的表達上是-個電容，但是在實際 積體電路的製作上可以包含多個並聯的m〇s電容實體， 而且也可以顧積體電路上的寄生電容來實現。由於此用 來儲存飄移消減電壓的MOS雷交心〇 ^ ^ ^ 〇兒夺408及608有一端係用 來連接電源VDD或接地GND，而尤3…奸门，丄 士 而不疋净接，因此在以積 體電路實現時可以有較低成本的優點。 13 200812220 【圖式簡單說明】 圖1顯7^―傳統的折疊疊接式運算放大器； 圖2顯TF-運鼻放大器的方塊圖； 圖3顯示一比較器的方塊圖； 圖4係圖3比較器在理想狀況下的輸入及輸出關係 圖； 圖5係圖3比較器在非理想狀況下的輸入及輸出關係 圖； 尚6顯示將自動歸零技術應用在圖2中運算放大器 200的電路架構； 圖7顯示圖6中運算放大器200在儲存模式時的電路 架構； 圖8顯示圖6中運算放大器2〇〇在正常模式時的電路 架構； 圖9顯示將自動歸零技術應用在圖3中比較器3〇〇 電路架構； ° 圖1〇顯示圖9中比較器300在儲存模式時的電路架 構； 〃 圖Π顯示圖9中比較器300在正常模式時的電路架 構； 圖12係本發明的第一實施例； 圖13顯示圖12中運算放大器400的儲存模式· 圖14顯示圖12中運算放大器400的正常模式· 圖15係本發明的第二實施例；以及 14 200812220 圖16係本發明的第三實施例。 【主要元件符號說明】 100 運算放大器 102 差動輸入對 104 鏡射電路 106 電流源 200 運算放大器 202 電壓源 204 理想運放大器 300 比較器 302 電壓源 304 理想比較器 400 運算放大器 402 差動輸入對 404 鏡射電路 406 電流源 408 PMOS電容 502 PMOS電晶體 504 PMOS電晶體 600 運算放大器 602 差動輸入對 604 鏡射電路 606 電流源 15 200812220 608 NMOS 電容 16The drifting voltage of the Emperor Aberdeen offsets the -portion of the power supply voltage VDP. Therefore, the gate bias voltage Vc supplied to the PM0S transistor M4 already contains the drift factor, so that the current 14 of the PM0S transistor M4 is turned on to compensate for the drift. Impact. In other words, since the bias voltage Vc on the gate of the pM?s transistor M4 - the gate is adjusted for the mismatch between the currents 16 and 17 in the storage mode, the offset voltage can be lowered. In the best case F, the effect of zero offset voltage can be achieved, and the offset effect is also eliminated. In general, capacitors are inevitably subject to leakage current problems. In the case of large leakage currents of some capacitors, the drift-reduction voltage stored in the M〇S capacitor is attenuated, and the effect of lowering the offset voltage is also reduced. Figure 15 is a second embodiment of the present invention, assuming that the pM〇s transistor M4 in the operational amplifier 4A is composed of a plurality of pM〇s transistors in the fabrication of the actual integrated circuit. Therefore, in order to reduce the PMOS capacitance 408 leakage current, the gate of part of the PMOS transistor 502 in the PMOS transistor M4 can be connected to the bias Bias 1 or other bias, as shown in Figure 15, another part of the pm 〇 S transistor 504 is connected to the PMOS capacitor 408, this ensures that a part of the PMOS transistor 502 in the PMOS transistor M4 is not affected by the leakage current of the PMOS capacitor 408, and a part of the PMOS transistor 504 can be used to reduce the offset voltage, and The ratio of the two portions of the PMOS transistors 502 and 504 is adjusted according to the application. In other embodiments, the gate electrode 11 200812220 can be connected to the biased Biasl or other biased transistor by adding a parallel connection with the PMOS transistor M4 to prevent the PMOS capacitor 408 from leaking. . Figure 16 is a third embodiment of the present invention, which is an operational amplifier 600 of a P input folding splicing architecture, wherein an NMOS transistor M9 is connected between the NMOS transistor M7 and the ground GND, controlled by the bias Biasl The NMOS transistor M10 is connected between the NMOS transistor M8 and the ground, and is controlled by the voltage Vc to conduct the current 14. The NMOS capacitor 608 is connected between the gate of the NMOS transistor M10 and the ground GND, and the switch SW5 is connected. Between the gate and drain of the NMOS transistor 镜, the mirror circuit 604 includes a stacked current mirror composed of PMOS transistors M3, Μ4, Μ5, and Μ6 for mirroring the current 15 to generate a current 16 to the output of the operational amplifier 500. Vo, in the differential input pair 602, one end of the current source 606 is connected to the PMOS transistors M1 and M2, the other end is connected to the power supply voltage VDD, and the switch SW1 is connected between the gate of the PMOS transistor M1 and the voltage V_. The switch SW2 is connected between the gate of the PMOS transistor M1 and the voltage Vref, the switch SW3 is connected between the gate of the PMOS transistor M2 and the voltage Vref, and the switch SW4 is connected between the PMOS transistor M2 and the voltage V+, and the PMOS is electrically connected. Crystals Ml and M2 are based on the electricity on their gates 11 and 12 conduct current. Similarly, in the storage mode, the output Vo of the operational amplifier 600 is floated, the switches SW2, SW3, and SW5 are turned on, and the switches SW1 and SW4 are turned off, so that the gates of the PMOS transistors M1 and M2 of the differential input pair 602 are connected in the same manner. The electric current is repeatedly vref, and the nm〇S transistor M10 is connected to the diode to automatically adjust the voltage vc on the gate thereof, thereby balancing the current 14 with the currents 12 and Γ7. Since one end of the NMOS capacitor 608 of 12 200812220 in this embodiment is grounded, the drift subtraction voltage stored thereon is equal to the bias voltage Vc on the gate of the NM0S transistor M10. In the normal mode, the switches SW2, SW3, and SW5 are turned off and the switches SWi and SW4 are turned on, so that the PMOS transistors M1 and M2 in the differential input pair 602 are respectively connected to the voltages V· and V+, and the NMOS capacitor 608 is supplied with the voltage Vc to the NMOS. The gate of the transistor M10. Similarly, in order to reduce the influence of the leakage current of the NMOS capacitor 608, the gate of the NMOS transistor M10 may be connected to a bias voltage or other bias voltage, or may be connected in parallel with the NMOS transistor Mi 而 and its gate connected to the bias voltage. Press Bias 1 or other biased transistor. Although the M〇s capacitance of the above-mentioned real-purpose wiper-reducing voltage is a capacitor in the expression of the circuit, a plurality of parallel m〇s capacitor entities may be included in the fabrication of the actual integrated circuit. And can also be realized by the parasitic capacitance on the integrated circuit. Because this is used to store the drift-reduction voltage of the MOS Thunder Hearts ^ ^ ^ 〇 夺 408 and 608 have one end is used to connect the power supply VDD or ground GND, and especially the door, the gentleman does not slam the net, so There is a lower cost advantage when implemented in an integrated circuit. 13 200812220 [Simple description of the diagram] Figure 1 shows the traditional folding cascode operational amplifier; Figure 2 shows the block diagram of the TF-transistor amplifier; Figure 3 shows the block diagram of a comparator; Figure 4 shows Figure 3 The input and output relationship diagram of the comparator under ideal conditions; Figure 5 is the input and output relationship diagram of the comparator of Figure 3 under non-ideal conditions; Figure 6 shows the circuit of applying the auto-zero technique to the operational amplifier 200 of Figure 2. Figure 7 shows the circuit architecture of the operational amplifier 200 in the storage mode of Figure 6; Figure 8 shows the circuit architecture of the operational amplifier 2 in Figure 6 in the normal mode; Figure 9 shows the application of the automatic zeroing technique in Figure 3. Medium Comparator 3〇〇 Circuit Architecture; ° Figure 1〇 shows the circuit architecture of Comparator 300 in the storage mode of Figure 9; Figure Π shows the circuit architecture of Comparator 300 in normal mode in Figure 9; A first embodiment of the invention; Fig. 13 shows a storage mode of the operational amplifier 400 of Fig. 12; Fig. 14 shows a normal mode of the operational amplifier 400 of Fig. 12; Fig. 15 is a second embodiment of the present invention; and 14 200812220 this invention The third embodiment. [Main component symbol description] 100 Operational amplifier 102 Differential input pair 104 Mirror circuit 106 Current source 200 Operational amplifier 202 Voltage source 204 Ideal amplifier 300 Comparator 302 Voltage source 304 Ideal comparator 400 Operational amplifier 402 Differential input pair 404 Mirror circuit 406 Current source 408 PMOS capacitor 502 PMOS transistor 504 PMOS transistor 600 Operational amplifier 602 Differential input pair 604 Mirror circuit 606 Current source 15 200812220 608 NMOS capacitor 16