TW200812092A - A vertically separated horizontal type double-gate multi-bits SONOS and the method for making the same - Google Patents

Abstract

The present invention relates to a vertically separated horizontal type double-gate multi-bits SONOS and the method for making the same. The method comprises the following steps: (a) providing a substrate having a first wafer layer, an oxidation layer and a second wafer layer; (b) forming a first insulation layer on the first wafer layer; (c) forming an opening on the substrate; (d) forming a second insulation layer on the sidewall of the opening; (e) growing the second wafer layer into the opening to form a bottom gate; (f) forming two discontinuous first dielectric layers on the top surface of the bottom gate; (g) forming a conductive layer; (h) forming two discontinuous second dielectric layers; (i) forming agate; and (j) forming a source and a drain. Whereby, the bottom gate and the gate have the effect of self-alignment.

Description

200812092 IX. Description of the Invention: [Technical Field] The present invention relates to a SONOS memory and a method of fabricating the same, and more particularly to a storage device having a horizontal shape and separated from each other in a vertical direction by a gate multi-element SONOS Memory and its manufacturing method. [Prior Art]

A layer of material derived from flash memory (FLASH) and non-volatile memory electronic erasing read-only memory (EEPROM) technology or other material layer that captures and retains eight electrons _ oxide-based (SONOS) memory architecture, first proposed by Dr. Shi Min and others, the United States, Europe, Taiwan, Japan, South Korea's semiconductor industry and academic circles extensive research and discussion, but there are still many such SONOS Disadvantages, such as the construction of the multi-layer architecture of the extremes, consumes a large voltage to guide the channel layer underneath, and the stored charge is easily dissipated. For the storage medium without the multi-layer architecture, The charge is extremely easy to escape; in addition, for the horizontal oxide-nitride-oxide (ΟΝΟ) structure of the storage mechanism J to improve the high operating voltage of the component, it is easy to produce due to the use of multiple masks. The disadvantage that the underlying structure cannot be properly aligned, in addition to the horizontal storage σ structure is easy to k into 7G pieces can not continue to shrink the limit length and channel length _); In addition, for the two-element of its = s 兀 兀 除了 需high Operating electricity (4), if there is no effective isolation in the two charge storage intervals, the stored charge will gradually diffuse from the high-density charge region: the density region will cause difficulty in reading the bit column, if it is to be isolated, it cannot be In addition to the lack of self-alignment, the manufacturing steps are complicated; in addition, the multi-layer architecture of the 111915.doc 200812092 at the gate extreme consumes a large voltage to guide the channel layer underneath, even in the read mode. A large voltage operation is required, and a small amount of impact ionization is generated, which affects component reliability and storage effective time. Finally, for a horizontal crucible structure, the charge distribution is too dispersed to induce a strong electric field to produce a threshold voltage. Great changes make it difficult to interpret. Paper [Wen-Jer Tsai, Chih-Chieh Yeh, Nian-Kai Zous? Chen-Chin Liu, Shih-Keng Cho, Tahui Wang, Samuel C. Pan, Chih-Yuan Lu, ''Positive Oxide Charge-Enhanced Read Disturb in a Localized Trapping Storage Flash Memory Cell,, in IEEE TRANSACTIONS ON ELELCTRON DEVICES, VOL. 51, NO. 3, MARCH 2004·] is a SONOS component with a horizontal ΟΝΟ structure below the gate extreme, when the horizontal structure is long enough, The high-voltage writing operation at the source or the drain causes the area of the electron collision free phenomenon to be different, and the electrons that have entered the storage area after passing through the gate oxide layer are localized, but the structure has The self-alignment feature of the upper ΟΝΟ and the channel is completely matched. However, when the component is miniaturized, the localization phenomenon will gradually disappear, the bit reading window is compressed, and the function of the double bit is lost. In addition, since the multi-layer structure is used in the gate, The operating voltage for writing or erasing is too high and may not meet the electrical requirements of the mainstream integrated circuit. Paper [Rossella Ranica, Alexandre Vi 11 aret, Pascale

Mazoyer, Stephane Monfray, Daniel Chanemougame, Pascal Masson, Arnaud Regnier, Cyrille N. Dray, Roberto Bez, and Thomas Skotnicki, "A New 40-nm SONOS Structure Based 111756.doc 200812092 on Backside Trapping for Nano-scale Memories''] In order to make the horizontal ΟΝΟ structure to the SONOS component below the gate extreme, this structure effectively improves the component structure mentioned in the previous paper in the operating voltage, because the upper gate is not a multi-layer structure, the writing voltage is written or erased. It is not too high; however, as mentioned in the previous paper, when the horizontal structure is long enough, the high-voltage writing operation at the source or the drain causes the area of the electron collision free phenomenon to be different, so that it passes through the lower side. The electrons in the upper oxide layer of the crucible are localized in the storage area. However, when the components are miniaturized, the localization phenomenon will be weakened by mutual diffusion or interference without effective isolation. The bit interpretation window is compressed, and the double bit is compressed. The function is lost. In addition, after completing the lower horizontal ΟΝΟ structure, the structure will construct the upper gate, and there will be self-right. The quasi-problem, if the gate cannot be placed in the center of the horizontal ΟΝΟ structure, the localization phenomenon is asymmetrical when writing from the source and the drain, and the bit reading window is compressed. When it is not refreshed for a long time, it will spread to the other end due to the gradual diffusion of charge to the other end. It is not easy to completely under-erase. [Laurent Bqreuil, Luc Haspeslagh, Pieter Blomme, Dirk Wellekens, Joeri De Vos, Martino Lorenzini, and Jan Van Houdt, , fA New scalable Self-Aligned Dual-Bit Split-Gate Charge-Trapping Memory Device'丨in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52? NO 10, OCTOBER 2005·] is a SONOS component that is used to make the horizontal ONO structure below the gate extreme. However, this structure uses isolation technology to ensure that the charge stored in different regions will not diffuse due to different concentrations or form due to electric field crossover. Inter-space 111756.doc 200812092 Interference' makes the length of the gate coincide with the length of the channel, but when it is necessary to make the storage area of each bit just on both sides of the gate end It is necessary to use another layer of mask definition, which will result in different lengths of the storage area of the two bits. Even when the gate is further reduced, there may be a slight offset of the mask, so that the storage area of a certain bit is completely Disappearing, in addition, the gate length is the characteristic length' is bound to make the structure more limited in miniaturization. Moreover, this structure still has to use a multi-layer structure, which will make the writing or erasing operation voltage too high. Can not meet the electrical requirements of the mainstream integrated circuit. Papers [Hwan Cho, Tai-su Parki, Si Yoimg Choi, jong Duk Lee, and Jong-Ho Lee1 " Body-Tied Double-Gate SONOS Flash (Omega Flash) Memory Device Built on Bulk Si Wafer", in Semiconductor R& D Center, Samsung

The components of Electronics Co., Ltd.] want to use the double-gate or even the multilateral gate to increase the drive current and enhance the high-speed collision dissociation effect in the depletion region at the end of the channel. This is intended to form a bilateral gate. Even at the multi-gate gate, or other more complicated gate structures, the self-alignment problem occurs between the gates of different faces. This problem is more serious after the components are miniature, and the relative geometric positions of the gates of different faces are often not available to the designer. The requirement to accurately achieve 'this is why the reticle cannot be absolutely accurate due to the alignment of the small scale' will cause unnecessary heating effect, and even different thresholds of different SONOS components in the same wafer will be Greatly reduce the value of the idea. 'This is to make a bilateral gate, even the multi-gate S S 〇 〇 s "a type of self-alignment problem will be encountered. Shunwen [Rob van Schaijk, Michiel van Duuren, Pierre 111756.doc -10- 200812092

Goann, Wan Yuet Mei, Kees van der Jeugd, "Reliability 〇f embedded SONOS memories'', in IEEE 2004·] is a SONOS component that forms a storage area under the gate, which is the prototype of the SONOS component, without self The problem of alignment, whether it is gate-to-channel or gate-to-storage structure, is only a one-dimensional memory. U.S. Patent Publication No. 2006/0,068,546 discloses a SONOS component that can be completely isolated per bit, by first stacking 0Ν0·, and then dug out a well with a mask definition to make a protective layer on both sides of the well. Then, in turn, the gate oxide layer and the gate deuteration layer fill the well horizontally, so that each bit can be completely isolated, but a well is dug out by a mask definition to separate the two bit storage areas. When the size of the storage area is uneven, this will cause a serious increase in the component's daily shrinkage. Even when the mask is too large, the storage area of a bit can be completely disappeared. In addition, during the filling process. Emphasizing the level will increase the difficulty of the process. In addition, after the side spacer is completed, the well forms an inverted triangle. If a few touches of free charge move to the lower tip of the well, it is easy to form a tip discharge, which is unexpected. The charge accumulation may have an influence on the change of the threshold voltage of the charge storage area on both sides. In addition, the 'gate length is the characteristic length' is bound to make the structure more limited in miniaturization. Furthermore, this knot Still want to use a multi-layer structure, will write or erase operation voltage is too high, it may not meet the electrical requirements of mainstream integrated circuit. U.S. Patent Publication No. 2004/0,207,001 discloses a self-aligning flash component 'only for a single bit flash component, but with 111756.doc -11 - 200812092 my effect on the back' but this architecture cannot Nearly the same number of reticle can be used to complete a more complex structure to achieve multi-bit storage, and to improve the efficiency and the efficiency of the bit accumulation. US Patent Publication No. 2002/0,004,291 discloses a SONOS τ yak that can be isolated from the king, and is similar to the US Patent Publication No. 2/6/〇, 〇68, 546 5 tigers. The gate is used as a reticle to cut off the s〇n〇s components that can be completely isolated without each bit. The only mask that forms the gate must be placed in the 〇N〇. In the center of the architecture, otherwise the storage area will be uneven when the two bit storage areas are to be formed. This will cause serious damage when the components are miniature. Even when the mask is too large, it will cause a bit storage. The possibility of complete disappearance of the zone, in addition, the length of the gate is the characteristic length, which is bound to make the structure more limited in miniaturization. Again, this structure still has to use a multi-layer structure, which will cause the writing voltage to be erased or erased. Too high, may not meet the electrical requirements of the mainstream integrated circuit. U.S. Patent Publication No. 2005/0,106,793 is also a single-bit FLASH component, which is substantially identical to the conventional flash component, and is formed by stacking the gate oxide layer, the FLASH layer, the upper resistive oxide layer and the gate layer. The etch is defined by a mask, although it has a good self-alignment effect. However, this architecture cannot be used in a relatively complicated structure in the same number of reticles to achieve multi-bit storage and improve performance. , the power of the bit set. The Republic of China Patent Nos. 237349 and 239073 all disclose two-dimensional SONOS components, which are horizontal three-layer structures and are effectively isolated. The components of the horizontal storage mechanism located below the gates are still two. Bit storage H1756.doc -12- 200812092 The length of the zone is uneven when the mask is defined. The choice of +7 is too large, and the component is limited. U.S. Patent Publication No. 20〇5/〇285 177铼tκ π, 2/0 is also a SONOS component that forms a storage area under the gate, and is used as a channel material for the door. When the two bit storage areas are separated, the size of the storage area will be uneven, which will be seriously increased when the components are miniature. Even when the mask is too large, the storage area of a bit may disappear completely. As can be seen, when the mask is used to define the closed pole, there will be an alignment problem, which will cause problems when the bit storage area is miniaturized. Referring to U.S. Patent Publication No. 2,6, Chuan, No. 23,513, a large gate is made and a well is dug in the large gate, and two bit storage areas are left by the residual of the side wall, and then the upper end of the well is used for sedimentation. To automatically align the gate, this concept has advantages in alignment, but the multi-layer gate still consumes a large voltage, and the gate is extremely characteristic length. During the miniaturization process, the two elements are gradually approaching, which will compress the possibility of miniaturization. U.S. Patent Publication No. 2005/0,255,657, which utilizes the continual deposition of a three-layer or eve layer structure, is defined by a reticle, leaving a sidewall during the etching process, but if the reticle cannot just etch the layered structure above the bump The effectiveness of this component is reduced by the multi-layer structure that just wants to leave the side wall. U.S. Patent Publication No. 2005/0,242,391, the disclosure of which is incorporated herein by reference in its entirety, the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all 'This is a single bit S〇N〇S, which is not scalable. In addition, as mentioned earlier, 'multilayer gates still require a large operating voltage. 111756.doc 13 200812092 It can be found from the above examples that in different papers and patents, there are some difficulties and problems faced in the development of S0N0S components, such as the multi-slide architecture built on the gate extremes. Large voltage; the stored charge is easy to escape, for a storage medium without a multi-layer structure or without insulation, the charge is easily dissipated; for the horizontal ΟΝΟ structure that is built under the storage mechanism to improve the high operating voltage The production requires multiple masks, the upper and lower layers will not be properly aligned during the miniaturization; the horizontal storage structure also limits the component shrinkage (due to & horizontal structure length and channel length); Other s〇N〇s components of the element, without effective isolation in the two charge storage intervals, will cause the stored charge to diffuse and cause the bit reading window to be reduced. If it is to be isolated, except for the lack of self-alignment, the steps are made. It is also complicated; in the end, for the horizontal 〇N〇 structure charge knife cloth 7 knife scattered, it is possible that the synthetic electric field does not change the threshold voltage or make the double bit Concept reduction. Therefore, it is necessary to provide an innovative and progressive storage unit having horizontal shapes, and double gate multi-bit s〇n〇s memory bodies separated from each other in the vertical direction and a method of manufacturing the same to solve the above problems. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for manufacturing a dual gate multi-bit S〇N〇S memory device having horizontally shaped memory cells separated from each other in a vertical direction, comprising the following steps: (4) providing a memory cell The substrate includes a first wafer layer, an oxide layer and a second wafer layer, the oxide layer being interposed between the first wafer layer and the second wafer layer; 111756.doc -14 - 200812092 (b) forming a first insulating layer on the first wafer layer, the recess penetrating the first insulating layer, and exposing the second wafer layer; on the sidewall of the recess 'and exposing the first (C) forming a recess in the substrate and forming the first wafer layer and the oxide layer, (d) forming a second insulating layer on the two wafer layers; (4) growing the second wafer layer to the recess Inner to form a protruding bottom gate; -° (〇 forming two separate first dielectric layers on the top surface of the bottom gate. (g) forming a conductive layer on the first insulating layer and the like a first dielectric layer, the upper surface of the conductive layer has a recess; (h) forming two separate second dielectric layers in the recess (i) forming a gate on the second dielectric layers; and (j) forming a source and a; and a pole. \ / Another object of the present invention is to provide a horizontally shaped storage a dual gate multi-bit (10) memory device separated from each other in a vertical direction, comprising: a substrate, a first insulating layer, a second insulating layer, a bottom opening, and two separated first-dielectric a layer, a conductive layer, two separated second dielectric layers, a gate, a source, and a drain. The substrate includes a first wafer layer, an oxide layer, a second wafer layer, and a recess, the oxide layer is interposed between the first wafer layer and the second wafer layer. The first insulating layer is located on the first wafer layer ±, and the groove of the substrate penetrates the first An insulating layer, the first crystal (four) and the oxide layer. The second insulating layer is located on a sidewall of the recess of the substrate. The bottom electrode protrudes from the second wafer layer into the recess. a dielectric layer is respectively located on the bottom gate. The conductive layer 111756.doc •15·200812092 is located on the first insulating layer and the first dielectric layer, the guiding The upper surface of the layer has a recess. The second dielectric layers are respectively attached to the recess. The gate is located on the second dielectric layer, and relative to the recess, the "original pole and the / and the poles are formed on the conductive layer and are respectively located on two sides of the gate.

In the present invention, two horizontal germanium structures (two first dielectric layers or two second dielectric layers) as storage regions are effectively separated, so that they can resist electrical interference of two bits or mutual charge diffusion. . Moreover, each bit storage area can be operated separately, so that write erasing is more efficient and reliable than using local trapping (Τη叩 long horizontal ONQ, and the upper and lower gates can be independently or cooperatively operated by voltage operation M write The ingress/erase is enhanced and efficient. In addition, the invention has the self-alignment of Wei', not only the process step is simple, but the mask is not separately developed by the component micro-shrinking, and the two storage areas are cut out by the conventional use of the mask definition. In terms of SONOS, the two storage areas are more symmetrical and more reliable. In addition, the present invention conforms to the mature metal oxide semiconductor (MOS) manufacturing process, so that it does not cause cost in the industry. Furthermore, it can be adjusted in the present invention. The difference between the upper and lower ΟΝΟ architecture makes the bit interpretation window adjustable. Finally, the present invention is a double-layered gate structure, and the upper and lower gates can be operated independently or cooperatively, so that two channels or other possibilities can be generated. The position at which the impact ion ionization phenomenon occurs can be selected. [Embodiment] Referring to the drawings! to FIG. 17, a storage unit having a horizontal shape according to the present invention is shown, and is in a vertical direction. Schematic diagram of the manufacturing method of the (four) extremely multi-bit s〇N〇s memory separated from each other. Referring first to FIG. 1, a substrate i is provided. In the embodiment of 111756.doc -16-200812092, the substrate i is a silicon-on-insulator (SCI) substrate comprising a first wafer layer u, an oxide layer 12 and a second wafer (four), the oxide layer 12 is interposed on the first Between a wafer (four) and the second wafer layer 13. Then, a first insulating layer 14 is formed on the first wafer layer 11. In the embodiment, the material of the first insulating layer 14 is oxidized. Or a dielectric material, and the first insulating layer 丨4 is formed by low pressure chemical vapor deposition (LPCVD). Referring to FIG. 2, a groove 15 is formed on the substrate 1, and a g groove 15 is formed therethrough. The first layer, the edge layer 14, the first wafer layer n and the oxide layer 12, and exposed a round layer 13. In this embodiment, after completing the standard cleaning step and completing the mask After the process, the recess 15 is defined by an isolation technique (L0C0S, STI)-mask, and the R method is used to etch the first wafer layer by using reactive ions. 11 to form the recess 15 5. The multi-pattern is formed on the sidewall of the recess 15 to form a second insulating layer 16 on the side wall of the recess 15. In this embodiment, the second insulating layer The material of the layer 16 is an oxide or other dielectric material. The second insulating layer 16 is formed on the first insulating core and the groove 15 by low pressure chemical vapor deposition, and the uranium is adjusted. The etched etching parameter etches the second insulating layer 位于6 at the bottom of the groove 15 and above the first, rim layer 14 with active ions, leaving only the second insulating layer located in the groove 15 16. The second wafer layer 13 is exposed. The second wafer layer 13 is located at the bottom of the recess 15 and extends into the recess 15 to form a bottom gate of the dog. Extreme 17. In the present embodiment, the second wafer layer 13 is grown by a selective epitaxial growth method. ^ ^elective Epitaxy Growth, SEG) 111756.doc -17. 200812092. The first dielectric layer is connected to the top of the bottom closed pole 17 in the case of the second dielectric layer. The formation of the first dielectric layer is as shown in FIG. Layer 18 is on the bottom pole 17. The crucible is carefully treated by thermal oxidation to cause the bottom gate electrode 7 to form an insulating oxide layer (i.e., the third insulating layer 18).

And: Ϊ-':' formed - the first electron storage layer 19 is on the first insulating layer 14:: rim layer 18. In the present embodiment, the shell of the first electron storage layer is a material such as a nitride, an aluminide, an aluminum telluride or a button compound, and the method of forming the film is (iv) chemical vapor deposition. Separating: the first electron layer 19 is partially removed to form two sub-zeroes' from the charge storage region 20, and the third insulating layer 18 is exposed, and the first-separated charge storage regions 2 are respectively attached to The second insulating layer is on the top. In this embodiment, the removed first active ion of the first electron storage layer 19 is engraved. It can be understood that, in the process of surname, the jth separation, the storage area 2G can not completely cover the underlying (four) three insulation layer ^, so the center of the third insulation layer 18 may be engraved by the surname, and The bottom gate 17 below is exposed. The fourth insulating layer 21 is formed on the first insulating layer 14, the first separated charge storage region 2, and the third insulating layer 18. In the present embodiment, the material of the fourth insulating layer 21 is an oxide or other dielectric material, and the method of forming the film is a low-pressure chemical vapor deposition method. Referring to Figure 8, the fourth insulating layer 21 is partially removed to a suitable thickness. In the present embodiment, the etching method of the fourth insulating layer 21 is alive: ion etching 111756.doc -18-200812092. It is to be noted that the fourth insulating layer 21 is in contact with the third insulating layer 18. It can be understood that, if the third insulating layer "the center has been etched away, the fourth insulating layer 21 will contact the third insulating layer 18 and the bottom gate 17; second, if the fourth In the embodiment, the third insulating layer 18, the first separated charge storage region 20, and the fourth insulating layer 21 are formed. The insulating layer 21 is formed to a proper thickness. A first dielectric layer 22, that is, two separate first dielectric layers 22 are provided in the present invention. In the present embodiment, the first dielectric layer 22 is a three-layer N〇 structure. In other applications, the fourth insulating layer 21 can be omitted. Therefore, the first dielectric layer 22 is a two-layered ON structure (including the third insulating layer 18 and the first isolated charge storage region 20). Referring to FIG. 9, a conductive layer 23 is formed over the fourth insulating layer. The upper surface of the layer 23 has a concave σ23, and the recess is formed at a relative position between the first dielectric layers 22. In this embodiment, the material of the conductive layer 23 is polycrystalline stone, and the system is reduced in voltage. After the conductive layer 23 is formed by vapor deposition, the upper surface of the conductive layer 23 is etched. After a plurality of deposition and etching, a relatively rounded recess 231 can be formed to deepen the groove pattern. The second dielectric layer is separated from the recess 231. In this embodiment, the second dielectric layer is formed as follows: The fifth insulating layer 24 is on the conductive layer 23. In the embodiment, the material of the fifth insulating layer 24 is oxide or other dielectric 111756.doc -19-200812092 Vapor deposition method or thermal oxidation method. " Figure 11 forms a second electron storage layer 25 in the fifth insulating layer 24 K t 'the material of the second electron storage layer 25 is nitrided, 1 ruthenium The material can be provided with a trapping material, and the forming method is a low-pressure chemical vapor deposition method. Referring to Figure 12, the second electronic storage layer is partially removed to form two separate ^ ί - knives. Deviated from the charge storage area and exposed the fifth insulating layer 24,

The separate charge storage regions 26 are attached to the side of the recess 231, respectively. In the present embodiment, the second electron storage layer 25 is removed by reactive ion etching. > The image of the sixth insulating layer 27 is on the fifth insulating layer and the second separated charge storage regions 26. In this embodiment, the material of the sixth insulating layer 27 is an oxide or other dielectric material, and the forming method is a low pressure chemical vapor deposition method. The first insulating layer, the second insulating layer 16, the second insulating layer 18, and the fourth insulating layer? ! The fifth insulating layer μ and the sixth insulating layer 27 are provided, and the material of the a_ layer 7 may be the same or different. It is to be noted that the sixth insulating layer 27 is in contact with the fifth insulating layer. In this embodiment, the 箆$ is g a. The fifth layer, the color edge layer 24, the second separated charge storage region 26, and the sixth insulating layer 27 form a dielectric layer 28, that is, two separate dielectric layers in the present invention. 28. The second dielectric layer is attached to the sidewall of the recess 231, respectively. In this embodiment, the second dielectric layer 28 is a three-layer SSf〇 structure. The interface is formed on the second dielectric layer 28. In the present embodiment, the method of forming the gate is as follows. 111756.doc -20. 200812092 Referring to FIG. 14, a gate layer 29 is formed on the sixth insulating layer 27. In the present embodiment, the material of the gate layer 29 is polycrystalline germanium, and the gate layer 29 is formed by low pressure chemical vapor deposition. The gate layer 29 is partially removed with reference to Fig. 15 to leave a residual stone 291. In the present embodiment, the gate ruthenium layer 29 is etched using active ions. The g Hai residual 2 91 is located at a relatively central position of the notch 2 3 1 . Referring to Fig. 16, the residual crucible 291 is grown to form a gate 3?. In the present embodiment, the residual stone 291 is grown by a selective epitaxial growth method. Since the residual 矽 291 is located at the opposite position of the recess 23 1 , the gate 30 naturally has a self-aligning effect during the growth process, that is, the gate 30 is formed in the second dielectric after being grown. In the middle of layer 28. Next, a gate protection layer 31 is formed on the gate electrode 30 and the sixth insulating layer 27. In this embodiment, the gate protection layer 31 is also an oxide layer (used as an oxide layer for ion implantation scattering). Next, the doped source 32 and drain 33 are self-aligned using ion implantation techniques. Referring to FIG. 17, if necessary, the gate protection layer 3 is removed to expose the gate 30, the source 32, and the drain 33 to form a horizontally shaped memory cell and vertically in each other. Separate dual gate multi-bit SONOS memory 4 〇 Referring again to FIG. 17, a schematic diagram of a dual gate multi-bit S〇n〇s memory with horizontal storage cells of the present invention and separated from each other in the vertical direction is shown. . The double-gate multi-element SONOS memory 4 having horizontal storage cells and separated from each other in the vertical direction includes a substrate, an insulating layer 14, a second insulating layer 16, and a bottom gate 17, Two separate first layers 111756.doc -21 - 200812092 - electric layer 22 a conductive layer 23, two separated second dielectric layers 28, a gate 3 〇, a source 3 2 and a drain 3 3. In this embodiment, the substrate 1 is an insulating substrate including a first-wafer layer U, an oxide layer 12, a second wafer layer 13, and two recesses 15. The oxide layer 12 is The first wafer (four) and the second wafer layer 13 are sandwiched between the first wafer (four) and the second wafer layer 13. The first insulating layer 14 is located on the first wafer layer, and the recess 15 of the substrate 1 extends through the first insulating layer 14, the first wafer layer 11 and the f, the oxide layer 12 . The second insulating layer 16 is located on the sidewall of the recess 15 of the substrate. The bottom gate 17 is protruded from the second wafer layer 13 to the recess. Inside. The material of the first insulating layer U and the second insulating layer 16 is an oxide or a dielectric material. The first dielectric layers 22 are respectively located on the bottom gate 丨7. In the present embodiment, each of the first dielectric layers 22 is a horizontal oxide-nitride-emulsion (ONO) structure including a third insulating layer 18, a first separated charge storage region 20. And a fourth insulating layer 2, the third insulating (four) tether = the bottom gate 17; the first separating charge region 20 is located on the second insulating layer, the first separated charge storage region 2g剌In order to store electricity::: The material is a material such as nitride, aluminide, aluminum telluride or telluride. The fourth insulating layer 21 covers the first separated charge regions 20 and the third insulating layer. In this embodiment, the fourth insulating layer 21 extends over the first insulating layer 14. The insulating layer 21 is a thinning p, and the left (4) four memory regions and the third insulating layer 18 are disposed to cover the first separation charge so that the two first separated charges Storage area 20 series lil756.doc -22- 200812092 No contact. In this embodiment, the material of the third insulating layer 18 and the fourth insulating layer 21 is an oxide or other dielectric material. The conductive layer 23 is located on the fourth insulating layer 21, and the upper surface of the conductive layer 23 has a notch 23 1 . In this embodiment, the conductive layer 23 is made of polycrystalline germanium or amorphous germanium or a recrystallized germanium layer. The dielectric layers 28 are attached to the recesses 23 1 , respectively. In this embodiment, each of the second dielectric layers 28 is a horizontal oxide-nitride oxide structure comprising a fifth insulating layer and a second separated charge storage region 26 . And a sixth insulating layer 27. (4) The five insulation layers are located above the conductive layer 23. The second separated charge storage area % is located on the fifth, ''bab edge layer 24, and the second separated charge storage area % is used for storing electrons, and the material thereof is nitride, compound, or ruthenium or 35 compounds can provide materials that can be trapped. The sixth insulating layer 27 covers the second separated charge storage region 26 and the fifth insulating layer 24. It is to be noted that the sixth insulating layer 27 contacts the fifth insulating layer 24 to cover the second separated charge storage region % such that the second separated charge storage regions % are not in contact. In this embodiment, the material of the fifth insulating layer 24 and the sixth insulating layer is an oxide or other dielectric material. The first insulating layer 14, the second insulating layer 16, and the third insulating layer 18, the fourth insulating layer, the material of the fifth insulating layer 24 and the sixth insulating layer 27 may be the same or different. The closed pole 30 is located on the second dielectric layer 28, and relative to the In the present embodiment, the material of the drain 3 is polysilicon. The source 32 and the drain 33 are formed on the conductive layer 23 and are respectively located on the two sides of the gate 30. Human H1756.doc -23· 200812092 Referring again to Figure 16, in other applications, the open pole 30 further includes a gate thin layer 31' to protect the gate 30. The advantages of the present invention are as follows: The horizontal GNO structure (two-dielectric layer 22 or two second dielectric layers 28) as a storage area is effectively separated, so that it can resist mutual electrical interference or charge diffusion of each other. The meta-storage area can be selected separately, and the pass-through 乍吏 write erase is more than the local trap

The long level of Opmg) is more efficient and reliable. 3. Self-right

The function of the Qi, and the process steps are simple, and the mask is not separately developed by miniaturizing the components. 4. Self-aligning function, so the two storage areas W_S are cut out more traditionally by using the mask definition, and the two storage areas are more symmetrical and more reliable. 5. Expandability 'The number of memory bits for a single cell can be expanded using the same or other techniques, up to four or more. 6 conforms to the mature metal oxide semiconductor _S) manufacturing process, so it will not cause a burden on the industry. 7 The difference between the upper and lower frame structure can be adjusted to make the bit reading window larger. & is a double-layered gate structure' so that two channels can be created, so that the location where the ion freeing phenomenon occurs can be selected. However, the above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Therefore, those skilled in the art can devise modifications and variations of the embodiments described above without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 7 are views showing a manufacturing method of a dual-pole multi-bit S〇n〇S memory having horizontally shaped memory cells in accordance with the present invention and separated from each other in the vertical direction. 111756.doc •24- 200812092 [Description of main component symbols] I Substrate 4 Double-gate multi-element SONOS memory II with horizontally shaped memory cells and separated from each other in the vertical direction First Wafer Layer 12 Oxide Layer 13 Second Wafer layer 14 first insulating layer 15 recess 16 second insulating layer 17 bottom gate 18 third insulating layer 19 first electron storage layer 20 first separated charge storage region 21 fourth insulating layer 22 first dielectric layer 23 Conductive layer 24 fifth insulating layer 25 second electron storage layer 26 second separated charge storage region 27 sixth insulating layer 28 second dielectric layer 29 gate germanium layer 30 gate 111756.doc -25- 200812092 31 gate protection Layer 32 Source 33 Datum 231 Notch 291 Residual 矽

111756.doc 26

Claims (1)

200812092 X. Patent Application Range: 1. A method for manufacturing a dual gate multi-element SONOS memory device having horizontally shaped storage cells and separated from each other in a vertical direction, comprising the following steps: (a) providing a substrate, the substrate The first wafer layer, the first oxide layer and the second wafer layer are disposed between the first wafer layer and the second wafer layer; (b) forming a first insulation layer Layered on the first wafer layer; '(C) forming a recess on the substrate, the recess penetrating through the first insulating layer, the first wafer layer and the oxide layer, and exposing the second a wafer layer; (d) forming a second insulating layer on the sidewall of the recess and exposing the wafer layer; (e) growing the second wafer layer into the recess to form a a protruding bottom gate; (f) forming two separate first dielectric layers on a top surface of the bottom gate; V/(g) forming a conductive layer on the first dielectric layer, the conductive layer The upper surface has a notch; (h) two separate second dielectric layers are formed on the recess; (1) forming a gate A second dielectric layer; ⑴ and forming a source and a drain. The manufacturing method of claim 1, wherein the step (4) utilizes a mask to disambiguate the recess and the substrate is etched with active ions to form the recess. 3. The method of manufacturing the invention of claim 1, wherein each of the first dielectric layers comprises -111756.doc 200812092, a first separated charge storage region of the edge layer, and a fourth insulating layer, wherein the step (f) comprises: (f) opening a second insulating layer on the top surface of the bottom gate; () forming a first electronic storage layer on the first insulating layer and the third insulating layer; (f3) removing the first An electron storage layer to form two separate first separated charge storage regions and exposing the third insulating layer; and (f4) forming a fourth insulating layer in the first insulating layer, the first separated charge storage regions And the third insulating layer. 4. The manufacturing method according to the item 1 2 3, wherein the forming method in the step (fl) is a thermal oxidation method. The manufacturing method of the present invention, wherein the forming method in the steps (f2) and (f4) is a low pressure chemical vapor deposition (LPC VD). 6_ The manufacturing method of claim 3, wherein the removing method in the step (f3) is reactive ion etching. The manufacturing method of claim 3, wherein the material of the third insulating layer and the fourth insulating layer is an oxide or other dielectric material. 8. The method of claim 3, wherein the material of the first electron storage layer is selected from the group consisting of nitrides, aluminides, aluminum tellurides, and button compounds. 9. The manufacturing method of claim 1 is a selective doping growth method, wherein the growth method in the step (e) is that the second dielectric layer comprises one and a sixth insulating layer, 1 〇·, 4 a method of edge-making, each of which is a second insulating layer and a second separated charge storage region 3 H1756.doc 200812092, wherein the step (h) comprises: (hi) forming a fifth insulating layer on the conductive layer (h2) forming a second electron storage layer on the fifth insulating layer; (h3) partially removing the second electron storage layer to form two separated second-side charge storage regions, and exposing the first a fifth insulating layer; and (h4) forming a sixth insulating layer on the fifth insulating layer and the second separated charge storage regions. 11. The method of claim 10, wherein the forming method in the steps (hl), (h2), and (h4) is a low pressure chemical vapor deposition method. 12. The manufacturing method according to claim 1, wherein the removing method in the step (h3) is reactive ion etching. 13. The method of claim 1, wherein the material of the fifth insulating layer and the sixth insulating layer is an oxide or other dielectric material. 14. The method of claim 10, wherein the material of the second electron storage layer is selected from the group consisting of nitrides, aluminides, aluminum tellurides, and button compounds. 15. The method of claim 1, wherein the forming method in the steps (b), (d) and (g) is a low pressure chemical vapor deposition method. 16. The method of claim 1, wherein the step (1) comprises: (i1) forming a gate layer on the second dielectric layer and the conductive layer; (U) partially removing the gate electrode The layer is left in a relative position to the recess; and the residual stone is just grown by a selective crystal growth method to form the gate. The manufacturing method of claim 1, wherein the step (1) comprises: (j1) forming a gate protection layer on the gate; (j2) forming the source by ion implantation and the Bungee; and (j3) remove the gate protection layer. 18. A double-question multi-element SONOS memory having horizontally shaped memory cells separated from each other in a vertical direction, including a substrate, including a first wafer layer, an oxide layer, and a second wafer Floor And a recess, the oxide layer is interposed between the first wafer layer and the second wafer layer; a first insulating layer is located on the first wafer layer, and the recess of the substrate penetrates the a first insulating layer, the first wafer layer and the oxide layer; a second insulating layer on a sidewall of the recess of the substrate; a bottom gate protruding from the second wafer layer into the recess Two separate first dielectric layers are respectively located on the bottom gate; a conductive layer is located on the first dielectric layers, the upper surface of the conductive layer has a notch; and the two separated second layers The electric layer is respectively attached to the recess; a gate is located on the second dielectric layer, and the %/day 1 is opposite to the center of the recess; and the source and the pole are formed in the true zig The windshield conductive layers are located on two sides of the gate. 19. The memory of claim 18, wherein each of the whistle + β 甘三弟-dielectric layer comprises a third insulating layer on the bottom gate; a first separate charge storage region is located in the third insulating On the layer, the first 111756.doc -4- 200812092 separate charge storage area is used for storing electrons; and the first four insulation layer 'covers the stem and the other is covered with a separate charge storage area and The third insulating layer. 20. The memory of claim 19 is placed in the form of an oxide or other dielectric material of the second insulating layer and the fourth insulating layer. The body of the stomach has a body, wherein the material of the first separation charge storage region is selected from the group consisting of nitride, sulphate, sulphate and group. The moon is 18 members. The memory of the first insulating layer and the second insulating layer is an oxide or other dielectric material. 23: The memory of claim 18, wherein each of the second dielectric layers comprises: a fifth insulating layer over the conductive layer; a first knife away from the charge storage region, located on the fifth insulating layer, The second knife is away from the charge storage region for storing electrons; and the ", the edge layer, the second separated charge storage region and the fifth insulating layer. 24. The memory of claim 23, wherein the fifth insulating layer and the sixth insulating layer are made of an oxide or other dielectric material. 2 5. For example, the top of the 丄, C, and the memory of the second separated charge storage area are selected from the group consisting of a squirrel, a sulphate, an aluminide, and a sulphide. 26) The memory of the jg, 8 is requested, wherein the conductive layer and the material of the gate are selected from the group consisting of 客 曰 、, amorphous 矽 and recrystallized 矽 756 111756.doc 200812092 , The memory of the gate 27. The memory of claim 18 further includes a gate protection layer. 111756.doc