TW200809864A - Cycle count storage methods and systems - Google Patents

Abstract

A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.

Description

200809864 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to a non-volatile memory system and its operation. All patents, published patent applications and other materials cited in 1 jin of this application (4) are incorporated herein by reference for various purposes. [Prior Art] Many commercially available non-volatile memory products are used today, especially in the form of small form factor cards, which are formed in one or more: integrated circuits. On the wafer - flash EEpR 〇 M (electrically erasable and programmable only) array of 70 early. The memory controller (which is typically, but not necessarily located on the split integrated circuit die) interfaces - the host of the connected card can be removed and the operation of the memory array within the control. Such controllers generally include - microprocessing; some non-swinging seven! · Sheng Wei 5 buys § 己 体 (r〇m), a volatile random access memory (RAM) and / or a number of special circuits, such as when data is passed through the controller during data stylization and reading A special circuit for calculating an error correction code (ECC) from the data. Some commercially available cards are CompactFlashTM (four) card, multimedia card player C), secure digital (SD) card, smart media card, personal standard (P-standard) inventory bridge; I: 矣 _ _vh, & . Hosts include personal computers, notebooks, computers, personal digital assistants (PDAs), various data communication devices, digital camera cellular, portable audio players, car sound systems and classes.

Like type equipment. In addition to ^ 恃 恃 + every A 八 思 card only ^ solution, can be embedded in this type of memory system. Two general-purpose memory single-element array architectures have been commercially applied, namely, Saki and NAND. In a typical N〇R array, the memory cell is connected between the bit line source and the drain diffusion region of the phase 119630.doc 200809864, and the drain diffusion region extends in the row direction, wherein the gate system is controlled. Connect to the word line that extends along the cell column. An e-memory unit includes at least one storage element positioned over at least a portion of the cell channel region between the source and/or the pole. A stylized charge level on the storage element thus controls an operational characteristic of the unit, which can read the "Hai unit" by applying an appropriate voltage to the addressed memory unit. Examples of such units The use in the memory system and its method of manufacture are provided in the following U.S. Patent Nos. 5,070,032, 5,095,344, 5,313,421, 5,315,541, 5,343, G63, 5,661, 〇53 and 6,222,762. NAND arrays utilize more than two memories a string of cells (eg, 16 or 32) connected between one or more select transistors between individual bit lines and a reference potential to form a cell row. The word line spans a plurality of cells within the row By extending the remaining cells in the string so that a stream of current flows depends on the level of charge stored in the addressed cell, a separate cell in a row is read and acknowledged during the stylization. Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Patents 5,570,315, 5,774,397, 6,046,935, 6,456,528 and 6,522,58 As discussed in the patent cited above, the charge storage element of the current flash EEPROM array is the most common conductive floating gate, usually formed of a conductive doped cerium material. For flash EEPROM An alternative type of system uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. Such units are described in 319630.doc 200809864

Takaaki Nozaki et al., "LMb EEpR〇M with MONOS Memory Units for Semiconductor Disc Applications," IEEE Transactions on Solid State Circuits, Vol. 26, No. 4, April 1991, 497 至Page 501). In one consumption case, a three-layer dielectric system formed of tantalum oxide, tantalum nitride, and tantalum oxide (〇N〇) is sandwiched between a conductive control gate and a memory cell channel. Between the surfaces of the conductive substrates, the cells are programmed by injecting electrons from the cell channels into the nitride, in which the electrons are intercepted and

Stored in the -X limit area and erased by injecting the thermal hole into the nitride. A number of specific cell structures and arrays employing dielectric storage elements are described in U.S. Patent No. 6,925, filed on. Individual flash EEPROM single ~ " two people dry τ 疋 篁 篁 篁 电荷 ( ( ( ( ( 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷The charge of a memory is used to control the threshold voltage of its memory cell ("General Reference VT"), which is used as a basis for reading the storage state of the cell. The boundary voltage window is typically divided into a range, and each of the two or more storage states of the memory unit corresponds to a range. The ranges are separated by a guard band. The guard bands include a nominal sense level that allows for individual cell storage status to be determined. The storage bits are accurate and consistent. (3) The interference is offset due to interference in the zigzag, read or erase operation of adjacent or other memory cells, pages or blocks. Therefore, the controller calculates the error positive code (ECC) and stores it with the programmed host data, which is used during verification to verify the data and - when necessary, to a certain level Capital correction. Moreover, the offset charge level is at , p ^ r rn ^ ^ . 10 ^ makes it completely offset from the bound target and thus causes the reading of the fault, and can be restored from time to time 119630.doc 200809864 Back to the center of its status range. This procedure is described in U.S. Patent Nos. 5,532,962 and 5,9,9,449, which are incorporated herein by reference. A multi-state flash EEPROM structure and its operating system using a galvanic gate are described in U.S. Patent Nos. 5,043,940 and 5,172,338. A multi-state memory - selected portions of the cell array can also be operated in two states (binary) for various reasons as described in U.S. Patent Nos. 5,930,167 and 6,456,528. • The memory cells of a typical flash EEPR0M array are divided into discrete cell blocks that are erased together. That is, the block (erase block) is the minimum number of cells that can be erased at the same time by erasing the unit. Each erase block typically stores one or more data pages, which are the smallest units of stylization and reading, but can program or read multiple pages in parallel in different sub-arrays or planes. Each page is generally stored - or multiple data segments, and the segment size is defined by the host system. An exemplary segment follows a standard established for a disk drive, including 512-bit host data, plus a number of byte management information about the host data and/or its erased blocks. Such memory is generally configured with 16, 32 or more pages in each block, and each page stores one or more. [Segment host data. The host data can include data from the user's application running on the host, the user data of the application, and the data generated by the host in the management memory (such as FAT (File Configuration Table)) and directory data. * In order to increase the parallelism during the programming of the host data into and out of the memory array, the array is generally divided into sub-arrays (generally referred to as planes). The sub-arrays contain their own data. Storing the circuit with I to allow parallel operation so that the data of multiple segments can be simultaneously programmed to 119630.doc 200809864 to each of several or all planes or from each of several or all planes The plane reads data of multiple sections at the same time. An array on a single integrated circuit can be physically divided into a plurality of planes, or each plane can be formed by a separate one or more integrated circuit wafers. Examples of such memory implementations are described in U.S. Patent Nos. 5,798,968 and 5,89,192. In some memory systems, physical memory cells are also grouped into two or more regions. An area may be any divided subset of the physical memory or memory system, and a specific range of logical block addresses are mapped into the subset, for example, a memory capable of storing 64 million bytes of data The body system is divided into four areas, each of which stores 6 million bytes of data. Then, the logical block address range can be divided into four groups, and a group is assigned to the erase block of the parent areas of the four areas. In a typical implementation, the logical block addresses are limited such that data for each logical block address is never written to the outside of a single physical area to which the logical block addresses are mapped. . In a memory cell array divided into a plurality of planes (sub-arrays) each having its own address, privacy, and read circuitry, each region preferably includes erased blocks from multiple planes. Generally, it is the same as the number of erase blocks from each plane. The area is mainly used to simplify address management such as logic to entity translation, resulting in smaller translation tables, less RAM memory required to save the tables, and faster access times for the current active area of the addressed memory. However, due to its limited nature, the level of wear and tear may not be optimal. To further manage memory efficiently, the erase block can be linked at a time of 119630.doc 200809864 to form a virtual block or metablock. That is, each metablock is defined to include an erase block from each plane. The use of metablocks is described in U.S. Patent No. 6,763,424. The metablock is identified as a destination for programming and reading data by a host logical block address. All erase blocks of the same 'one dollar block' are erased together. A controller in a memory system that operates with such larger blocks and/or metablocks performs several functions, including a logical block address (lba) received from a host.

The transition between the physical block number (pBN) within the array of memory cells. Individual pages within the blocks are typically identified by offsets within the block address. Address translation often involves the use of a logical block number (LBN) and an intermediate term of a logical page. The data stored in the unary block is updated from time to time. The likelihood of an update in a metablock increases as the metablock data capacity increases. The update section of the unary block is usually written as a separate meta-block. As part of the same stylized operation, the invariant sections are usually copied from the original metablock to the new metablock. Alternatively, the invariant data may remain in the original metablock: f to be later merged with the updated data again in a single metablock - all data in the A block will be changed due to updates and duplications. The 1H 7L block is placed in a column for erasure. Ding! ! A wipe out block undergoes a continuous stylization and erasing cycle, which experiences the wear of the month b t衾t 4 ζ丨古 & ρ Μ Λ, , 1 • ghost failure. In some cases, a control port is controlled by maintaining a heat count to control the wear of the wood, which indicates the number of erase cycles of a block. a few ^ , ^ because a flash memory block must be available

It is erased before it is privateized, # ^ ^ J The number of erase operations experienced by _ H9630.doc -10- 200809864 is equal to the number of stylized operations experienced. The number of erase operations experienced is generally a preferred measure of the wear experienced by the block. In some cases, the controller uses this thermal count for wear leveling purposes to try to ensure that blocks within a memory array wear at approximately the same rate. However, maintaining a thermal count for all blocks of a memory array can take up valuable 2 controller resources. In particular, the burden of maintaining and updating the heat count may be significant in the case where the memory array contains a large number of blocks. and,

Communication associated with monitoring and updating the hot count can use some communication capacity between a controller and a memory chip, thereby slowing down other communications and reducing access time. [Inventive content] 1 A dedicated circuit on the same wafer or multiple wafers of the bulk array allows the thermal count to be maintained independently of the controller. This point makes the = function, which improves performance. • By using on-wafer circuits:

Wave, "maintaining heat count in raw memory, reducing the risk due to the number of breaks. K inside (four) memory array intrinsic - block - management data area, to the temporary "received-erase command for the block, The thermal count is complex: the second, the heat count is combined with one or more threshold values, and the action (if any) is taken. Such actions may include knowing the use of blocks or modifying the power or time period used by certain block operations. —I + block time 埶 count.荽 - • 5, erase the block and update the F 妁 person updated hot count write back to the management data area of the block 0 if disabled 兮F said, a few <& Duanbei Chai Block, you can select another block and mark the deactivated area 119630.doc • 11 - 200809864 In the memory using multi-level storage in p-binary format to store more storage density, the machine data system With multiple quasi-thermal counts, even if the main value in the same page destroys the risk, it is not stored. This is provided at this point—especially for lower heat meters. In the case of a multi-plane for updating its individual materials, a dedicated circuit is provided for each plane, and (on the wafer) is implemented. Not requiring controller resources and having - high reliability [Embodiment]

The block diagram of Figure 1 illustrates a gentleman & DD r see one of the various aspects of the present invention. The memory cell array 1 including the matrix matrix b moment I is configured by the row control system, the column control circuit 3, the c source circuit, and the c-well control circuit 5 to control. In this example, the memory cell array I is incapable of A # Μ 幻幻1, which is described above in the prior art and incorporated herein by reference. Other types of non-volatile memory can also be used. The row control circuit 2 is connected to the bit 7G line (BL) of the memory cell array for reading data stored in the memory cell for determining a state of the memory cell during a stylized operation, and Used to control the potential level of the bit line (BL) to facilitate stylization or prohibit stylization. The column control circuit 3 is connected to the word line (WL) to select one of the word lines (WL), applies a read voltage, and combines the bit line potential level controlled by the line control circuit 2 to apply the stylized voltage. And is applied to the -p-type region (cell?) of the memory sheet 119630.doc 12 200809864 疋, which is controlled by the electrode control circuit 4, to be connected to the body J: erase the electric dust. c source line. The c-ρ well control circuit 5 controls the unit c_p well. The shared source of the early 兀 远 远 远 远 远 n n n n n n n 读取 读取 读取 读取 读取 读取 读取 读取 读取

line. To be stored in the ":: output circuit 6 and turn to the external I / O 蝻 there is an I / O line in the 4 # memory unit and input to the audio 粑 private shell material through the external r month] into the Bessie Input/rounding circuits 6, 2. These external special α(4) are connected to the temporary storage crying of the type of control circuit control ^ > Technical state 9 includes various body (RAM) l〇. The memory is used to control the command 7 of the flash memory device, and the command circuit 7 is connected to the external control line connected to the controller 9: the incoming command circuit is connected to the flash memory. To the state machine 8, J; the smuggling line to the squad, ~ turn in the command system transmission system 4 North J order control circuit 2, column control circuit 3, · pole control 4, cp well control electric can be in and 枓Input 7 output buffer δ. State machine 8 叮 Output flash memory PASS/FAIL 〇 枓 枓 枓 READY/BUSY or controller 9 is connected or can be connected to a host system, such as a person =, - Digital camera or personal digital assistant. That is, the host initiates a life y, such as storing or reading data to the memory array 1 Or reading or receiving data from the data cutter. The controller 9 converts such commands into command commands that can be interpreted and executed by the command circuit 7. Controlling the crying 9 generally also includes buffer memory. To write or read host data into the memory array. - 曲 and 丨^ α π γ /, 1 memory 糸 包括 system includes an integrated circuit chip 119630.doc • 13 · 200809864 2 which includes the controller .9; and one or more integrated circuit chips i]B, each 匕3 § 体 体 array and associated control, input / output and state machine circuits. It is possible to a system of memory array Integrate with the controller circuit on one or more integrated circuit chips. • The system can be part of the host system, or the /, U can be included in the 5 memory card, The memory card can be removably inserted into a matching slot of a host system. Such a card can include an entire memory system Φ, a charge or a disturbance, and an associated peripheral circuit can be provided in the separate card. A number of card cases are described, for example, in US Patent Case 5 , 887, 145, the entire contents of which is expressly incorporated herein by reference. A popular flash EPROM architecture utilizes a nand array in which a large number of memory cell strings are passed between individual bit lines and a reference potential. Or a plurality of selection transistors are connected. One part of the nand memory cell array 1 of the figure is shown in plan view in Fig. 2A. blo_BL4 (where BL1-BL3 is also labeled as ~6) represents the global vertical metal bit line. (not shown) the diffusion call is % line connected. Although four floating gate memory memories 2' are displayed in each string, the individual strings generally include 16, 32 or more memories in one row. Store components such as floating gates. The sub-element labeled WL〇-WL3 (labeled p2 in Figure 2B (-section of line A-A of Figure 2A) and the string selection lines SGD and SGS extend across the plurality of strings on the column of floating gates. However, for selecting transistors 40 and 41, the control gate and the floating gate (not shown) can be electrically connected. The control gate lines are generally formed as a self-aligned stack on the floating gates and are electrically coupled to each other through an intermediate dielectric layer 19, as shown in FIG. The top and bottom of the string are generally connected to the bit line and ugly by using a floating 119630.doc •14-200809864 dynamic gate material (P1) as the transistor of the active gate driven by the electric power. Source line. This capacitance-to-fuse between the floating gate and the control idler allows the voltage of the floating idler to be increased by increasing the voltage at which it is controlled. A unit in the line is placed on its individual word line by placing a relative age 祁対#乂 voltage

Placing a relatively low voltage in the -selected word line to turn on the remaining cells of the string (four) so that the m flowing through each string depends only on the level of charge stored in the addressed unit below the selected word line, During the stylization, the m-like strings for the A-quantity are read and verified in parallel to read the charge level state in parallel along a column of floating gates. Figure 3A shows a circuit diagram of a NAND string 50 having floating gate memory cells MO, M1, M2 ... Μη. The memory cell medulla, M1, M2... Μη is controlled by the control gate formed by the word lines WL〇, WL1.·· WLn. In addition, a select gate (SGS) controls select transistor S1, which connects NAND string 50 to a source connection 54. Another select gate (SGD) control selects transistor S2, and select transistor S2 connects NAND string 50 to a drain connection 56. The number of cells within the NAND string 50 can be 4, as shown in Figure 2B' or can be some other number, such as 8, 16, 32 or more. Figure 3B is a circuit diagram showing how a series of blocks can be connected to form a memory array. NAND strings 50a, 50b ... 50c are connected together to form a block. NAND strings 50a, 50b. The strings of .cc have the same structure as the NAND string 50 of Figure 3A. The NAND strings 50a, 50b ... 50c can include a number of strings. In one example, a block 119630.doc in a NAND memory. 15· 200809864 can contain 16,384 strings. NAND string 50a, 5〇b··· 5〇c share common word line WLO, WL1··· WLn and select line SGSSASG. nAN]D string 50a, 5 0b.·· 5 0c is erased together, thus forming a block. In addition, the nand string 50a, 5 0b··· 5〇c co-dry a common source line. The bit line is connected to the NAND string of different blocks. The data is generally programmed in a NAND array in units of pages. In a NAND array, a page can be formed by a single word line connected memory cells. The data is generally continuous, page by page. Stylize in a block, select a word line at a time. The bit line has a voltage that does not want to program the data. In some memories In the memory, the data stored in the memory unit of a word line can be regarded as the data on the previous page and the data on the next page, corresponding to the specified two. The four voltage ranges of one bit. In some memories, the management data is stored in the same block as the host data. One part of a block can be dedicated to storing management data. Therefore, for example, ναν〇 string 5〇 The a and 5 〇 b can store the host data, and the NAND string 50c stores the management data. The size of the individual pages of FIG. 3B can vary, but a commercial form includes one or more segments of data in one page. The contents of the pages of the two sections 153 and US are as shown in Fig. 4. The 纟 section has management data. In other fe cases, more than @ sections can be stored in one page. The host data (5) is generally 512 bits. In addition to the host material 157, there is a management data 159, which may include ecc data calculated from the host data, associated with the segment data, and/or erased blocks in which the region & Parameters and 仗4, etc. *number w different -ECC and any Management information that he may include. In some examples, the management data for the host material of a section is 119630.doc -16- 200809864: the child is in a physical location adjacent to the host material. In other examples The management data for one page is stored together in one of the management areas of the page. The management data may include erasing the number of stylized/erasing cycles experienced by the block, and the amount is controlled by The device is updated after each cycle or a certain number of 'eyes' cycles. But use this number of experiences in the - wear level, '! % method, by the controller to regularly remap the logical block address to a different physical block address 'to make all erase blocks The amount of use (wear) is uniformized. The management profile may also include an indication of the location values of the storage states (referred to as "rotation") assigned to each of the memory cells. This also has a beneficial effect on wear leveling. An indication or status may also be included in the management data. An indication of the voltage level used to program and/or erase the erase block may also be stored in the management data, which may vary with the number of cycles experienced by the erased block and other factors. Update. Other examples of the management data include the identification of one of the damaged cells in the erase block, the logical address of the data mapped to the physical block, and any alternative erased block in the event that the primary erased block is damaged. Address. The specific combination of parameters stored in the management data used in any memory (4) will vary depending on the design. In general, the reference frames are accessed by the controller and updated by the controller when needed. Figure 5 shows a erase block in the array of the 财 财. The erase area, (ie, the minimum erase unit) contains four f()_3, and each page is the smallest stylized single 7〇. - or the data of the multiple host segments is stored in each page along with the management data (including 119630.doc -17- 200809864 at least ECC calculated from the data in the segment) and the data segment of Figure 4 can be used. Form. Each page of the erase block is formed by a sub-turn line extending from a horizontal % NAND string and the string of the erase block shares the source and drain select lines.

Another multi-segment erase block configuration is illustrated in Figure 6A. Here, the entire memory unitary array is physically divided into two or more planes, indicating four planes 0-3. Each-plane-memory unit sub-array has its own data register, sense amplifier, address decoder, and the like so that the month b can be reported to operate independently of other planes. All of the planes may be provided on a single-integrated circuit or on multiple devices, and the examples are used to form each plane by - or a plurality of different integrated circuit devices. Each erase block in the exemplary system of FIG. 6 includes 16 pages ρ 〇 · ρ ΐ 5, each page has one, more host data sectors and one of some management data capacity 0 Figure 6 Β The plane 〇-3 of 6Α has a dedicated column control circuit and a dedicated row control circuit for each plane. The _single_chip can have a plurality of planes of an array of memory layers thereon. In addition, a plurality of wafers can be connected to form an array. A single controller can be used to process the batting in all planes of the memory array. In general, the control is located on a separate wafer. Another memory configuration is shown in FIG. Each plane contains a large number of erase blocks for the parallelism of the operation, and the erase blocks in different planes are logically linked to form a metablock. Such metablocks are shown in Figure 7. The metablocks can be remotely addressed and the memory controller assigns and tracks the blocks that form the individual blocks. The host system provides 119630.doc -18-200809864 for information in a stream. This sector stream is divided into logical blocks. Here, the shout block is a logical data unit that contains the same number of data segments as the data area in the 7L block of the memory array. The memory controls a record that maintains the location where each logical block is stored. For example, such a logical block 61 of FIG. 7 is identified by a logical block address (LBA), which is mapped by the controller to form the metablock. The physical block number (PBN) of the block. All blocks of the metablock are wiped together

Except, and the page system from each block is generally stylized and read at the same time. The pages of different planes that are programmed or read together in this way can be regarded as forming an unary page. FIG. 8 is an example of a block 8 that is not in the plane N, and has a host data area 8 for storing host data. i and one are used to store management data ^ management data area 83. The host data area 81 can be used to store data transmitted by the host, including user data and data generated by the host for managing the memory, such as a file configuration table (FAT) section. The host data area is formed by a group of rows having a first group of row control circuits 85 > the lyrics area 83 is formed by a second group of rows having first, and row control Circuit 87. The number of lines provided for managing data depends on the management to be stored. In addition, redundant rows can be provided to replace damaged rows when needed. The row control circuits 85, 87 include circuitry for determining the state of a memory cell in the memory array in one bit: the control circuit further includes circuitry for programming to memory early The state of the memory is used to supply voltage to the bit line. In general, the management tribute area 83 is not accessed by the host. The controller accesses the management data area 81 119630.doc -19- 200809864 and stores the data used by the controller for managing data in the memory array. Figure 8 shows a compare and increment circuit 89 connected to one of the registers of the management line control circuit 87 and to one of the registers 88. In one embodiment, the management row control circuit 87 reads a thermal count from the management data area 83 of the block 80 and stores the hot count value in the scratchpad 抹 before erasing the block 80. Next, the compare and increment circuit 89 performs a - comparison between the heat count value and one or more predetermined values and determines based on the comparison. In the example n, the heat count value can be compared with a predetermined value to determine the heat meter. Indicates whether the number of erase operations exceeds a critical number indicating that the block is under or near a wear condition. In an example, the threshold is 100,000' but other higher or lower values may also be used. When the number of erase operations exceeds this threshold, block 80 can be deactivated and indicated that it is no longer used to store data. If the number of erase operations does not exceed the critical number, the compare and increment circuit 89 increments the heat count value in the register 88. The block 80 is erased and the incremented heat count value is then written back to the management data area 83 of the block 80 by the management line control circuit 87. In the example, register 88 holds two bits of 7L data 'sufficient for a thermal count value up to the critical number. In this case, the hot count portion of the management data area also holds three bytes. A different system than a particular prior system that maintains a heat count value. This particular embodiment does not require the controller to manage the values for different blocks. Instead, the thermal count value is maintained by dedicated circuitry that includes the flat circuit of the block. This reduces the control benefit and the burden on the communication line between the peripheral circuitry of the memory and the controller. This allows the controller to perform other functions and operate faster. In addition, using the on-wafer circuit to suppress the heat, the heat count is reduced by a heat count, due to an unpredictable break. The risk of loss, which may occur in a volatile state in the volatile RAM within the # _ ^ + gate dimension heat count. When a block exceeds the threshold, the σ f匕 state means that this is not the point so that the control does not attempt to access the block after Ik. π 十% _ Combined, the routine can be independent of the control of the _ rice. Φ In a specific embodiment, the counting system is initialized to a non-zero value. This can be done at the factory, for example as part of a test and configuration procedure after U, body manufacturing. For example, you can initially set a bit to , , ". The 埶 counting system is later read as all "〇, ... ^主, 乂王邛1, then this indicates an error. Electric day ^^ is in the privateization of the heat count to the management data area during the break in a specific In an embodiment, the 埶舛..., juice value may compare one or more predetermined values indicating one or more wear levels less than a wear strip condition. In the grass memory, the memory list亓夕壮— The characteristics of the early singularity may change with the wear and tear. In such memory, the aging female car is advantageous, and the specific operating conditions are changed as the recording unit is worn out. a first set of operating conditions may select to use the block & 11 block to experience less than the -th critical number of erase operations. The block may have experienced more erases than the first & Operation but less than the second critical number of erase operations, μ k release two sets of operation # pieces. In this block has been experienced more than /, 斤一, brother gtm boundary number of erase operations but less than a When the triple critical number of the erased ^ 1 |a is erased, the _ condition can be selected. The conditions of the work and the door group are used for different wear levels 119630.doc *21 . 200809864. The operating conditions modified in this way include stylized electric lee, program «rush number, stylized pulse Duration, pulse-by-pulse stylization; 昼 increment, self-pressurized dust during stylization, erase power, assignment of threshold voltage to memory state, guard band size, program timeout period, erase And the operation, the number of Eccf materials in each block, the frequency of the operation 2, the standby, and any other operating conditions. The operating conditions can be changed independently of the controller. For example, the comparison and increment circuit can To: 2 command the circuit to transmit a signal to access the memory (4) (4), the command circuit causing a state machine to use different operating conditions. According to one embodiment of the invention, stored within a block: :: A different format than the one stored in the host data area of the block can be stored in the host area == Some data in the data area can be stored in the coffee data that allows correction errors. One For answering the number of times 11, there is such ECC information: for example:: The data is generally not allowed to be used in the data storage of the bit 毁 / yi 任何 任何 任何 任何 任何 任何 任何 任何 任何 任何 任何 任何 任何 任何 任何This (four) material, more favorable can be used - the ECC data host material f or management data is more secure to program. In a lend, η - / ' is not stored in a block of management data == count To calculate any coffee, on the contrary, the thermal count is stored in a binary format to increase reliability. In a specific embodiment, f M _ ow L, 丨Y ^ format incoming material. In (4) multi-digit order 7^ It is specified by a different threshold voltage range of four four or more different logic states. 119630.doc -22- 200809864 Figure 9A shows an example in which four critical electrical dust (Vt) ranges are assigned to four evils 1, 11, 10, 00. The 〇1 state corresponds to the _erase stylized state and may include a negative critical 遂 range. In other examples, the logic state can be represented by different critical electrical ranges. In some examples, the assignment of the range to the logic state varies at different times = the threshold voltage range that should be in the logic state may be discontinuous with the guard band provided between them to reduce the interference. The opportunity to read the electric power, so that the state of memory, the state of the state changes to another state. In other examples, the logic of the sorrow can be expressed by different threshold voltages. The data is stored in the host data area, and a high storage density is expected in the main: beaker area and the error can be corrected by ecc. Figure 9B shows two of the two logical states of the memory unit in the management data area. The threshold voltage range. The logic states correspond to the two logic states of Figure 9A having the largest electrical error. Thus, the threshold voltage ranges assigned to the logic state lmi〇 in the plan become in the example of the figure - Part of the larger guard band and only the logic states 〇1 and 〇〇 at the same time "01" and "〇〇" symbols are still used in Figure 9B for comparing Figure 9A, only one bit is stored and the states can be regarded as Μ" And ',〇 ,,status). This format allows for stylization at a very low risk. A memory cell having a threshold voltage corresponding to state 〇1 in Figure 9 is unlikely to experience an interference that causes it to have a pair of threshold voltages at logic state 00. Stylization can be done more quickly with only two stylized singularities. Stylized-single-bit data in the unit with a larger guarantee can be regarded as "flag stylized" because it is particularly suitable for stylized flags. According to one embodiment of the present invention 119630.doc -23- 200809864, the specific embodiment, the indication [stored in the stylized mode g.; number one... in the flag basin he manages the data of the data machine (and in some cases, 4 , for example, ECC data) is stored in MLC mode. This is the invention of the invention - the specific circuit on the chip can be used - UiU command to erase - block. The controller transmits - erases the ^ command to identify the block to be erased: pxp 7 is received by the on-chip circuit, as the controller takes over all the data in the block. . Use the thermal count of your 兮, ', (4) block to copy 1〇3 from the block where it is stored = and write it to a scratchpad on the same wafer. The heat count is compared to the TM6TM threshold. The threshold value can be set to a number in the factory, 苴:! According to the number of erase operations and the experimental data related to the failure of a block, Γ=Γ Generally, it can be set in the way of work and waste: Hunting by making (four) silk or anti-(four)'. If the heat count exceeds the critical ancestor 07, the block is generally marked as unavailable for library storage. An indication can be sent to the eraser operation of the #, _ ρ on the block: and the block is not available for storing data. The controller can record that the two blocks are not available, so that they no longer attempt to access the block. In general, the controller will select another block at this stage and continue to program. In the case where the failure zone = is parallelized with other blocks in other planes (for example, as part of a unitary block, the brother's knife), the failed block is replaced by the same in-plane block. If all the blocks that are being stylized in parallel are missing (4), the stylized operation can be abandoned. If the heat count value is less than (four) value ', then the block (including a management data area 119630.doc -24-200809864 field containing the heat count) is erased 109 and the heat count is updated in the register Iu to reflect the extra erase operation. In a particular embodiment, the thermal count is only incremented - to reflect - an additional erase operation. In another embodiment, the heat count is not incremented each time an erase operation is performed. Instead, the random number generator is used to decide whether to increment the hot count. In this way, the thermal count is incremented infrequently and the frequency is dependent on the random number generator in a predetermined manner. This allows for less space to be stored within the block - hot count. The extent to which the heat count value is updated with such a random number generator is provided in U.S. Patent No. 6,345, GG1. Once the hot count value is updated in the scratchpad, the updated hot count value is written back to the administrative data area of the erased block 113. Thus the 'block' contains a heat count that reflects the erase operation that has been performed. This thermal count is maintained independently of the controller. Figure 11 shows a flow chart of another example of updating the hot count during erasing a block and using the heat count to administer the block. The controller 35 transmits an erase command that identifies the block to be erased. This command is connected by the circuit on the chip to 121. The thermal count for the block is copied 123 from the management f-region of the block in which it is stored and written into the phase 3 wafer. On the same wafer, in a comparison circuit, the heat count is compared to !25 - a predetermined threshold. If the thermal count value is greater than the threshold, then modification 127 is used for the operating conditions of the block such that the block operates from a first mode to operate in a second mode. Modifying the operating conditions may involve modifying one or more voltages for the block operation or modifying one or more timeout periods or modifying other parameters for managing the block. In this example, the 计数 count is compared to a single threshold such that the preset operating conditions are used when the thermal count is less than the critical 119630.doc -25· 200809864. In the application where the erase count exceeds the threshold - the second set of operating conditions. In other example f, the 孰 count = two or more thresholds to determine which condition should be used for three or more operations. Erasing the block 129 and updating (3) the trick value in the scratchpad/arguing that the operating conditions have been modified. Then, the number is programmed back to the f" of the block,

e Li Beike £ 133. The procedure shown in Figure n can be implemented on the wafer without cloud I" and ... to reduce the control benefits on the controller to perform other operations more quickly. The modified operating conditions can be worse than the perimeter of the same plane as the block. The circuit is completed. The specific embodiments described in =0 and η are simultaneously provided by the circuit machine provided on the wafer, the 各 千 千 ' ' ' ' ' ' ' ' ' ' ' ' 各 各 各 各 各 各 主MPA q β "Ribebe region and each plane has a - register and a comparison and increment circuit, the lightning circuit allows each plane to independently perform the heat count more ^ 彳 V Lu can be independent of the controller to implement heat The update operation is counted, but the controller can use such a hot count value. For example, the controller may use the "on-the-spot, quasi-holding thermal count value on the wafer for wear leveling purposes. The various embodiments described above include providing specific knowledge beyond the prior art' but generally need to maintain such features. Ability. This can be achieved for backward compatibility purposes or for some use, including - temporary storage... comparison: two =. In a specific example _ ^ ^ ratio #乂 and increment circuit thermal counting circuit Actuated in the -first mode and deactivated in the second mode. In the other mode, the thermal count is maintained by the circuits, but is not used to disable the _: block or modify the block. Choose what?" Conditions. Such heat counts can be used for testing purposes, failure analysis, or other purposes. H9630.doc -26- 200809864 The present invention has been described with respect to various exemplary embodiments. It is understood that the present invention is entitled to be protected within the scope of the appended claims. [Simplified Schematic] Figure 1 shows a memory cell unit without a memory unit | A • A trivial array and a memory system of a controller; Figure 2A illustrates the organization of the NAND memory cell array of Figure 1. 2B shows a cross section of one of the NAND memory cells of the figure; FIG. 3A shows a string of "solid memory cells M〇_Mn"; FIG. 3B shows that a block is formed by including One of the memory arrays of the NAND string 5〇a, 5〇b ..5〇c is one of the memory arrays; FIG. 4 shows an example of one of the host data and management data including two sections; Figure 5 shows an erase block comprising one of four pages; Figure 6A shows a memory array having four planes, each plane having a plurality of blocks, including erase block 0 and erase block 1, plane 1 The erase block 1 4 includes pages P0-P15; ® B , , , and the member of Figure 6 a έ έ 体 array, each plane has a dedicated column control circuit and row control circuit; Figure 7 is not in the stylized unitary Example of parallel stylized plane ^plane 3 inner block during block; Figure 8 shows a memory array and peripheral power , which includes a column and row control circuit, a register and a comparison and increment circuit; H9630.doc -27- 200809864 Figure 9A shows a representation of the four solids; the knots & λα ^ ^ 1U The four temporary voltage ranges of the memory unit; % ” • Two critical figures of a memory cell in the state of the picture 9B show two voltage ranges; Figure 10 shows the number of T used in the heat count ^ over one g In the case of the boundary value, one of the flow blocks of the block-block erasing operation is disabled; FIG. 11 shows one of the operating conditions for modifying the zone 在 in the case of one of the heat thresholds ^^^^, σ : & ϋ ^ . [Main component symbol description] 1 Lu Yiyi body unit array 2 row control circuit 3 column control circuit 4 c source control circuit 5 CP well control circuit 6 data input / output circuit 7 command circuit 8 state machine 9 Controller 10 Volatile Random Access Memory 11A Integrated Circuit Wafer 11B Integrated Circuit Wafer 12 Not described in the text 14 Not described in the text 16 Not described in the text 119630.doc '28. 200809864 Reference 19 Intermediate dielectric layer 40 Selective transistor 41 Select electro-crystal Body 50 NAND string 50a NAND string 50b NAND string 50c NAND string 54 source connection 56 drain connection 61 logic block 80 block 81 host tributary area 83 management data area 85 first group row control circuit 87 second group row control Circuit 88 Register 89 Comparison and Increment Circuit 153 Section 155 Section 157 Section 159 Management Data BL Bit Line BLO Bit Line BL1 Bit Line 119630.doc -29- 200809864

BL2 bit line BL3 bit line BL4 bit line MO floating gate memory 'body unit Ml floating gate memory unit M2 floating gate memory unit Μn floating gate memory unit PI floating gate material P2 word line SI select gate (SGS) control select transistor S2 select gate (SGD) control select transistor SGD string select line SGS string select line WL word line WLO word line WL1 word line WL2 word line WL3 word line WLn word line 119630.doc -30-

Claims (1)

200809864 X. Patent Application Range: 1. A method for managing an erase block of a NAND flash memory array formed on a first substrate, the array being controlled by a controller on a second substrate, The NAND flash memory array has a minimum erase unit of one block, and one block includes two or more pages. The method includes: / reading a heat count value from a block, the heat count value Indicates the number of times the block has been erased; storing the heat count in a register located on the first substrate; comparing the heat count value with a predetermined value; and right the heat count value does not exceed the predetermined value, And erasing all the data in the block, incrementing the hot count value and writing the incremental hot count value to the block; and if the hot count value exceeds the predetermined value, recording the block is not used for subsequent Data storage. 2. The method of claim 1, wherein the heat count value is stored in a memory unit in which each memory unit stores one bit and the host data stored in the block is stored in each memory unit. Store two or more bits in the brother memory unit. 3. The method of the requester, wherein the register is initialized to a non-zero number. 4. The method of claim 1, wherein the block forms one of a plurality of blocks in a plane and the register is dedicated to the plane, and the additional register is used for the additional plane. 119630.doc 200809864 5. The method of claim </ RTI> wherein the plane, the additional planes, the temporary benefits, and the additional registers are attached to the first substrate. The method of claim 1, wherein an indication is communicated to the controller if the thermal count exceeds the predetermined value. • The method of claim 1, wherein the count value is read from one of the blocks and the incremental heat count value is written to the management data area of the block. • 8. A method of using a thermal count in a flash memory system, the flash memory system comprising a NAND flash memory array on a first substrate and a memory on a second substrate a body controller, the NAND flash memory array having a minimum erasing unit of a block, the hot count indicating the number of times the block has been erased, and a block containing two or more pages of one page A minimum stylized unit, the method comprising: «5 hai block reading the hot count; comparing the heat count with a pre-φ value in a comparison circuit on the first substrate; and the right heat count exceeds The predetermined value changes the operation bar of one of the blocks. 9. The method of claim 8, wherein changing the operating condition results in deactivating the block. 10. The method of claim 8, wherein changing the operating condition results in a change in the at least one voltage used to access the block. The method of claim 10, wherein the at least one voltage comprises at least one of a stylized voltage and an erase voltage. 119630.doc 200809864's two:=methods' further includes comparing the heat count with an additional set of operating conditions. Bu pre (the value of tons to choose i3. =;: 8 method 'where the heat count is - binary form: one of the remote block management data area and the host data system is stored using μ - two standard In the host data area of the block. • Array = Yes: The minimum erase unit is a block - the flash memory is outside, and the ^5 memory array has at least one first plane 盥 = two planes a plurality of planes, each plane of the plurality of planes having /, its own column and row decoder circuit, the method comprising: six f by copying the -first heat count value from the first block to - the first Temporary dimension #第_热数 is used in the first plane - the first block: increment the first heat count value, erase the first block and write the incremental heat count value to the a first block; comparing the first heat count value with a threshold value and operating the first block in the -first mode if the first threshold value is less than the threshold value - operating the first block in a second mode if the thermal count value is greater than the threshold value; The second heat count value is copied from the second block to a second temporary store to maintain - the second heat count is used for the second block in the second plane: incrementing the second heat count value, erasing The second block writes the incremented second heat count value to the second block, and compares the second heat count value with the threshold value, and the second heat count value is less than the threshold value In the case of operating in the _first mode, the second 119630.doc 200809864 == operating the second block in a second mode if the second hot count value is greater than the threshold. 1 5 · For example, the method of item 14 is to control the mouth of the pot. The number of planes in the basin is controlled by a single control. 16. = ί The method of item 15, wherein the plurality of planes are in — or a plurality of memory slabs and the controller is on a separate controller chip. 17.2. The method of claim 16, wherein the comparing the first heat count value with -1 and the comparison (4): the heat count value and the The threshold is performed by circuitry on the memory chip. 18. The party of claim 17 In the case of the e-diet, the first block is used and the 5th block is transmitted to the controller by the 4th~^^. 19· Platinum item 14 The method, the eclipse of the eldest brother - the extreme type, the first block. ^ brother - mode 'the first block uses a brother two sets of operating voltage. 20 · If the method of claim 14, wherein The &lt; body array is a NAND array! J. 21^^ Item 14 'where the flash memory array - block or more pages and the pages of the two or more pages Data comprising two or more segments. 22. A flash memory array comprising: and a complex plane: each of the plurality of planes has a dedicated column and lamp decoder circuit; Each plane of the plurality of planes has a-comparison circuit; a temporary ", - increment circuit and a 119630.doc 200809864 °H register receives a number of times the block has been erased from a block; the hot count value of the heat count value Indicating the incrementing circuit capacity; and echoing one of the blocks to increment the comparison circuit within the register Compared with the contents of the register and a predetermined value. 23. The memory array of claim 22, wherein the plurality of planes are located at one The plurality of memory chips and the registers, the incrementing circuit, and the comparison circuit are also located on the one or more memory chips. 24. The memory array of claim 23, further comprising a controller on a controller wafer in communication with the one or more memory chips. 25. The memory array of claim 22, wherein the register is initialized to a non-zero number. 26. The memory array of claim 22, wherein an incremental hot count value is written back to the block. 27. The memory array of claim 22, wherein the host data stored in the block is stored in two or more bits per memory unit and the thermal count is stored in only one bit per cell . 28. The memory array of claim 22, wherein the block comprises a host data area and a management data area, the host count system being stored in the management data area. 29. The memory array of claim 22, wherein the comparison circuit is responsive to provide a signal indicating that the block is no longer used. 3. The memory array of claim 22, wherein the comparison circuit is responsive to providing a signal that causes one or more of the operating blocks to be modified. I19630.doc 200809864 pieces 0 3 1 · The page is a private unit and a block as a NAND flash memory array for erasing units, a block of NAND flash memory, an array containing ·· containing two or more pages, the ^, having a host a tributary area and a management data area, the management data includes a heat count, which records the number of times the block has been erased, and the block is located on a first substrate; a comparison circuit that compares the thermal count with a threshold value, the comparison circuit being on the first substrate; and a controller on the first substrate that manages data storage within the memory array. 32. The request item 31iNAND flash memory array, wherein the comparison circuit is coupled to a first plane of the memory array, the additional plane of the memory array being coupled to an additional comparison circuit on the first substrate. 33. The NAND flash memory of claim 31, further comprising a register on the first substrate that maintains the thermal count for comparing the threshold, the hot count being incremented within the register . 34. The NAND flash memory of claim 31, wherein the host data area comprises host data stored in two or more bits of a parent memory unit and the management data area comprises only one memory unit per memory unit The data stored in the bit. 35. The NAND flash memory of claim 31, wherein the comparison circuit is responsive to comparing the thermal count to the threshold to transmit a signal indicative of a change in one of the at least one operating condition of the block. 119630.doc