TW200809691A - A graphics processing unit and a method of processing border color information - Google Patents

Abstract

Systems and methods for border color handling in a graphics processing unit are disclosed. In one embodiment, the system includes a border color register that stores at least one border color pointer. A border color pointer indicates an address in an external memory at which border color information is located. Border color information is populated within external memory and retrieved by the texture cache controller if the texture filter unit requires a border color for texture mapping operations.

Description

200809691 ¥9, invention description: [Technical field of the invention] The invention relates to a bribe hardware device, and the system relates to a frame color processing system and method for the species edge processing unit. [Prior Art] As we all know, the electric job map is used to process large materials, including texture data. The texture is a digital image of a (1),... coordinate space, usually rectangular. The smallest addressable unit of a texture is a texture primitive (texel), which is assigned a specific (u, v) coordinate based on its location. In the texture mapping operation, the texture is applied to the graph of the % graph model when the model is drawn to produce the destination shirt image (destlnati〇n image). For this purpose image, the pixels are located on specific coordinates of the (X, y) coordinate system. Texture data is usually stored in system memory and is a shared resource. In other computer systems, other devices that have access to the data used by the processing bank, or the use-share system bus, will increase the data access time of the edge map processing system. In addition, when requesting data from system memory, it may take too much time due to other factors. Therefore, accessing system memory may affect the performance of the edge map processing system. - Improved #material access technology, through the storage of the data: a texture cache memory. The system memory provides texture data to the texture cache memory prior to the need for texture processing, thereby providing texture data to the edge map and reducing the need to access system memory. Therefore, it is less than waiting for memory.

ClienVs Docket No.: S3U06-O012I00-TW TTs Docket No: 0608-A4I !59-TW/Final/Rita/2007/04/20 5 200809691

However, the other type of data that is usually required for texture processing is the border color (border data, which is different from the texture data of the above texture cache system, and can also be stored and accessed in the continuation_#. In the border, in the border color mode, the border color data is usually requested in the texture processing. When processing - texture, or pasting it to the surface of the -_ model, the texture may not be full = overlay - edge graph model 'and The texture processing system of the tiling processing unit, in a special (u'v) dimension, must process the drawing model texture map beyond the coordinates of the texture range. - The specific border color can help the super-mosquito itself boundary coordinates The edge map model, therefore, the border color is usually required in these cases. Other examples of texture processing are in the -clamp mode, requesting -4 for the 4 graph model. If this mode, -_彡Including the full-face type 'fixes the texture image to cover the entire polygon (p〇lyg〇n). Any technical field of the art has the usual knowledge scales, and can also extend - the last pixel of the texture image, and The bribe texture image is attached to the remaining area of the bribe. Or, in other words, the pixels outside the image range are examined, and the texture data of the system is used as the edge of the image. For those who have knowledge of the f, the operation of the gorge It is a known operation, as the texture processing operation of the above-mentioned super-marker boundary. In the -Border color mode, the texture application of the '-Lai model is another example of texture processing. If this is the mode - the image Does not cover the entire model 'can apply the -_ color to the texture image range continuation chart model coordinates.

Clients Docket No.: S3U06-0012I00-TW TT s Docket No: 0608-A41159-TW/Final/Rita/2007/04/20 200809691 For the slaves to fix fresh 'for (4) - select the model part of the difficult image, This texture is effectively extended to the sturdy graph model. In the border color mode, you can select the color of the border for these coordinates. Can be through - programmer designer lion er), - automated software algorithm (遂. shout ed s〇f fre algQrithm), or hardware to perform texture processing operations, _ to select a border color 'and paste to the basic type , in the seat beyond the range of selected images

Marked. It should be read that 'Lin Hong's other such reliance on texture mapping operations' include, but are not intended to be limited to, wrap mode, a central mode, or other known modes. Currently, in the border color mode, the border color information used for the texture processing operation is usually stored in a dedicated memory set in the graphics processing unit (service. (4) or cache memory (cache) architecture. For each shader executed in the score processing unit, the border color information is usually represented by at least $ border color. That is, for each shader that can be executed in the drawing processing unit. In general, at least 16 border colors are required. In addition, the 16 border colors can be stored in different formats for use in a texture filtering unit or filter. In a non-limiting example 'Some, % map processing unit' stores each border color in a border color cache or border color memory in I2 different formats. In addition, each format requires at least 128-bit cache memory. Or memory storage space. Texture data is a shared resource, not a drawing pipeline

Client's Docket No.: S3U06-0012I00-TW TT5s Docket No: 0608-A41159-TW/Final/Rita/2007/04/20 200809691, the same class needs. And the multiple texts of the texture data (Fan Lu = different levels can perform texture processing operations, and need texture data or = education. Therefore, the profit on the (4) is fast. I r =, the effect of the treatment -, In the picture, the space of the card processing card is added early. Therefore, when the unit (4) executes several shaders in parallel, it is dedicated to the border color storage and caches the memory or memory, except for the texture data. In addition, it may also be needed for the edge processing unit of the color memory or memory. The use of '(10) to improve the processing of the graphics processing unit, set the leaf, and produce efficiency. The _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Overcoming the shortcomings of the known and required address technology. [Invention] The present invention - implementation of the disclosure - the type of processing unit. Scale - rational unit delicious including - border color register, - texture cache memory, a texture Cache memory control benefits, and - texture filtering The border color register stores at least one side color therapy, and at least - the border color indicator 'is used to indicate that at least 16 kinds of border colors are stored = the memory address. The texture cache memory controller is It is configured to display at least a kind of border color to a texture unit, and to edit the color of the copper frame.

Client’s Docket No.: S3U06-0012I00-TW TTys Docket No: 0608-A41159-TW/FinaI/Rita/20〇7/〇4/2〇 200809691 - Made. The texture cache memory and the body control device are configured to store the border color read by the external memory of the texture cache memory. The fity f 夬 忆 忆 体 控制 控制 控制 控制 控制 控制 控制 控制 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 纹理 纹理 纹理 纹理 纹理 纹理 纹理 纹理 纹理 纹理 纹理 纹理 纹理 纹理 纹理 纹理 纹理 纹理The state of the deposit - specified by the indicator. The at least 16 kinds of border colors are stored in the external memory towel, and when the texture filtering single-border border color guess texture mapping operation is performed, the texture is read by the controller. The at least is border color, in the form of a complex number, is arranged in the external memory at intervals of 128 bits. Another embodiment discloses a method of processing border color information. The method comprises the steps of: storing the plurality of border colors to an external memory, and storing the position of the border color of the 5th and the other in the external memory to the border color register. The method also includes reading a single record of the #border color record by the cultivating body, and storing the single record in a texture cache in a texture format. The method ^ step further includes providing the border color information required for the texture mapping operation to provide the single record of the texture primitive, the Lv recording format, to a texture filtering unit. The above described objects, features, and advantages of the present invention will become more apparent from the detailed description of the embodiments of the invention. [Embodiment] In summary, the present invention discloses a novel system and method for processing edge color data. Before beginning to discuss implementation details of various embodiments, reference is made to the drawings, which are block diagrams of particular elements in a schematic line in accordance with an embodiment of the invention.

Client's Docket No·: S3U06-0012I00-TW TT5s Docket No: 〇608-A41159-TW/FinaWlita/2007/04/20 200809691 . As mentioned above, different levels of the i-picture pipeline can perform texture operations and sequential access. The border color is poor. Therefore, the present invention discloses the storage and reading of the border color data for improving the logic performance of the processing unit.翏考弟1图, shows that the -_ pipeline such as the mosquito component or the hierarchical block diagram is - the command stream processor 252, receives the money to take the vertex coordinates of the memory, to form the geometry of the pipeline (ge〇 Sense primitive) or generate a work item. In this regard, the command stream processor 252 reads the data of the memory, and according to the turn, generates a triangle, a line, a point, or another map of the pipeline to be transmitted, once composed, It is then passed to the vertex shader (5). The top coloring $ 254 ' can be used to perform paste coordinates, such as conversion, scanning, and illumination. The vertex shader 254 can be accessed by a texture component to access a texture operation or a texture engine of the green map processing unit MO. As mentioned above, when the texture operation occurs in the - edge (four) twilight mode, the persimmon (4) twilight information. The vertex shader 254 passes the data to the geometry shader. The geometry shader (5) receives the vertices coordinates as input, as a complete primitive, and can output multiple vertices coordinates to form a single topology (t〇P〇l〇gy), for example: Triangle (he is difficult to strip), line segment (Une coffee, index set (^ pull: Ust), etc. 5 Hai geometry shader MS, is further configured to perform various algorithms, for example: tessellation (tessellati〇n) The yaw (four) product generation method, etc. The vertex shader 254 as described above - Similarly, the geometry shader may be requested by the texture element 267 to access the texture operation or the graphics processing unit 25 - the texture engine.

Clienfs Docket No.: S3U06-0012I00-TW TT5s Docket No: 〇6〇8.A41159-TW/FinayRita/2007/〇4/20 10 200809691 'This, the border color information can be requested by this level of the drawing pipeline 2〇〇. The geometry shader 256 outputs the information to a triangular composition layer 257 for performing operations 'eg, triangle trivial rejection, determinant calculation, culling, KLMN Attribute setting (pre-attribute setup KLMN), edge function, number calculation (6 (1 v; ^11 (:1::1〇11 calculation), guarcjband clipping). Usually the knowledgeer should understand the operation required for a triangular composition phase' without further elaboration. The triangular composition layer 257 outputs information to a span generator/tile generator. The pipeline layer is also a well-known technique and need not be described in further detail. If the triangle processed by the triangular composition layer 257 is not rejected by the range generator/tile generation 258, or other drawing pipeline layer, the drawing The # attribute setting layer of the pipeline performs the attribute setting operation. This attribute sets the layer to generate a set of known and required interpolation variables to be determined at the next pipeline level. In addition, the attribute setting layer 259 is also one of the prior art for processing various attributes related to geometric primitives processed by the drawing pipeline. The hex pixel shader 260 loads the primitives output by the attribute setting layer 259. Each pixel is covered. The pixel shader 26 is operative to perform interpolation and other operations for determining the pixel color and outputting to a display buffer memory 2S2.

Clienfs Docket No.: S3U06-0012I00-TW TT5s Docket No: 0608-A41159-TW/Final/Rita/20〇7/〇4/2〇11 200809691 —Vertex Shader 254 and Geometry Shader 256, This Pixel Shading The texture device 269 may request access to the texture operation or graphics processing unit 2s - the texture engine. Therefore, the drawing pipeline 2 may require border color information at this level. The operation of the various elements illustrated in Figure 1 is known to those skilled in the art, and there is no need for additional processing. Therefore, the specific implementation and operation of these components need not be further elaborated herein to make the understanding of the present invention more complete. The above drawing pipeline is usually implemented in a drawing processing unit or a drawing processing device. The drawing pipeline of the standard is usually specified in the published application interface (application pr〇gramming interface; work), or application type / 1 surface set, ribs to add specific requirements to the program of the drawing - non-limiting example For the heart (1) flap:. This should refer to FIG. 2, which shows a conventional processing unit, including: a texture cache memory controller (TCC) 120, wherein, in the border color mode, it is configured to store ite color data for Texture operation reads. You should be aware of the components that are not necessary for the description of the pattern processing, and are omitted here for easy explanation. The computer graphics system includes the image processing system, and the reader graphic designer can use the shader, such as: geometry, crying, you, #々绿之色色, pixel color, vertex shader, 矣 矣body. This shader is issued by the programmer and can be executed at least with less == single na 3... The age of the decision is: This can include this multi-thread operation - the processing unit. It should also be "this map processing unit included by the green graphics programmer, with parallel execution 12 200809691 : Γ: multiple shaders. For example - - pixel shader, can be - geometric shader, and pixel shader Another event is flattened, and it may be necessary to execute the single pepper 3Q6. This is the color of the parallel frame color data of the shader. The texture data, and / or the edge η: early 兀 126 received from - Processing pipeline (not shown)

=Γ26 ′ When processing a lobed line, some pixel operations are handled. In the above-mentioned unit, '_128 is the one of the pipeline execution data pinning', which is the pre-packaging unit 126. The texture address generator ιΐ8 sends a mosquito description symbol request in response to the execution of the coloring crying communication in the execution unit (4) 3.6. The request is sent to the texture cache controller (tcc) 12〇. Texture cache memory, output sensible descriptor bribes to _ address generation _ call sister _ resignation to deal with. Since the various embodiments of the inspection address generator 118 are well known to those of ordinary skill, further description of such elements is omitted herein. 1. The tattoo is taken from the memory control (4) 12. The system includes a memory for the memory, for fast-moving the button, for example, the pattern _ element, and the rib processing texture data to clear one of the memory controllers. The texture cache memory controller reads the requested texture data from the memory and extracts the texture data in the texture cache memory. The texture cache memory controller UO provides texture data, including texture primitives, to the texture filtering unit I22 for texture processing operations. The pattern

Clienf s Docket No.: S3U06-0012I00-TW TT5s Docket No: 〇608-A41159-TW/Final/Rita/2007/04/20 200809691 - The memory controller, in texture primitive format, will be the data, For example, a texture record is provided to the texture filtering unit 丄22. If the requested data is not stored in the silky structure, then the texture access unit 52 is accessed by the memory cache, and the texture data can be accessed by the memory ls. When the texture filtering unit I22 requests the poor material to perform the texture operation, the texture cache memory controller! 2〇 also reads the border color information stored in the border color cache memory, and the border color is Information is provided to the texture filtering unit 22 . When the border color, age, and frame color format are stored in the border color cache (four) 124胄, the texture filtering unit 22I22' further includes a logic circuit for decoding the color of the frame read by the texture filtering unit (2) operating. Furthermore, the texture filtering unit process must convert the read boundary to the - format and perform the texture operation. In the border color mode, the border color information usually includes predefined constants for representing colors for texture operations. For example: - edge _ color his μ bit job format table I ' and stored in the border color cache memory 124, when the selected texture map is aged (1), when the ticket is filled, in the model coordinates, the texture filtering unit 122 Can

The box color is applied to the 2D or 3D model. I know that the execution unit collects multiple borders in parallel. Therefore, the border color cache _ 124 _ 2 = space, used to store the execution unit pool 3 〇 6 parallel ^ "sub-frame color information. In addition, for the __ mother - the color required In the edge map processing unit * color, in the border color mode, 仃,,,,,,,,,,,,,

Clients Docket No.: S3U06-0012I00-TW TT,S Docket No: _8-A41159-TW/Fiml/Rita/2()_4/2〇14 200809691 'Color, and the texture is over the unit 122, in the border color box The color is applied to the __ model. Depending on the texture, different edges can be manipulated. H can be formatted. For example, the edge map processing unit architecture can support up to work = color. The border color is thus kind of 124! The border color is saved and stored in the color cache format. At the same time, for each of the 7 work colors, it is necessary to support multiple records with different elements. _Inside the lb of the mother, a shader is used to process the single-frame color memory 124 to maintain the color of the frame. Multiple contexts, A multiple format storage. ^母—The color of the frame is the same as that of the computer system. As the edge processing unit and the computer system improve, it needs a larger six miles: _ color cache memory 124 to store the frame_message on the chip: = = color cache memory. In the implementation of the secret, the -_ processing unit can perform a certain number of colorizers in parallel with the prior art; however, the technology of the future can greatly enhance this capability, and f more chips are needed to store the border color. In addition, usually through the - software margin application interface (10), for example, · add t job PI ‘with her-style, _ special border color poor news. Therefore, in order to perform the texture operation in the border color mode, it is supported by the hardware device, and the borrowing body driver accesses and writes the heterogeneous color cache carrier 124. side

Client’s Docket No.: S3U06-0012I00-TW TT5s Docket No: 0608-A41159-TW/FinaI/Rita/20〇7/〇4/2〇 200809691 3. . In addition, some of the elements of the embodiment of the present invention are omitted. (4) Some components not necessarily described in the stomach map processing unit are omitted here, (4). As described above, the paste processing unit of the second object, in the figure, includes a drawing processing unit $, a graphic program, and a computerized system, which can provide a coloring device, such as a geometry. A technique known as shader, pixel color state, vertex shader, or A. Developed by the programmer = color 1' and at least through the multi-programmable execution of a single domain area. ^ Note that the execution unit pool 3Q6 may include multiple maps; It should also be noted that the 4' processing unit includes the edge mapping processing unit, which is a test of the coloring crying diagram. Q's implementation, it may be necessary for the execution area to read the texture data, and/or the multiple texts of the border color data/the, and the texture address generates the spoofing 'send-texture description symbol request to respond to The implementation of single-leaf 3Q6+ execution shader communication. The request is sent to texture cache memory and texture cache memory control _ (Qing gamma. The texture cache memory control 42., will be happy to describe the symbol data round to texture address generator II8 or texture Filtering is performed by unit 422. Since the various embodiments of the texture address generator (10) are well known to those of ordinary skill, further description of the elements is omitted herein. As described above, the texture cache memory controller (Tcc) 42〇, including a mosquito memory, _ cache texture, such as: texture primitives, and for processing

Clienfs Docket No.: S3U06-0012I00-TW TT5s Docket No: 〇608-A41159-TW/Final/Rita/2007/04/20 16 200809691 Texture Data Request - Cache Memory Controller. The new fast-moving body controls the crying, and the requested texture data is read by the memory, and the texture data is cached in the texture cache. The analytic cache memory controller (4) 42 ◦, the texture data, including the texture map s ' is provided to the texture filtering unit, for texture processing operations. The texture cache memory controller 42G provides a texture record, such as a texture record, to the texture filtering unit a2 in a texture primitive format. When the requested data is not stored in the cache memory, the view is viewed. Newton access unit 152, the texture

The cache memory controller 420 can access texture data from the memory 1SQ. When the texture operation is performed, the texture filtering unit a2 requires a border color, and according to the embodiment of the present invention, a thin processing unit can provide a border color processing secret, and (4) improve the number of hardware logic gates. The border color information can be stored in external memory! Yes, instead of the read-only processing unit dedicated to the cache as shown in Figure 2. The border color register 424 stores the position information of the external memory 15Q. Stored in the border color register like an indicator, you can specify the base address of the silk storage frame color information in the memory 15G. As described above, for each shader executed in the readable image processing unit, the texture operation can be performed in the border color mode (4), and the texture filtering unit 422 can be in the border color mode. Apply different border colors to the -edge graph model. According to the volume filtering operation performed by the texture filtering unit 422, any predetermined border color can be requested in a multiple data format. For example, · 一缘广 Processing unit weaving New Zealand 16 kinds of format (/ riding 16 kinds _ 贞 color) ^

Clients Docket No.: S3U06-0012I00-TW TT5s Docket No: 〇608-A41159-TW/Fina3/Rita/2〇〇7/〇4/2〇17 200809691=早—_ can request 16 kinds of border colors, and Each of the 16 border colors =: must be stored in a different format. At the same time, each pair can be executed in parallel: the shader. The % picture s supports the township to remember New Haven, and the colorizer maintains the multiple texts of the border color. In order to be parent-supplied, the color information can be aged in the external memory 15Q when the texture is operated in the border color mode and the border color is required. Such as - non-limiting embodiment, - camp processing unit, can be executed simultaneously - vertex shader,

=-pixel shader, and supports both of the two shaders: ", therefore, through the texture cache memory controller 420, the scale processing unit has the ability to simultaneously store, read, and cache external memory. The 6 sets of border color text. In addition, 'by the domain driver, the border color can be stored in the outer pool %" and eliminates the need for texture cache memory 42〇 and texture over 7L 422 to Convert to - appropriate data format ^ for texture operations. In addition, the texture cache memory controller can be similar to or consistent with the structure of the cached texture image that has been read. The texture cache memory control H can selectively sculpt the texture primitive recording format, that is, the miscellaneous color of the silk and the current miscellaneous color cache to the texture filtering unit 422. When the original border color and/or the current border color are cached to the texture filtering single core 22 in the texel recording format, the texture overrunning unit 422 is simplified by the requirement of silk or eclipse Texture cache memory control

Client's Docket No.: S3U06-0012I00-TW TT’s Docket No: 0608-A41159-TW/Final/Rita/2007/04/20 18 200809691 Controller 42. The hardware logic circuit is used to process the temporary unit 422 and the external && The texture early and heterogeneous cache memory controller 42 可 can selectively use the same data structure, using a border color as a record of two, 士, 、, 、, 里图兀. It also eliminates the need for the border color cache memory of the processing unit. This color information is stored and read by the external memory 15 instead of the border color memory. · As far as possible, ____, store the continuation of the memory of the squad, _, where the 'each-frame color record is stored at intervals of café bits. In the non-form example, it is continuous Memory block. It is also best to store the various types of support for each of the corridors in the continuous memory block.妓 'Texture Cache _ _ ga, can be read from the contiguous block with the help of the border color indicator - the specified border color. The border color indicator is stored in the border color register 424 to specify the silk of the continuous memory block. When Nuori operates in the color mode, each border color can be stored in external memory in different formats, including (but not limited to): UINT32, SINT32, _RM8, _ship, TO〇RM16, SNORM8, SNORMIO , SNORM16, SNORM24, FP16, and FP32 The technical details regarding these formats are disclosed and are known to those of ordinary skill in the art. For example, the basic information of each format is defined as follows: UINT32 . unsigned 32 bits integer ; SINT32 : signed 32 bits integer ;

Clients Docket No.: S3U06-0012I00-TW TT5s Docket No: 0608-A41159-TW/Final/Rita/2007/04/20 19 200809691 UNORM8 : 8 bits unsigned normalized integer ; UNORMIO : 10 bits unsigned normalized integer ; UNORM16 · 16 SNORM8 ' 8 bits signed1 normalized integer ; SNORM16 - 16 bits signed normalized integer ; SNORM24 ^ 24 bits signed normalized integer ; FP16 · 16 bits float Point value ; FP3 2 · 32 bits float point value o As described above, when each border color is stored in a contiguous memory block, and each border color in the contiguous block range is stored in different formats and in a consistent order. In the contiguous block, the texture cache memory controller 4; 2 readable - the predetermined border color record only by using the base address pointed by the border color indicator of the border color register 424 . The drawing processing unit architecture as disclosed above, relative to the drawing processing unit of Fig. 2, greatly eliminates the need for border cache memory and greatly improves the logical rendering performance of the hardware. In addition, with the advancement of the performance of the computer system and (4) processing unit, the present invention provides a method for color processing of a frame, because when the "Lotus sound unit" can perform the binding (9) or the field-coloring-need text in parallel, By adding the border color indicator to the border color register is like ^

Client's Docket No.: S3U06-0012I00-TW TT^s Docket No: 〇608-A41159-TW/Final/Rita/20〇7/〇4/2〇20 200809691, σ~成所~ plus border color processing requirements, Instead of using more border color to cache memory.

The McCaw 4th image shows an exploded view of the edge-color register and an external memory 15〇. It should be understood that the free memory space 427 (a~f) need not be described as - all available free space of the external memory, however, the free memory space 427 is described for clarity and ease of illustration. The border color register 424 stores the S pen border color indicator to supply three parallel performable shaders, and the two sets of memory in each shader φ are:

Pixel—Shader_l—Pointer, Pixel_Shader_2_P〇inter > Vertex_Shader_l_p〇inter -

Vertex—Shader_2—Pointer,

Geometry—Shader_l_p〇:[nter, and Geometry_Shader_2_P〇inter ° _ It is worth noting that more or fewer border color metrics can be used depending on the number of border color texts that are required to support the graphics processing unit. For example, a low cost graphics processing unit using current technology can be configured to support fewer colorizers that can be executed in parallel; therefore, fewer border color metrics are required. Alternatively, the graphics processing unit can be configured to support more parallel shaders, requiring more border color metrics. It should be understood that when the above-mentioned border color temporary state 424 supports 6 sets of border color data in the external έ 忆 iso iso iso,

Client's Docket No.: S3U06-0012I00-TW TT^ Docket No; 0608-A41159-TW/Final/Rita/2007/04/20 21 200809691 At this point, the 'one-phase processing unit does not need 6 sets of internal memory (4) space, ϋFor various kinds of coloring n that can be performed in parallel, it is possible to perform texture operations without using the border color mode. For example, only one shader needs a border color for texture operations; therefore, only one set of border color information is stored in the external memory ls〇.

When the texture operation is performed in the border color mode, the border color information can be stored in the contiguous memory block 425 (a to d) through a software driver. Each contiguous memory block 425 can store 16 border colors corresponding to the executable shaders. Step-by-step, each border color is stored in 12 different data formats for texture retrieval, memory control, and texture over-reading. Each border color can be stored in external memory in the following format, including (but not limited to) UINT32 > SINT32 ^ IMorms > UNORM10 > UN0RM16 > UN0RM24 > SN0RM8, SNORM10, SN〇RM16, SN〇RM24 , Fpi6, and 32. Each border color can also be continuously stored in the above U format. In addition, in order to change the access force, the parent border color format can store the fineness of the bit gate Ik and note that the interval will vary with the location structure of the external memory and/or the size of the memory block. change. Each of the contiguous memory blocks 425 can be stored at different locations of the external memory M lso , with the result that a free memory space 427 is created between the different contiguous memory blocks 425 . It should be noted that freedom. The Lfe workstation 427 need not be unused or vacant because the graphics processing unit can use the free memory (4) 427 for other purposes. The above-described arrangement for each contiguous memory block 425 can also be varied in accordance with the present invention.

Clients Docket No.: S3U06-0012I00-TW m Docket N (4) 608-A41159_TW/Fina_a/2_〇4/2〇22 200809691 The above-mentioned border color indicator, specified - continued to be stored in the external memory 15Q color 425, Sub-and the pointing body side-to-edge _ color index, the axis I required for the test cache memory, the processing operation - both _, wrist. As mentioned above, the second is called the texture processing operation - the base position: :?:=, the texture cache __ readable two-two fine-cut memory and arrangement structure, the border color data can be stored in the order In the external memory 150. Referring to Figure 5, there is shown a flow chart 5 of a method in accordance with an embodiment of the present invention. In the step coffee, the border page color data is stored in an external memory. As described above, the border pure data, corresponding to the shader executed by the processing unit, can be stored in the contiguous memory block to provide more efficient reading. When the texture operation is performed in the border color kernel, the border color information can be stored in the external memory. The color information of the border can be stored in the external memory through the combination of the software-driven and the software-based interface, such as Direct3D@API. In step 5〇4, a border color indicator stored in a border color register is specified, and one of the base addresses of the memory is used to correspond to the position of the color information of the border in the memory. Referring to the above embodiment, the border color indicator allows the texture operation to read the border color information from the external memory. In step 5〇6, a request for a border color is received. In step 508, the base address of the border color information is returned, which is stored in the border

Clients Docket No.: S3U06-0012I00-TW TT5s Docket No: 0608-A41159-TW/Final/Rita/2007/04/20 23 200809691 . _ 5i. , fine border color, outside Liangzhu 隹 Bay State mouth item to take the required border color. ^ Color is also viewed in a fast-tracking billion body. For example: _ texture fast-moving billions of body, to pass through - bribe silk (4) series _ miscellaneous touch. In the step (1), the frame can be transmitted to the texture-pattern recording format, and the method of the fifth embodiment is as described in the present invention. Others ► (4) Implemented in hardware, software, her, or in combination. In Yu Beiguan, the method continues to be implemented in the memory and stored in the memory, and an appropriate instruction execution system is executed. In another embodiment, the method is implemented in a hard body, and the method can add a discrete logic circuit by any of the following techniques, or a combination thereof, and the ancient twist-change-negative, and the gastroin. Between the logic of the function, an ASIC (such as 〇, with appropriate logical closed combination; logic coffee (four) ... field effect programmable logic __ Α), integrated 2 figure processing unit components. Any force that has a general knowledge of this turn should be understood, stream descriptions or blocks, _ _ _ _ circuit, embedded circuit = group, section, or part of the code, including to achieve specific Logic function difference = the storage process step, the financial formula is also in the invention = the knowledge of the case, the functions may not follow the order shown or discussed, ^ simultaneously or in reverse order, According to the required function. c

ClienVs Docket No.: S3U06-0〇12I〇〇.TW TT's Docket No: 0608-A41Tw/rr, i59>TW/Final/Rita/2〇〇7/〇4/2〇24 200809691 On the strong mouth, The embodiment of the present invention is merely a possible example of the implementation method, and is merely for the purpose of clearly understanding the present financing method. Without departing from the spirit and principles of the invention, the embodiments of the invention described above may be modified. All such acts and modifications are included in the scope of the present invention and are protected by the appended patent application. For example, according to the details provided, those skilled in the art should understand that the image processing unit of the embodiment includes a border color register, a texture cache, a body, and a texture cache memory control. Following, and - texture filtering unit. In some embodiments, the border color temporary storage H stores at least a border color indicator, the at least—the border color indicator points to the position of the border color information in the external memory, and the border color information is stored in the external memory, and When the texture filtering unit requests a border color for the texture mapping operation, it is read by the texture cache memory controller. In an embodiment of the invention, the border color register stores at least a -border color indicator 'for each shader event executed by the scaleable processing unit, and the external j-memory can be configured to store at least 16 A border color for each-shader event that can be executed early by the green map. The at least 16 border colors can be stored in any of a plurality of formats and further arranged in an external memory at intervals of 28 bits. In other embodiments, the texture cache memory controller can be configured to read a border color from the external memory on behalf of the texture filtering unit, wherein the indicator is temporarily placed through the border color H - the base New, but left external memory

Clienfs Docket No,: S3U06-0012I00-TW TT5s Docket No: 〇608-A41159-TW/Final/Rita/2007/04/20 25 200809691 In _@/4 cases, the texture cache is used when the border color is operated. The memory 1 is configured to represent the texture filtering unit, and in the format _, select ==. In other embodiments, the texture cache memory can be configured to be used to read the borders of the textures to the texture cache memory. In ―1 d, the memory controller can be configured to set the border color == mesh (4) to run the flap & In other real _ towel, when the - grain address is generated

Compared with the texture 滹 罩 所 + + + h h h + + + + + h h h h h h h h h h h h h h h h h h h h h h h h h 70 70 70 70 纹理 纹理 纹理 纹理 纹理Consistent with other embodiments of the present invention, a method for processing the color information of the frame, the steps of the method include: storing the color of the plurality of borders - externally remembering the location of the external memory of the border color in the _ The color of the border is temporarily stored... The single record of the border color is recorded by the D-Hui's memory; the _ secret_single-recording storage-texture memory, and the texture mapping operation f The border color ##, the texture element of the single-record format is provided to a texture filtering unit. In some cases, the steps of the border color section (4) are executed by the software drive. The step of storing to the external recording, further includes: converting the color of each of the border colors to the data format of the plural, and translating the color of the (4) frame into the (4) format cake section. The conversion operation can view each border color as at least 12 data formats. In the external memory, the transfer 26 200809691 - the change operation is also 128-bit coffee, each side - in some embodiments, the storage to the external memory. A _ processing unit can perform every - shader false total = including: for external memory. In some embodiments, the color indicator of the aging frame age is stored in the border color register, and the at least _, true will at least 兮笙, true 4 ± · μ 夕 border color indicator points to the finder frame wrist Store fines (4) (10) i. · „ Parallel execution of each-consumption (four) words, in the -& ^ phase processing soap element can be a border color indicator. In the middle, including storing at least 1 his Shisaki '-_ processing unit, including: - border color temporarily stored The m ^ 脉 体 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的The external record, the hex controller can be configured to provide the 16^ texture primitive record format to the texture filter unit for color operation; the texture cache memory controller can be configured It is used to store the color of the border read by the external warfare to the texture cache memory. The texture cache body (4) H' is also configured to represent the fresh elements, from the outside of the sea, - the base address reads a border color, the base address is stored in one of the 5 hai border color register indicators; 4 in the external memory, and when the texture _ single = 1 border color storage Early 70 needs a border color for texture mapping operation The cache memory controller reads; and to a plurality of the grid

Clienfs Docket No.: S3U06-0012I00-TW TT5s Docket No: 〇608-A41159-TW/FinaI/Rita/20〇7/〇4/2〇 27 200809691, the at least is border color is in the body. The spacing of the I28 bits is excluded from the external caution. Although the thief of the preferred embodiment is as described above, it is intended to limit the present invention to those of ordinary skill in the art without departing from the spirit and scope of the present invention. _, when (4) is more dynamic and _, the scope of this daily protection is subject to the definition of the patent application scope attached. :

Clienfs Docket No.: S3U06-0012I00-TW TT5s Docket No: 0608-A41159-TW/Final/Rita/2007/04/20 200809691 [Simple diagram of the diagram] Figure 1 of the component diagram of the f1 diagram Display - Continuation of the processing unit and its specific map; .

The figure 3 shows that each of the five examples of the present invention is a drawing processing energy block diagram; the first drawing of the present invention shows a schematic diagram of one of the yoke examples of the present invention; The fifth picture shows the present [main component symbol description] One of the methods of the implementation of the flow chart 3〇0~, ♦ Figure processing I minutes · early 兀, 15 〇 ~ memory; 3 〇 6 ~ 夕重Programming execution unit pool;

26 ~ pre-packaging unit; 13 〇 ~ packaging unit; I22 ~ texture filtering unit; 424 ~ border color register; 120 ~ texture cache memory controller 124 ~ border color cache memory; 128 ~ interpolator 118~ texture address generator; 420~ texture cache memory controller; 152~memory access unit; 200~ drawing pipeline; 25〇~ graphics processing unit; 265, 267, and 269~ texture elements; ~ command stream processor; 254 ~ vertex shader;

Clienfs Docket No.: S3U06-0012I00-TW TT's Docket No: 0608-A41159-TW/FinaI/Rita/2007/04/20 29 200809691 - 256~ geometry shader; 257~ triangle composition layer; 258~ range generator/ Brick generator; 25 9~ attribute setting layer; 260~pixel shader; 262~ display buffer memory; 425a-425d~ contiguous memory block; , 427a-427f~ free memory space; 502, 5〇4 , 506, ..., and 514~ operation steps.

Clienf s Docket No.: S3U06-0012I00-TW TT5s Docket No: 0608-A41159-TW/Fmal/Rita/2007/04/20

Claims (1)

200809691 X. Patent application scope: 1. A drawing processing unit, comprising: a border color register; a texture cache memory; a texture cache memory controller; and a texture filtering unit; wherein 'the border color Temporary storage left It is used to refer to the color index of the side of the side, and the location of the body; and where the '姊__ is stored in the Yuan requires a trace of age, _ 卜 卩 卩 卩 当 当 when the enemy filter single device reads ', 仃, When the '5 texture is known, 'through the texture cache memory control 2. Please refine the key unit described in item 1, where the color can be complemented by the border. ^檐 wrist gamma at least - Side tearing, shooting, each shader event executed by the _ processing unit, the external note border color f system is configured to store the plural as stated in the application! The _ processing unit of the job, the towel, the external note system is configured to store each border color in a plural format. 5. If the edge map processing unit described in the fourth paragraph of the patent application is used, the border color stored in the format is arranged in the external memory at a predetermined interval. μ... Pjenfs Docket No.: S3U06-0012I00-TW S D〇cket No: 0608-A41159-TW/Final/Rita/2007/〇4/2〇 31 200809691 Please wait for the second! The processing unit of the clarification, in which the memory is controlled by the arranging ribs, ..., one of the Wu Ma #uj 夂 early 70, the border color of the external memory is taken 'the base address is temporarily stored One of the indicators specified by the state. 7·如申鞠_第! The read-reading processing unit takes the memory m to be configured to represent the texture filtering privately, and in this way, a border color is taken for the border color operation. 8 · If you apply for a patent fine! The item of the rider is at the piano element, and the towel = 2 grain configuration _ saves the texture information of the border taken by the texture memory and the external memory. 9. The application for the edge map processing unit described in the above paragraph, wherein the texture cache is configured to provide the border color information to the texture filtering unit in a texture primitive recording format, The operation of the color. 10. The processing unit as described in the patent application, wherein when a texture address generator generates a bit address that is beyond a range of ones processed by the texture filter unit, The control is configured to be the outer fiber frame color. U. If you apply for a patent! The fine processing unit described in the item, _, the color of the side frame temporarily stores the gambling of the age of Wei, and the ribs read the color of the border color required for the color boundary of the plural. ^ 12. A method for processing border color information, the method includes the following steps: Ciienfs Docket No.: S3U06-0012I00.TW 〇c et No. 0608-A41159-TW/Final/Rita/2007/04/20 32 200809691 f Color to - external memory; in the external memory, the position of the border color is stored to a border color register; 'by. The color record of the outer scale of the rattle scale is a single record; in the texture map recording format, the single record is stored in a texture cache memory, and For the border color information required by the text and texture, the single record of the edge of the texture primitive recording format is provided to a texture filtering unit. 13 ^ The processing of the border color information as described in item 2 of the patent application scope Method, - the step of 'storing to the external memory, further including ·· _ Qing Nen (four) 峨, the fiber _ color is stored in the external memory in the scallop format. i ”_第12狮叙纽杂The method of storing the image to the external memory further includes: for each shader executable by the edge map processing unit to the external memory. 15 · 帻 帻 第 第 第 第 第 第 第 第 处理 处理 处理 处理 处理 处理 龟 处理 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟 龟The method for processing the border color information according to the item η, wherein the step of converting each border color further includes: TT^Docket^ 200809691 Part of the memory of the part memory - the border color, at a predetermined interval The outer shell color is stored in the value of the cultivating part memory. : 18. If the first paragraph of the patent application scope is 12j, +, ^, the method of processing the edge _ color information is as follows: , and the indicator is for each border of the coloring benefit of the _ processing unit. The color 19', as in the 12th item of the patent application scope, is less than the old one, and will be used in the block method of the information. = sub-continuation of 5 hai external memory Clienfs Docket No.: S3U06-0012I00-TW TT’s Docket No: 0608-A41159-TW/Final/Rita/2007/04/20 34