TW200809688A - A system for reducing bandwidth requirements for transferring graphics data and its related method - Google Patents

Abstract

Various embodiments for reducing external bandwidth requirements for transferring graphics data are included. One embodiment includes a system for reducing the external bandwidth requirements for transferring graphics data comprising a prediction error calculator configured to generate a prediction error matrix for a pixel tile of z-coordinate data, a bit length calculator configured to calculate the number of bits needed to store the prediction error matrix, a data encoder configured to encode the prediction error matrix into a compressed block and a packer configured to shit the compressed block in a single operation to an external memory location.

Description

200809688 . v - * , IX, invention description: [Technical Field] The present invention relates to image data compression, and more particularly to a system and method for z-axis data compression and encoding. [Prior Art] As known in the art, the 3D computer image system 10 of art and science is generated or drawn by 2D images of 3D objects and then presented on a display device (such as a cathode ray tube display or a liquid crystal display). on. This object may be a simple geometric primitive such as a point, line, triangle, or polygon. Many complex objects can be drawn on the display device by a series of connected planar polygons. For example, the object can be represented by a series of consecutive planar triangles. All geometric primitives may end up being represented by a vertex or a set of vertices. For example, the coordinates (χ, y, z) may be defined as a point, or the end of a line, or a corner of a polygon. # In order to generate a set of data for a 2D projection of a 3D primitive to be displayed on a computer monitor or other display device, the vertices of this primitive will undergo a series of operations or stages in a pipeline. A basic pipeline is only a series of processing units or stages of superposition, and the output of the previous stage is taken as the input of the next stage. For example, the processing stages in a graphics processor include vertex operations, primitive combination operations, pixel operations, texture combination operations, rendering operations, and fractal operations. In a typical graphic display system, an image database (such as a command line) I stores an object description of a scene, and these objects are described as frost

Clienfs Docket No.: S3U06-0020, Viewing dishes in the table TT5s Docket No: 0608-A41222-TW/Fmal/LukeLee/2007, 06, 06 5 200809688 Several small polygons. Similarly, several tiles can be covered in the same way on a wall or other surface. Each polygon is represented as a table, including vertex coordinates (X-axis coordinates, Y-axis coordinates, Z-axis coordinates in the model base), and some material surface characteristics (color, texture, brightness, etc.), and possibly There is a regular vector of the surface formed by each vertex. For 3D objects with complex curvature surfaces, the polygons must usually be triangular or quadrilateral, while the latter can be broken down into / to triangles. The Xin conversion engine converts the coordinates of the object to the angle of view output by the user. In addition, the user can set the field of view, the resulting image size, and the visibility of the back end to include or remove the background as needed. When the field of view is selected, the brave logic removes the polygons (triangles) outside the field of view and trims the polygons that are outside the field of view but partially within the field of view. These trimmed polygons will correspond to polygons within the field of view, and their new edges will correspond to edges within the field of view. The vertices of these polygons are then passed to the next stage in the form of coordinates corresponding to the screen field of view (X, Y coordinates) and depth (Ζ coordinates). In a typical system, there will be a source model to take the light into consideration. The color values of the polygons are then passed to the renderer, which produces blank pixels for several blocks as a subsequent visibility decision, or a hidden surface removal and texture calculation/shading of the remaining pixels. Figure 1 shows an embodiment of a current hidden surface removal unit, commonly referred to as a paraxial data processing unit. As is known to those skilled in the art, system performance is improved by the implementation of removing the official line using a two-stage hidden surface. In the first stage, the ZL1 unit processes the axis data of the complex pixels in the block. When the z-axis data of a pixel in a block is super

Client's Docket No.: S3U06-0020 TT;s Docket No: 〇6〇8-A41222-TW/Finai/LukeLee/2007, 06, 06 6 200809688 η - -'w When the ZL1 format range is used, this axis data It is necessary to perform pixel level processing in the pixel data processing unit (sometimes called ZL2). The names of ZL1 and ZL2 generally represent the first-order buffer and the first buffer, respectively. Their names will vary depending on the type of algorithm, such as a super buffer or a hierarchical buffer. This two-order ζ unit implementation allows for higher-order depth data storage of larger pixmaps (such as a block and minimum particle depth data storage (such as a single pixel on the screen). The advantage of ZL1 is to reduce depth data in the drawing pipeline. The calculation is 9 degrees in complexity. The block generator 1 generates a block metric (ie, a pixel mask) of pixel tiles (such as an 8 by 8 square) and transmits a request to the ZL1 cache 1〇4. The block data is then transferred to ZL1 102, which is coupled to ZL1 cache 104 and defines visibility at the block level. If the axis data of the pixel cannot be processed in ZL1 102, the axis data will be at the pixel level. The axis data processing unit 2X2 106 is processed, ZL2 1〇6 || is connected to ZL2 • Fast = 1〇8. Under this setting, ZL1 102 can reject processing up to 64 pixels in one cycle. The unrejected pixels are marked as accepted or retested to reduce the memory usage of the ZL2 106. As the performance of the graphics chip continues to increase, the bandwidth requirements of the memory become the primary performance when performing the above operations. Factor Moore's Law, the increase in memory bandwidth usually lags behind the increase in wafer computing power. Thus, in many cases, the overall performance of the graphics engine in the system is ultimately limited by the available amount of image memory bandwidth. The cache and data compression scheme is used to solve the problem of memory bandwidth limitation.

Client's Docket No:: S3U06-0020 TT5s Docket No: 0608-A41222-TW/Final/LukeLee/2007, 06, 06 7 200809688 The efficiency of the mode is high. The degree is related to memory access. The problem is that a large triangular primitive with a large amount of pixels is good for _W_cache, so the way to provide a cache is almost I-effect. Because: the lack of two kinds of 阙 阙 (4) seeking to exist in the industry to gamble the above deficiencies [invention content]

Include a ===!!: The external bandwidth-system example, a box, twenty different to produce a pixel block of the Ζ coordinate data of a prediction of the disease matrix, one yuan county produces 4 tubes Μ , + Μ Μ to calculate the total number of bits needed to store this prediction σ, difference matrix, a data input i π A. .^^ Bellow, the flat coder is used to pre-process the matrix, the 4-code into the compressed block, and the packetizer is used to move the compressed block to an external memory in a single transport. Stand upright. Still another embodiment includes a system for reducing the bandwidth requirement of image data transmission, comprising a de-enveloping core group moving with an alpha-external memory location-compressing block and unwrapping a prediction error matrix from the abutting block, And an addition tree for deriving a pixel block. In some embodiments, the decapsulation module further includes a hopping sequence depacketizer for decompressing each hopping sequence in the prediction error matrix, and a depacketizer compresses the prediction error matrix from the compressed block. And an addition tree restores the pixel tile. There is still an embodiment of the method for reducing the bandwidth requirement of image data transmission, comprising: compressing image data containing a plurality of pixel tiles by storing a pre-ambiguity error of each pixel tile. The length of the element, the compressed paraxial data is encoded into a compressed block, and each compressed area is moved in a single operation.

Client's Docket No.: S3U06-0020 TT5s Docket No: 0608-A41222-TW/Final/LukeLee/20075 〇6} 〇6 200809688 Block-to-output bus, where each block contains several bits, and transmits these Data is transferred from the round to the fast: and passed. The π limbs are used for subsequent reduction of other systems, methods, and sufficiency and/or advantages of the present invention. Those skilled in the art can obtain the following description and accompanying drawings. know. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , [Embodiment] Various embodiments of the present invention will be illustrated. When the accompanying drawings are accompanied by explanatory characters, the invention is invented in these embodiments. On the contrary, the complex 2, 'ί is not intended to limit this ^ m +,, "there is a lot of alternatives to the spirit of the application and the scope of the application of the scope of the application of the 方 丨 曰丨 乃 乃 乃 乃 乃 乃 乃 乃 乃 乃 乃 乃 乃 乃 乃 乃 乃 乃 乃= The singularity requirement is the current graph processing unit (Gpu) architecture = desired. Embodiments of systems and methods for reducing memory frequency and improving cache performance by compressing pixels are described herein. For example, a 2-axis lean material dust reduction scheme that reduces the memory requirements of an image processing system in determining visibility. Many embodiments of such a dust reduction method utilize the Z-axis lean material height-related characteristics within the primitive and provide A block-type data processing scheme for random accessing external memory data. Finally, these embodiments, from another perspective, can perfectly implement this compression scheme in the graphics wafer without changing the existing wafer architecture. When the corner is in a compressed block (that is, the compressed block contains one of the corners/one corner of the primitive), the compression becomes less efficient. However, the embodiment of z codec is efficient. (4) TT s Docket No: 0608-A41222-TW/F Inal/LukeLee/2007> 06, 〇6 9 200809688

Some shortcomings. A linear change in the value of 2 in a block is known, and this trait can be used as an incremental Z-compression scheme for the (four) rate. That is to say, the example refers to a compression scheme that stores a 2-value change amount. This final knot;: Memory storage requirements for less uncompressed Z-axis data. σ 里 / 2: Section is usually referred to in the image processing system (4) pipeline Ζ shaft - shell material. In addition, the gradient function with three variables changes the (four) vector of the ζ value in the flat direction and the vertical direction. For each:

The gradient vector clamps the error most likely to the direction, and this gradient vector corresponds to the rate of change of the direction. The triangle is installed; for example, the 2-axis data in the k-corner base is a surplus of '@this is a certain-three (four) base In terms of yuan, most of the sacral cultivating materials are superfluous. This means that in a few thousand pixels, only two gradients can be used to represent all the pixels. Therefore, the "(4) nature of the f axis f material is in -^ The triangular primitive has a fixed gradient. That is, the Z-axis data of all pixels in a certain-digonal base is usually located in the same plane. This allows the pixels in the same block to be linearly heterodyned. The S-mode obtains its Z-axis data. In general, this produces a very good entropy reduction for the entropy-based scraper. Figure 2 shows the basic component diagram of a z-axis data compression embodiment. The Z-decoder 202 of Figure 2 performs many of the functions of the z-compressed data. As shown, the z-decoder 202 may include a prediction error calculator 2〇4, a bit length calculator 206, a data encoder 208, a temporary storage 210 storing all z compressed data lengths, and a 212. These basic elements is the z-data compression. As long as the z-axis data in the compressed state, to take a second-order fast memory 214 will store data for later use as the z-axis. When compressed

Clienfs Docket No.: S3U06-0020 TT’s Docket No: 0608-A41222-TW/Final/LukeLee/2007, 06’ 〇6 10

The axis data is extracted by the access day ± dance 214 and J to = shrink: '_ from the second-order cache memory decapsulator 218. The data is further connected to the decapsulator 216, and then transmitted to the data compression axis data/, and then sent to the addition tree 220 to be restored to the original uncompressed path.

Like __ per pixel of the calculation, the program, the calculation - block (four) followed by the export of two reference ladders. , and yes. First, a reference pixel error is determined and stored until - prediction = difference, and the leaf calculates the prediction of the remaining pixels in the block. Starting up. This prediction error matrix is followed by the compression block of the bit length calculator 2 axis data.) The prediction error matrix is required (ie, the measurement error, the decision - the full length value is based on the largest 3 in the block - In the case of quantification, this binary value corresponds to pre =, when the prediction error is not zero. The data encoder 208 has the number of bits required for the ― and the difference matrix c code to process each large triangle. Pixel prediction error as

Hardware complexity. In order to achieve a balance to increase efficiency and at the same time,

Degree unit) is used to compress the data, &, and the total amount of the member (or the prediction error of one pixel in the block J, the block is 2, and the code is not zero and the competition is not zero. Large | The number of bits needed to store this prediction error, _ ;1, then the sentence

Length unit. The compressed resource index representing the encoded data is selected as the buffer 210 as the z-load; the length of the bucket group is stored J, and the encoded data is transmitted to the original. The compressed block of the data code is stored in the memory. Second, the value of the mobile phone is included in the z-light prediction error. The maximum J-month of the compressed block γ is the size of the parent pixel block.

Clients Docket No. : S3U06-0020 ί Packer 212 Move TT's Docket No: 0608-A41222-TW/Final/LukeLee/2007, 06 05 200809688 Move the entire light block to memory. In some embodiments, the packer refers to a column shifter. However, the chores of this packer are controlled by the city. At the packetizer 212, the complete z-compressed data ^ to the second-order cache 214 is used for later data recovery. As shown in Fig. 2, the data segment is also written into the second-order cache memory 214. ° When accessing the compressed data, 2 compressed data is obtained from the second-order cache 214 and sent to the Lai-Bai packet, 216. The skip sequencer 216 decompresses the trip sequence for each pixel in the block. The trip = column is then used in depacketizer 218 to determine the number of f-segments in the data. The data at this stage contains prediction errors. The final 'uncompressed prediction error matrix is sent to the addition tree for storage in the ·m difference moment (four)_start 2 axis data. The details of the z-axis data recovered from the error error barrier are as follows.

Figure 3A shows an embodiment of compressing the axis data within the block by calculating the prediction error. Stored in a compressed block "from the 2 degrees of the data, the value stored in the compressed state is the prediction error. Generally, the prediction error refers to the difference between the actual value and the predicted value. To illustrate: each case The compression algorithm is described here with an 8x8 pixel block. The second block can be called the compressed block size, and the compressed block size is not set to "^ at 8x8 pixels. Step 310 first finds that two can be calculated. Reference two reference pixels of the gradient. In different embodiments, the z-axis data may have different storage units, including but not limited to 24-bit z-axis data or 32-bit one-axis data. Λ For example, an 8x8 pixel map The block has the following values:

Client's Docket No.: S3U06-0020 TT^s Docket No: 0608-A41222-TW/Final/LukeLee/20075 06, 06 12 200809688 Μ 〇〇 〇〇 2〇1 g 02 2〇3 2 ό04 -ΊΟ '20 - ^21 Ζ. Ί2 Ζ.Ζ, '23 Ζ〇5 Ζ06 Ζ〇7 Ζ24 2 Ζ~ ζ. 25 Ζ26 Ζ21 Ζ30 ^〇! Ζ ζ 32 % -34 -35 -36, 40 Ζ41 24 ^Α-χ Ζ 7 7 ^ 2 43 ζ44 Ζ45 Ζ46 247 Ζ5° 2μ ^ ζ. - Qiao 3 Ζ54 Ζ55 Ζ56 Ζ57 60 261 ~^ ~Ζ' Ζ7〇271 ζ 65 Ζ66 Ζ67 ΖΎΙ Ζ. '13 74 Ζ75 Ζ76 Ζ77 In steps 320 and 330 In the middle, the loss of the tracing Τ $ test gradient dz / dx and dz / dy are included + 皙 out. The formula for the reference gradient is as follows:

Dz -=2·.. — 7 dx lJ dz -=2.. — 7 dy lJ and [1.0] [2.0] From this block, the prediction error of each pixel is derived (step 340): J , , and式式\ / 十0 Ζ(/:Ζ..., ^ = 1,7 = 0 σ,.

[3.0] 2,7 2/J~p i-〇yj = i (3⁄4 - zMJ) one (zM, wide %) 5"> w = 〇~-heart, -2), / = 0j>l (Z') Z/"·-〗) (z,.-u - z/-wi ), / > 〇, y > 〇 Figure 3B shows the budget error of different pixels in the block. In this case, if the block falls completely within the -three (four) primitive (that is, falls on the opposite side), the prediction error matrix may be as follows (step 35 "z〇〇0 1 0-1 00 0 0 -1 ο ο 〇0 0 1 0 〇1 ο 〇Z=〇〇〇0°〇0〇0 1 0 0 0 〇1 〇0 0 1 0 〇-1 ο 〇1 〇0 0 0 〇0 1 -10 0 0 0 0 0 1 The z value of the upper left corner of this prediction error matrix, z., is the reference pixel.

Client’s Docket No·: S3U06-0020 TT’s Docket No: 0608-A41222-TW/Final/LukeLee/2007, 〇6> 〇6 13 200809688

However, if the sum is 2, the VL^ difference matrix occasionally appears: the rounding value of the /O x-y axis. Finally, this prediction incorrectly predicts the error matrix 夕 +1 and -1 does not round the error. It is worth noting that it is located in a primitive. The value of the eve is 0, because this pixel tile is completely this compression algorithm is -

The purpose of the required external essay engraving is to reduce the amount of data transferred in the compression block but not to reduce external storage. All of the unrestricted data addresses and the 111 configuration space are determined by the size of the memory access quantization. Moreover, this compression algorithm is limited by the significant granularity loss due to this. Inclusion of two. When deriving the data encoding scheme in the example of A~, there are several factors that need to be λα ^ - a test is intended to contain a total of several 8x8 pixel maps I : = (for example, the square base 7 achieves maximum compression performance. The other 2 = reduces the hardware complexity. When there are many 8 χ 8 pixel tiles completely packed in S , , - angle base ,, the calculation of the prediction error matrix will be very similar = the example of the predicted rank difference matrix. Therefore, because The pixels in the pixel block are all in the same position, and the prediction error is mostly zero in the same plane. In some cases, the coding scheme can utilize the 13⁄4 level of the z-axis material in this architecture. In other words, by checking the z-axis (four) in the compressed block (for example, an 8jc8 block), the maximum prediction error range of the mosquito can be made. Therefore, the bit element required for the storage-pixel can be easily checked by the block 8-8. The z-axis data is determined. Other implementations consider that the hardware implementation of the data encoding scheme has a small complexity, which can lead to cost reduction. In order to achieve this, the first consideration is that the error must be configured. Number of bits (eg prediction error) Absolutely

Client's Docket No:: S3U06-0020 TT5s Docket No: 0608-A41222-TW/Final/LukeLee/2007, 06, 06 14 200809688 The value is greater than i), and this will depend on the number of quantization steps determined in advance to compress Reduce hardware complexity and cost when maximizing rates. Figure 4A shows an embodiment of a layer flow diagram above the number of bits required to store a compressed block. In this example, the bit length unit, or quantization level, is selected to be 4 bits (step 410). In some embodiments, this value provides the best balance between hardware complexity and compression maximization. The bit length unit (quantization level) is the smallest unit or section in which the compressed data block can be aligned. For example, suppose the bit length unit is 4 bits. If a piece of data is 10 bits long, then two extra bits will be added to this data block because the nearest 4 times the 10 bits is 12 bits. yuan. The compressed block of prediction errors for each stored pixel tile includes a fixed length field and a variable length block. That is, each compressed block always contains a block of the same length. In order to configure and indicate the number of bits required for a one-pixel prediction error, the following steps will show how to decide. First, the number of bits required to represent the z-axis data is first determined (step 420). Next, the "full length value" and the "half length value" are determined (step 430). The full-length value and the half-length value mean the number of bits greater than 1, which can be used to store prediction errors. The z-axis data here represents the maximum prediction error for a given 8x8 block. For example, the z-axis data here is 14 bits long. Because the bit quantization level is 4 bits, because the actual minimum length is 12 bits. Thus, the possible lengths are 12, 16, 20, and 24 bits. These lengths may correspond to full length values. In some cases, the prediction error may require a small number of bits to obtain a better compression ratio. In these examples, "half-length coding" may be used. Full-length values of 12, 16, 20, 24, and 24 bits can produce half-length values of 8, 8, 12, and 12, respectively.

Clienfs Docket No„: S3U06-0020 TT,s DocketNo: 0608-A41222-TW/Fmal/LukeLee/2007, 06, 06 200809688 l Bit, since the bit length unit is chosen to be 4 bits in this example. In step 440, a variable block of the compressed block may be determined. Each compressed area has a variable block because the size of the prediction error within a block may be greater than 1. Therefore, the full length value used to encode the pre-duplication error is The half-length value may differ for each compressed block f. Finally, in step 450, a fixed block of the compressed block is stored and a variable block portion of the compressed block is added. The fixed field of the compressed block includes There are sixty-four 丨-bit masks, and three 24-bits corresponding to the pixels z00, z01, and z1〇. Figure 4B shows a block of the compressed block representing the 8 χ 8 pixel block. The first block 460 includes 64 1-bit masks corresponding to each pixel in the pixel block, wherein a value of "0" indicates that the pre-error error is zero, and a value of "1" indicates a trip sequence requiring two bits. The second block 47 includes three 24-bits corresponding to the pixels ζ00, Ζ() 1, and Z 〗 Q. Blocks 46 and 470 form a fixed field of compressed blocks. The third block 480 includes a trip sequence of the remaining pixels (ie, pixels other than z〇〇, Z〇1, and ZlG). This field is a variable field, because a pixel may or may not have a corresponding trip sequence, and this occurs when the prediction error of one pixel is zero, so there is no need to skip the sequence. The last block 490 includes a long prediction error (i.e., the magnitude of the prediction error is greater than one). The demand for the second full length code or the half length code depends on the magnitude of the prediction error. The length of the compressed block to be encoded is determined. This length will be stored in two separate registers, and the metadata is required to describe the data length of each block. When restoring compressed axis data, read the length block before reading the compressed data to know in advance how much data to read. It can be known that if the length block corresponds to the uncompressed .2 axis data (for example 24

Client's Docket No.: S3U06-0020 TT^ Docket No: 0608-A41222-TW/Final/LukeLee/2007, 06, 〇6 16 200809688 The Z-axis data of the bit is expressed in units of six-bit length), which means data Not compressed. Use this feature to avoid the possibility of compressing data larger than the uncompressed state. Figure 5 is an upper flow diagram embodiment of the configuration of the prediction error and the corresponding hopping sequence in the encoding procedure. The bit configuration at this stage includes the variable block description of step 440 of Figure 4. In step 510, the prediction error for each pixel in an 8x8 compressed block (except for the three pixels in the upper left corner) is first compared to {-1, 0, 1}. In step 520, the prediction error "0" indicates that there is no error, so there is no additional bit configuration for this particular prediction error. If the absolute value of the prediction error is equal to 1, then only two extra bits are needed to represent this prediction error. However, in step 540, if the prediction error is not 1, 0, or -1, it indicates that the magnitude of the prediction error is greater than one. Therefore, the prediction error of this pixel is either full-length coded or half-length coded. These steps are repeated at step 560 until all prediction errors have been processed. The total number of required bits to store the prediction error will include the variable block of the storage block. The two-element configuration of step 580 indicates whether the prediction error size is one and whether a full-length value or a half-length value is required for encoding. The possible situation is summarized in Table 1.

Client’s Docket No.: S3U06-0020 TT5s Docket No: 0608-A41222-TW/Fmal/LukeLee/2007, 06, 06 200809688

Ή立元 罩 0 The prediction error is 0. Therefore, this pixel does not require additional fields (bits). 1 Predicting this prediction error is not awkward. Therefore, this pixel requires at least a 2-bit hopping sequence 00 to indicate that this prediction error is +1. Therefore no extra bits are needed (this pixel has no extra fields). 01 indicates that this prediction error is -1. Therefore no extra bits are needed (this pixel has no extra fields). 10 indicates that this prediction error size is greater than 1, and this pixel requires a half-long bit position. 11 indicates that the prediction error size is greater than 1, and this pixel requires full-length bit position 0. The prediction error of the first table pixel Ζ〇〇, ZG1, and ZlG is always greater than 1, and Z00 is the upper left corner of a pixel block. Reference pixel. Therefore, these three pixels use a 1-bit mask to indicate that a half-length or full-length value is used, and that the two pixels do not need to skip the sequence. Since the minimum half length is 8 bits, there are 24 bits (3 pixels x 8 bits) that represent these pixels, reducing the total length of the block. This 24-bit and 64-bit mask forms a fixed block of compressed data and is required to store all blocks. The trip sequence and the full and half length prediction errors constitute a variable block. If the second bit of the entire trip sequence is not a multiple of :, the extra bit will be appended to the block to align the ^ unit (quantized level).兀, and Figs. 6A and 6B are representative examples of the packer and the decapsular. Fig. 6A shows an example of a packer unit having eight wheeled ends. Packets crying, strings of independent blocks (such as independent input prediction error matrix Zhuang / even

Client's Docket No.: S3U06-0020 ) J Clothing: 3⁄4 to TT^s Docket No: 〇6〇8-A41222-TW/Final/LnkeLee/20〇75 〇6> 〇6 - 18 200809688 Avoid wasting excess funds / _ Λ # ', /, padding bits align the individual blocks to the edge of the group. The package is crying & the upper 70 column shifter is a °L field shifter (baiTel shi (four). - Generally speaking, 〃, 'used as a device for shifting the lean material / circuit. Column shifter can be used The software model broadcasts the arbitrarily numbered group = 11 in the single-operation, the data word bit, and thus the reduction can be avoided - the only time - column movement - the column shift n can be moved by the word group Position f time. In general, the shift value is called ^ (four) multiplexer to achieve a (four) clever round of the output, the next - multiplexer input. Each cry = every bit = 2 The difference between the packetizers described here is in the package: in the 4th position: 2, the control is controlled. For example, suppose the packetizer bit: then: Γ array 'if the input and output of the packetizer are _ segment to lose =: Two "(four) shifters will require nine stepped mother inputs: the private bit value is not less than the shift value of the previous - input. The multiplexer at the parent input is controlled by the next low effective bit (LSB) Every cultivator is crying, and the most blessed W m Shan Shi is not only shifting the data but also the private value of the reciprocal value. Therefore, in the parent stage, the low effective bit is lost and the lower position is allowed. Effect: Element. Therefore, the -bit pair on the original shift value: , X's pure 'this 2nd power shift performs the data shift on the column shifting crying two corresponding phase. (10) Decapsulation The device is used to restore the original state of zL mz «枓"(3) II (that is, decompressing the z-axis shell). The 6B diagram shows the unsealing of the white mouth ^ yang a unpacking the pirate using the same long sound as the packer The decapsulator calculates the shift value of each 钤^j- parent 1Q wheel-in terminal and then passes this value to the multiplexer. The parent-line input-output multi->I uses the same shift value.

Client's Docket No.: S3U06-0020 TT5s Docket No: 0608-A41222-TW/Final/LukeLee/2007 〇6 〇6 19 200809688 Therefore, it is not necessary to perform multiplex production on the shift value. 'More streamlined shifter set to cry, down -#. Taking the low-effective bits for reading in the final stage is used in the multi-guards of the Μ stage and so on. More about the state of the package and the decapitation of the sentence At 又 又 2005 2005 2005009387U Beixun can be disclosed in the US Patent Publication No. 5_3873 and listen to the milk number. ♦ (4) using the above Figure 7 to restore the original z-axis data left gold ~

Planted dark. Too, + in the upper layer of several embodiments, in the step, in the human 710, z compression, 1 r ~ 4 A dry axis shellfish compression block is taken out from the second stage cache 214. Next, the size of the compressed block is taken from the temporary, and the daily storage is 21〇% (step 720). Step 73: From ^, /V73〇, the house data is transmitted to the trip sequence unpacking state 216, and the trip sequence is unblocked white 1, and the unpacking packet 216 also reads each pre/shell j port error. 1-bit mask. All 1-bit masks, which are expected to have four prediction errors (corresponding to an 8x8 pixel block), are read. ^ , Bit 70 mask is used as the output control for the trip sequence unblocking state 216. The corresponding trip sequence can be solved based on the value of the 1 咖 t t 兀 mask. For example, if the money is one right, when the 1-bit mask of a prediction error is "Θ", it indicates that the prediction error g / ^ ^ > left Feng Wei and no redundant bits are stored to store the prediction error. . However, if a 1-bit π mask of one prediction error is read as "1", then there is a corresponding 2-bit hopping sequence for this prediction error. The trip sequence is then unpacked and used in the next stage (decapsulator 218). The unwrapped trip sequence is used in this phase to control the decapsulation bounds 218. In step 740, the depacketizer 218 unpacks and reconstructs the prediction error matrix from the compressed block according to the detachment bed ～ 叩 叩 姚 姚 , sequence, according to the 1-bit cool I# 〇 / — 兀 ' Zhuo and 2-bit The trip sequence 'read full length value or half length value. On the other hand, it is better to unload one of the prediction errors of the right.

Clienfs Docket No.: S3U06-0020 TT’s Docket No: 0608-A41222-TW/Final/LukeLee/2007, 06, 〇6 200809688

If the bit mask value is "〇", no extra bits will be solved. According to the value of the detachment, the Lai phase decapsulator will read more bits or continue reading the next one! Bit mask. For example, if the value of the skip sequence is "H)", the number of bits corresponding to the half-length value will be read to reconstruct the prediction error. On the other hand, if the value of the trip sequence is "(10)", no extra bits will be read because this specific value indicates that the prediction error of this pixel is small. This program will execute the money until 64 _ error values (corresponding This 8x8 pixel tile) is read.

The prediction error matrix built in the last 1 is transmitted to the final stage, and the original z-axis data is reconstructed in the addition tree using the prediction error matrix (step 750). In order to restore the prediction error matrix back to the original z-axis data, all values of this matrix will be calculated in a repeated manner from the moment _ upper left corner. In each of the examples, the z-axis data value ZlJ is reconstructed from the prediction error moment using the following equation. ZLlmax - ο)』, i = j = q ai/+Zi-U^ z=l?y = 0 Z/. Two W1, v (々+z~)+(z/-]n2J), / >l"· = 〇[4 〇] (^+2.^) + (2. Z.._2)? / = A + )+(zM,r z(一)灼), / > 〇, 7 > 〇~ Indicates the prediction error in the pre-difficult moment _ row] column, and ZLlmax represents the maximum prediction error of the entire matrix. Figure 8A illustrates an elementary block diagram of an embodiment of an image processing system 81A. In some cases, the image processing system may be, but is not limited to, any type of computing device such as a desktop computer or a notebook computer. Image processing system 810 may include a graphics unit,

Client's Docket No.: S3U06-0020 TT^ Docket No: 0608-A41222-TW/Final/LukeLee/2007 〇β 〇6 21 200809688=A certain function such as pixel coloring can be programmed to perform these functions exclusively/more complexly. . The graphic operation unit 81=free of the need to make the separation coprocessor other than the main alien, / as the specific operation of the specific operation that is set in addition to the processor execution, the 'graphic operation unit may release this ;::. Perform these tasks. In some cases, such as the graphics processor, the other computer actually executes on the motherboard of the computer system: the coprocessor of the early stage may be the central processor. However, the other should be accompanied by a graphics card interface 840 that may be a microprocessor graphics computing unit that may be present in the independent device. The interface card 812 and the cache memory are used to store the second-order 匕 解 解 解 824 814 814 fe 824. In some embodiments, the first-order cache 816 of the z-segment data, the bit length calculation cry, and the current j-w w 14 contain a prediction erroror 122. These modules are used in the following: the coder 820, and the package axis data, the z-decoder 814 is more compact. The reduced compressed z-stater 828 derives from the prediction error matrix the de-packetization stage 826 and the addition of the hop-off sequence depacketizer 216 and the de-packet stage as if the z-decoder 814 is a plurality of 包 "$ 214" . The system can be used or connected to a computer readable medium towel when it is implemented. In this context, the computer system "system or method magnetic, optical, or other physical stomach media can contain electronic, or method of use or connection of computer programs, including computer-related system-readable media for instruction execution systems," There are many computers, or devices (such as computers).

Clienfs Docket No.: S3U06-0020 TT's Docket No: 〇608-A41222-TW/Final/LukeLee/2007, 〇6 〇6 22 200809688 Basic system, including processor line system, equipment, or Zhuang' or other The system can connect from the instructions. A system that uses instructions or instructions to execute or use the computer-readable system of the present invention or to store, connect, transfer, or transport a computer-readable medium for use by a computer. . For example, electromagnetic, infrared, and infrared are not limited to electronic, magnetic, optical, or rich chains.

medium. The computer readable medium ~ - 糸, special, equipment, device, or electronic link 1 that transmits a line = the example includes the following: there is a - or a number of machine access memory (RA;) (: t 顺 电脑 电脑彳, ^ 八迅式), read-only memory (ROM) (electronic) / erasable stylized read-only memory (10) ROM, EEPR0M, or flash S memory) (electronic), 氺镛 ( ^Fiber (pre-learning), and portable CD-ROM (optical). ^ f

The δ Β 表示 表示 表示 表示 表示 表示 表示 表示 表示 表示 表示 表示 表示 表示 表示 表示 表示 表示 表示 表示 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可, special service H, multi-processing H computing device, mobile ^ personal digital assistant (PDA), handheld or tablet, embedded events, etc. For example, it is irrelevant for its specific use 'image processing two: specifically includes a ί-shaped interface 840, an arithmetic device 830, a plurality of round-in/round-out media, and a memory 834 'each of which is powered by a data oven"Axis; 1 face 832 838 ie τ? Connection. For example, display device 836 can include a plasma screen of a computer or a liquid crystal screen of a handheld device.

The central processing P computing device 830 can include a custom or commercially available processor,

Clienfs Docket No.: S3U06-0020 TT5s Docket No: 0608-A41222-TW/Final/LukeLee/2007, 06, 06 200809688

Or a plurality of processors intervening in the image processing system 810 to process crying, semiconductor-based microprocessors (in microchip format), giant M- or multi-ply integrated circuits (ASIC), numbers Suitable for -=, bit logic gates, and other known electronic facilities, including several (four) works that can perform operations in a variety of combinations.

...memory 8 3 4 may include volatile memory components (such as dynamic random access dfe bodies or static memory accesses, etc.) and non-volatile carvings (such as read-only memory, hard drives, cassettes, Combination of optical discs, etc.; = 834 usually contains - reverse operating system, one or several reverse libraries: type, simulation ", or difficult application, for many (4) = pseudo hardware platform, simulation operating system, etc. Those skilled in the art will be able to include other components that are omitted for simplicity. The alpha input/output interface provides several interfaces for data input and rotation. For example, when image processing system 81G includes - In the case of a personal computer, these two pieces may be connected to a user input device such as a keyboard or a mouse. When the image processing system 810 includes a handheld device (such as a personal digital assistant, a mobile phone), the component may be connected to a function button or button, touch 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Do something The scope of protection of the present invention is defined by the scope of the appended claims. For example, those skilled in the art will be aware of several methods for reducing the bandwidth requirement of image data transmission in this specification. For example, the image data including a plurality of pixel tiles is compressed by storing a prediction error of each pixel tile.

Client's Docket No.: S3U06-0020 TT's DocketNo: 0608-A41222-TW/Final/LukeLee/2007, 06, 〇6 24 200809688 The 'bit length of the pixel block' is encoded into the compressed Z-axis tribute. Compressing blocks, moving each compressed block to an output bus in a single operation, wherein each block contains a plurality of bits, and transmitting the data from the output bus to the cache for later restoration use. In some embodiments, the image data is 24-bit Z-axis data. In other embodiments, the image data is 32-bit z-axis data. In some embodiments, the z-compressed data further includes: identifying a plurality of pixel tiles entirely within a primitive, wherein performing the following steps for each pixel tile: identifying a reference pixel value z00 within a pixel tile, Determining a first slope value, determining a second value, calculating a linear gradient based on the first and second gradient values, applying the linear gradient to the remaining pixels of the pixel tile to calculate a prediction error of each pixel in the pixel image, And storing prediction errors associated with each pixel value. In some embodiments, the pixel tile includes a square of pixels. In some embodiments, calculating the linear gradient includes a horizontal component and a vertical component. In some embodiments, the horizontal component represents the differentiation of the Z coordinate data to the X coordinate data. In some embodiments, the vertical component represents the differentiation of the Z coordinate data to the y coordinate data. In some embodiments, the maximum prediction error value in a pixel block is the z-axis data of the pixel. In some embodiments, calculating the bit length further comprises: establishing a bit length value for determining a quantization level of the total number of bits stored in the one-pixel tile, and calculating a half-length value and a full-length value based on the quantized value. , wherein all fields of a pixel block include a variable field and a fixed block. In some embodiments, calculating the variable block of a pixel block further comprises examining the Z-axis data of the one-pixel tile to determine the largest prediction error value therein and configuring the number of bits based on the maximum prediction error value.

Client's Docket No.: S3U06-0020 TT,s DocketNo: 0608-A41222-TW/Final7LukeLee/2007, 06, 06 25 200809688 In the case of two members, the half-long-length coding produces a higher than normal rate. For the value, for the 纟 纟 ' ' ' ' ' ' ' 编码 编码 编码 编码 编码 编码 编码 编码 编码 编码 编码 编码 编码 编码 编码 编码 编码 编码 编码 编码 编码 ' ' ' ' ' ' 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素This 1 bit 兀, black s is Γ ', and set a 2-bit trip sequence, 1 in, 〇〇, +1,,,. 1, indicating that the prediction error is -... (4): two 1 + long-value coding 'and, u,, indicating that the prediction error requires a full-length value: to = in some embodiments 'moving each constriction f to - in a single operation Output bus is controlled by using independent control

Shifter. The 々I η embodiment includes a method for reducing the bandwidth requirement of image data transmission, including the transfer of data from the cache memory to a decapsulation unit.

The compression-contraction data is read to obtain the error value of each pixel in the pixel block, and the prediction error is transmitted to the addition tree, and the addition tree (10) is used to restore the defect. In one embodiment, the decapsulation unit is configured to perform the following actions: decompressing the ^ ^ mask of each pixel in the ς block, and based on these 〗 〖 bits, each pixel of the pixmap oil is decompressed. The skipping column, _: The tripping sequence decompresses this pixel tile (4) with the measurement of each pixel = f,. In some embodiments, the derivation further includes a page-based:: starting from the upper left corner of the prediction error matrix in a repetitive manner; the z-seat of the system pixel block of the round-bandwidth requirement has another embodiment including Reduce the tradition of image data, including a prediction error calculator to generate a

Clienfs Docket No.: S3U06-0020 TT5s Docket No: 0608-A41222-TW/Final/LukeLee/2007, 06, 〇6 26 200809688 A prediction error extension of the data - the length of the prediction error matrix The state is used to calculate the total number of bits in the reservoir, and the prediction error matrix is encoded into _, ,,, and horses for use in the σ 'Wang 钿 钿 block, and — 封 句 哭 】 — a single Move this pressure port in the difference. Earth,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, In each case, the Z coordinate data is 3

. ^ 1 vertical Z-axis shell material. In a 4b cream, you I ́ this collapsed area, including a fixed block and a variable block. The system includes a system for reducing the bandwidth requirement of the image data transmission, and a system for moving the 屙 (four) block from an external memory location and unpacking from the _ block to predict the error matrix, and adding one The ς tree is used to derive a pixel block. In each case of the upper shell, the de-encapsulation module is more t-hopped, and the packet is decompressed by the parent-tripping sequence in the error-compensation matrix and the de-packetizer is decompressed from the compressed block. This prediction error matrix is produced. In some embodiments, the addition tree is further used to derive the pixel block in a repeated pattern from the upper left corner of the predicted missed car. 0. Brief Description of the Invention Many aspects of the present invention may be best illustrated by the accompanying drawings. Interpretation. The elements illustrated in the figures are not to scale and are intended to clearly explain the principles of the invention. In addition, in the drawings, the same reference numerals indicate corresponding parts. Although a few embodiments are related to these illustrations, this is not meant to limit the invention in these embodiments, but rather, there are many possible alternatives, modifications, or equivalents. .

Clients Docket No.: S3U06-0020 TT’sDocketNo: 0608-A41222-TW/Final/LukeLee/2007, 06, 06 27

厶 WOV77UOO Fig. 1 shows a conventional view. Fig. 2 shows an embodiment of a ~2 z register. Fig. 3A is a diagram showing the basic components of the data compression embodiment. An embodiment of the axis (4) computes the prediction error to compress the z-instance map region within a block. 4A SI represents the budget error of different pixels within. Process diagram embodiment. Ye Sheng stores the laminar flow above the number of bits required to store the compressed block

Figure 4B shows L not intended. The block of the compressed block of the 48X8 pixel block is shown in Figure 5. The prediction error is configured in the middle and the corresponding hopping sequence 歹 6A and 6B @,. Figure 7 is a representative embodiment of the '2 packetizer and decapsular. Cheng Tu. , ', D 2 axis data in several examples of the upper 屛,, * δ Α 说明 说明 〉 曰 amp &;

Figure. For example, the component of the embodiment of the processing system 810 is shown in Fig. 8B as having an internal contention or... like the processing of "_", the shadow of the graphic operation unit 812 [main element symbol description] 100~block generator (10)~ ZL1 cache 108~ZL2 cache 204~ prediction error calculator 102~2X1 106~ZL2 202~z decoder coder 2.06~bit length calculator

Client’s Docket No.: S3U06-0020 TT^s Docket No: 〇6〇8-A41222-TW/FmayLukeLee/20〇7, 06, 06 28 200809688

208~ data encoder 212~packer 216~trip sequence depacketizer 220~addition tree 812~graphic operation unit 816~predictive error calculator 820~data encoder 824~second order cache 828~addition tree 832~ input/output interface 836~ display device 840~ graphics card interface 210~ register 214~ second stage cache 218~decapsulator 810~image processing system 814~Z decoder 818~bit length Calculator 822 ~ packetizer 826 ~ decapsulation phase 830 ~ computing device 834 ~ memory 838 ~ data bus

Client’s Docket No.: S3U06-0020 TT^ Docket No: 0608-A41222-TW/Final/LukeLee/2007, 06, 06

Claims (1)

200809688 f X. Patent application scope: 1. A method for reducing the bandwidth requirement of transmitting graphic data, comprising: compressing the graphic data by storing a complex prediction error of each pixel tile, wherein the graphic data comprises a complex pixel image a block; calculating a bit length of the pixel block; encoding the prediction error into a compressed block; moving each of the compressed blocks to an output bus; and transmitting the compressed block from the output bus to a cache Memory • Used for future data restoration. 2. The method of reducing the bandwidth requirement of transmitting graphics data according to claim 1, wherein compressing the graphic data further comprises: calculating a linear gradient of each pixel in the pixel block to determine the prediction error. . 3. The method of reducing the bandwidth requirement of transmitting graphics data according to claim 1 of the patent application, wherein compressing the graphic data further comprises: identifying each of the plurality of pixel blocks completely located in a primitive, wherein Performing the following steps on each of the foregoing pixel tiles: finding a reference pixel value Z00 in the pixel block; determining a first reference slope value; determining a second reference slope value; based on the first and second references Calculating a linear gradient; applying the linear gradient to the remaining pixels in the pixel block to calculate the prediction error of each pixel in the block; and Client's Docket No.: S3U06-0020 TT5s Docket No: 0608 -A41222-TW/Final/LukeLee/2007> 06, 06 30 200809688 and 4·如; Qisonglian's above prediction error. The bandwidth requirement is the same as the vertical component. ...the linear gradient mentioned above includes the method of reducing the transmission of graphic data by the method of the horizontal component, and the method of reducing the transmission of the graphic data, which causes the above-mentioned water to be a direct component: the maximum value of one of the above r is one The z-axis data of the pixel /, the frequency of the above-mentioned prediction error ^: ° Please refer to the method of reducing the transmission of graphic data in the first part of the patent scope, see the high-seeking method, in which the calculation of the bit length is more inclusive: The degree unit is used as a quantization level for determining the storage of a given pixel block, and the number of heart positions: According to the above quantization level, the calculation - the half length block value and the - full length block value η determine the above compression The length of the block-variable block, wherein the above-mentioned barrier block plus the fixed block of the above-mentioned compressed block is the total length. & For example, the method of applying for the bandwidth requirement of the reduced frequency graphic data of the seventh full-length rhyme, wherein determining the length of the above-mentioned block of the compressed block further comprises: checking - the graphic data of the given pixel block is Decide each pixel map Chenfs Docket No.: S3U06-0020 IT^s Docket No: 0608-A41222-TW/Final/LukeLee/20 075 06, 〇6 ' 31 200809688 One of the maximum prediction errors of the block; and based on the above maximum prediction The error is assigned to a complex number of bits. For example, the method for reducing the transmission of graphic data as described in claim 7 of the patent application, wherein one of the compression ratios generated by using half of the long-length coding is encoded by a full-length value. For example, the method for reducing the frequency of transmission of graphic data as described in the patent scope, wherein the prediction error encoding further comprises: a star, and a 1-bit associated with each pixel in a given pixel block. If the above prediction error is 遮, and the above right is 上述, the above bit is "^ If the above prediction error is not G, then the above-mentioned bit mask is set to ",";" The meta-separation sequence "〇〇" represents the above prediction error as + 1 ; 01" represents that the above prediction error is q, · "::" ίί The above prediction error requires a half-length code; and = the above table requires the full-length value Compilation. For example, the scope of claiming patents 帛 〗                                                宽 快 快 快 记忆 记忆 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快TT. Docket No: 〇^-A41222.TW/Fmal^^^ ^ 32 200809688 A prediction error for each pixel in a pixel block; transmitting the above prediction error to an addition tree; and ^ above: from the tree The above prediction error is derived from a graphic data. The bandwidth is required to be: T item 12 (4) (4) The unit is subjected to the following steps: solution/earth-one-bit mask, and each pixel in the pixel block described above ; /, "Bit % mask is related to the above column; the description of the 1-bit mask (4) is one of the above-mentioned pixel blocks, and the above-mentioned prediction error is related to the above-mentioned pixel κ block (4). A method for reducing the transmission of graphic data as described in item 12 of the patent scope of the patent, which derives the complex z-value of the above figure. Xiao Kai also makes the above prediction error to obtain a system for reducing the bandwidth requirement of the transmitted graphics data, including: - prediction error calculator, which is used to generate a prediction of one-z-axis of a pixel block The error matrix; the bit length of the juice is used to calculate the number of bits required to store the prediction error moment; a data encoder' is used to encode the prediction error matrix into a celebration block, and a packet For moving the compressed block to an external memory location. Heart and Client's Docket No.: S3U06-0020 TT^s Docket No: 〇6〇8-A41222-TW/Final/LukeLee/2007, 06, 06 33 200809688 The bandwidth needs 11; t profit t circumference 15th The reduction prediction matrix includes: a reference pixel, located in the pixel block, a first reference slope; a first reference slope; and a read prediction error, and the pixel map The residual value in the block is related to the basin, the error is applied - linear gradient to each value ^ ;; linear gradient system according to the above-mentioned first-reference slope and the above-mentioned second reference material count (four) 15 rhyme reduction __ data ^ See the two-seeking system, wherein the above-mentioned compressed block package and a variable block. A system for reducing the bandwidth requirement of the transmission pattern data, comprising: changing the nt device to move from an external memory location to the compressed region ghost, and obtaining a prediction error matrix from the compressed block. And an addition tree to derive a pixel block. 19. The system of claim 18, wherein the decapsular further comprises: , , and a tripping sequence decapsulator for decapsulating the packet to the trip sequence. Each value of the above prediction error matrix. 20. A system for reducing the bandwidth requirement of a transmission pattern as described in Item 18, wherein the addition tree is further calculated by a reverse square (the upper left corner of the prediction error matrix) to obtain the upper ^ Like ^ Cent's Docket No.: S3U06-0020 s Docket No: 〇608-A41222-TW/Final/LukeLee/2007J 06, 06 34