TW200809612A - Circular register arrays of a computer - Google Patents

Abstract

A stack processor comprises a data stack with a T register, an S register, and eight hardwired bottom registers which function in a circular repeating pattern. The stack processor also comprises a return stack containing an R register, and eight hardwired bottom registers which function in a circular repeating pattern. The circular register arrays described herein eliminate overflow and underflow stack conditions.

Description

200809612 IX. Invention Description: This application is based on the provisional application filed in June 2006, the weight of which is 60/81 8, 084, and the application is May 26, 2002. For the continuation of the declaration, the number and title are 11/441,818 and "Method and Apparatus for Monitoring Inputs to a Computer". The number 11/44!, 818 is a continuation of the application filed on February 16, 2006. The number and title are 11/355,513 and "Asynchronous Power Saving" respectively.

Computer. This application also takes precedence over the provisional declaration filed on May 31, 2006. The number is the priority application and the priority application filed on May 3, 2006. The number is 6〇/ 797, 345. All of the above-cited applications are hereby incorporated by reference in its entirety in its entirety in the the the the the the the the the the the the the Method and apparatus for stacking processors. ', [Prior Art] Stacking machines make processor complexity much lower than Complex Instruction Set Computers (CISCs) and make the overall system less complex than the Reduced Fingerset Computer (Rises) Or CISCs machines. Stacking machines do not require high-performance complex compilers or cache control hardware to achieve low complexity. Stacking 5

3019 — 8669 — PF 200809612 The machine also achieves competitive performance and superior performance at a certain price in most programmable environments. They are first successfully applied in the embedded control environment of = and they are better than other systems. Most of the previously proposed stacks are placed in the program memory, and the stacked machines are used to separate memory chips or even The memory area of the crystal carrier (.Chlp). These stacked machines provide extremely fast program squeaking capabilities and perform well in interrupt handling and function exchange. However, there is no hardware to detect stack overflow (〇verfi〇w) or owe. The stack overflow occurs when the available scratchpad is insufficient 但' but the data is continuously input to the stack, causing the scratchpad to be continuously written to the lower layer. When all the scratchpads are unused, a heap underrun occurs. This can result in the constant throwing of stacked content, resulting in meaningless or incorrect 4th. ··#,丨' Ten U Some other stacking processes use stacking 4 days and memory management, so that the “indicator” refers to the memory of the stack and will be marked with an error flag. It was proposed by Zahir et al. Then, ntNo. 6,367,005 exposes a scratchpad stacking mechanism that preserves the scratchpad used by the memory of the scratchpad stack to stack overflow = directly: available scratchpads. This scratchpad stacking mechanism It is also delayed == until the mechanism can reply to the appropriate temporary storage number when the stack overflow occurs, the delay will be terminated. The proposed method of USPatentN〇. 6,21 9 685 ^ stay results and - threshold Values are compared. However, this study does not result in a low threshold (which may produce an overflow) and just equals the threshold.

The result of 3019-8669-PF 200809612 is distinguished. + Another way to identify an overflow or under-production path is to read and write a hard flag to fly a person. However, the indicator must be - and any pointers and buffers read and written by the scratchpad can be executed, which reduces the processing speed. "Writing # is done after using the stacked shape in the memory to write the stack item or use one not: two bits: can ^ :: so reduce or eliminate the overflow or undershoot of the stack [invention SUMMARY OF THE INVENTION The object of the present invention is to provide a device and method, which: the data, the stack and the reply stack are not stacked in the memory body: and the hard-wired memory is used for a decentralized dedicated shift register. Another purpose of Tanaka Maoyue is to reduce or eliminate the occurrence of overflow or undershoot in the data stacking and back stacking. >, another object of the present invention is to place a bidirectional stack register between the single stack registers The length of the electronic connection is minimized to minimize: drive size and buffering. These and other purposes are achieved in the present invention, where the traditional heap is replaced by a register array, and the register array is looped. Repeated modulo 2, line work. This loop, repeat mode is implemented by using the associated bidirectional stacker, while the bidirectional stack register contains a plurality of single bit stacks, in alternating patterns (alternating patter) n) The data is read by electronic connection 3019-8669-PF 7 200809612, and the junction exists. This structure can avoid reading the empty register value from the outside of the stack. The above dual stack processor can be used. Used in conjunction with different processors interconnecting the computer array. For use as a stand-alone function processor, or internally, with several other similar processors or [embodiments] The present invention will refer to the figures and the elements indicated in the figures. The present invention has been described in the form of the present invention, and the present invention may be modified in accordance with the teachings of the present invention without departing from the spirit of the invention or the scope of the invention. The preferred embodiments of the invention and the modifications are intended to be illustrative only, and are not intended to limit the scope of the invention. 4 different applications, unless otherwise specified, as long as the invention is maintained The individual forms and components of the present invention can be ignored or modified, because the present invention can be adapted to A different application. Figure 1 is a general plan block diagram of a dual stack computer 12 for use in the present invention. In general, computer 12 includes its own RAM 24 and R〇M. Other basic components of computer 12 include R Repository heap 28 of register 29, instruction area 30, arithmetic logic unit (AL[J or processor), data stack 34, and decoding logic area % for decoding instructions. Computer 12 has data stack 34 and reply stack 28 The dual stacking computer. Those skilled in the art should basically be familiar with the stack 3019-8669-PF 8 200809612 operation of the computer 丨 2 as in this embodiment. In this embodiment, the command area is white A... - Some registers 40, that is, A temporary storage 40a 'B register 4〇b, with a month Γ and C register 40c. In this embodiment, the A register 40a is full! 8仂; offer seven, ηκ 8-bit 兀 register, while Β register 4〇b and C register 40c are all 9-bit registers. The hips are stacked on the computer in this embodiment. Both the stacking and the stacking of the shells and the stack are included in the temporary stack. These temporary storage operations are Θ4 kM % turn, repeat, or step-by-step. As with the brain, the data is not as good as the previous technology. It is accessed in the memory with stacking indicators. Figure 2 is a block diagram of the % A L a 18-bit 70 data stack according to the present invention.枓 枓 4: The upper two registers are six π times, 丨”, 々 δ 70 τ register and 18 bits are recorded as... The cycle is temporarily...: 18 bits - hardware temporary storage The device, the standard crying... The clothes are temporarily stored as ϋ, and there is no Τ and S temporary storage, ... combined with at least s register and s2-s9 speed circuit access, and can get :::::, speed In addition, the "sequence between the two systems is the same as the entire processor season"... This is the case to make the temporary storage - the sequence between the first and the first. This yoke example also includes a plurality of single bit shifts #, W bidirectional shift temporary storage bit 70 shift temporary storage benefits ^ the number of early 70 shift register and the bottom layer located under 5 temporary storage The stack is temporarily the same in the temporary storage state of each cover. In Figure 2, the device. As shown in Figure 2, /J is connected to the S2-S9 stack temporary link, so that the S shift register is connected to the S2 + in a sequential loop by the interactive S_S9 register.

3019-8 669-PF 9 .200809612 sases8—s9—s7+s5—S3—S” The sequential selection of the underlying stack register is operated in cyclic repeat mode. The connection line of the single bit shift register will not be scattered. More than three adjacent shift registers prevent the underlying shift register from being connected to the upper shift register with a long line. These shorter connections require only a small driver and minimize buffering. Embodiment (4) The ring register array uses eight additional stack registers. However, it is also possible to use multiple other combinations based on the four bottom registers. Figure 2 also shows the link & to S9 temporary storage. And the read line and the write line of the 7 and s register. Each single bit shift register of the bidirectional shift register n is connected to the S9 array of the underlying stack register. At one point in time, only one bit in the shift register is on ((10)) (the value is read, and the other bits are read to G. When the power is turned on, the T-bit register can only be initially One bit is i and the other bits are set to 0. In this embodiment, the top level of the shift register The meta refers to or reads S2, and writes to the adjacent register S4. The register τ and S and (4) Sg form a stack of ten lattices extending downwards because the bottom eight registers are -cycled Punches, so hardware wraps, not overflow or underscore. Although you can't expect to put more than ten scratchpads' and recall them all, you can always get the last stack from the bottom stack. The value of the eight scratchpads. This does not match the underrun error, because the program can always read the underlying: Feng, so that it is constantly getting eight characters, so this is the fastest way to copy eight ( Or 4, or 2, or 丨) characters. Similarly, because the stacking indicator allows stacking into any scratchpad, 3019-8669-PF 10 .200809612 so there is no stack overflow. It is limited, and if there are more than ten registers, only the contents of the last ten registers will be kept; every storage after the first ten registers will be written to the Sg register. One. This stack does not need, initialize, go to The previous position only needs to be declared empty at the beginning of the stack. Figure 3 is a detailed view of the data or reply to each register in the stack. Each 18-bit scratchpad includes 18 latches ( Latch), the latch is latched to the latch 17. There are 18 inputs through the gate (numbered to 丨7), each input is connected to the busbar through the gate and the read busbar is connected to 18 latches. There are also 18 The output passes through the gate (numbered to 17), each output is connected to the busbar through the gate and the read busbar is connected to the 8 latches. The input is controlled by the write control of the inverting amplifier, and the output is output. Pass: The gate is controlled by the read control of the inverting amplifier. Figure 4 is an 18-bit reply stack in accordance with the present invention. Reply to the stack upper register A 18-bit R register, and under the buffer: There are eight additional 18-bit hardware registers, labeled Ri_R8. As with the data stack described above, the eight temporary buffers in the lower layer operate in the interactive pattern in the form of a repeating loop in the state K1. The cyclic register array Ri-r8 can operate without the R register. However, combined with the R register and "can speed up the access of the circuit, and can optimize the timing, so have a higher cycle register array crash speed. In addition, this R register can be used as a memory and The buffering between the entire system is such that the timing between the #H register and the entire processor system is independent of each other. 3019-8 669-PF 11 200809612 This embodiment also includes a bidirectional shift register The number of shift registeres for a single n-bit shift register is the same as the number of the bottom stacks located below the r temporary storage, and the number is the same as "8. For example, the fourth Figure

No, the mother moved one yuan in the morning.

?丨D纠士 Do not link to the relative sound, P to h register. Two-way shift temporary storage η野m mutual 枵 堂 工 工 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 7 partial R, 4 partial L register of the sequential selection of the re-lending ceremony - the private mountain fruit known. The connection line of the shift register does not release more than three adjacent single-bit layer 亓 仞铋 仞铋 皙 皙 皙 皙 皙 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Save. These shorter wirings are σ 70 bits to minimize buffering. Although this lack of real driver 'and can be the most ..., this real example uses eight additional reply register, can also be used in the loop register of the main bean... Save the main /, he combined. A read line and a shift temporary hold crying ~ gas inlet line connection ^ R8 register. The mother of the W Suppression is connected to the stack register of the R8 array one morning. Μ, t, t, in the shift register only = bit 4 is on (read the value υ, while other bits turn on the power, the shift register can only have one bit at the beginning is now = he = is set to. In this embodiment, the top 4 of the shift register is either read to R1, and the adjacent register R of the write link is "in the invention, there is no overflow or Under-the-counter hardware detection. In the case of 2 Guard 3, 'pre-technical processors use stacking metrics or memory management: 1 way, so that when the stacking metrics exceed the stack occupancy, this error situation will flag Standardization. When stacked in memory 3019-8669 - PF 12 200809612 Overflow or under-bit may overwrite - stacking items or use to stack items. However, the underlying register of the present invention is a circular array, so Stacking does not fit or underpin. Conversely, the array of loops only wraps the scratchpad array. Because the stack is limited in depth, entering any data on top of the stack means that the underlying layer will be overwritten. Item data to data stack, or enter more than nine items to reply The stack will cause the bottom to be overwritten. The body must maintain the trace of the data items in the stack, and cannot input more than the amount of data that can be loaded by the heap. The hardware will not detect the overwrite of the underlying stack or the error. The flag is to illustrate that the use of software to process the underlying stack of loop arrays is advantageous 'and there are several ways. For example, software can simply assume that the stack is at any time, empty, when old When the data items are pushed down to the bottom layer, they do not need to be cleaned up. In the beginning of the program, it is assumed that the stack is "empty," it does not matter. Another advantage is that you can reload the used data. The bottom eight data items of these stacks can also be read or read and written in a loop. After reading the two data stacks, T Zhu 7 knees I μλ shells Tf i and s will be temporarily stacked from eight stacks. Two data items are copied in the sequential array of registers. After reading eight or more data, T and S will use the stacking winding, and then carry the data items of the bottom and bottom (4). In the case of back stacking, there is no limit. The number of times the eight data items are read. If it is not the stack error 'in the data or the reply stack', the group coefficient can be repeated eight, four, or two lattices, repeatedly from the stack. Although the embodiment of the present invention uses a dual-stack 18-bit processor data 3019-8669-PF 13 200809612, the present invention can also be applied to other bit number stacking and reply stacking as a description processor. Array, .., and Phantom 4 are related to the early double stacking process. The above-mentioned circular register array can also make «' computer array ig as shown. Computer array ig has multiple (in this case) For 24) Thunderbolt 1 9 r households by q 1J electric moon from 12 (in the array embodiment, sometimes referred to as "core,, or, section.lL _ ie point). In this embodiment, all of the computers 12 are placed in a single die 14ji. In accordance with the present invention, each computer 12 is a computer that operates independently. The computer 12 is connected to each other by a plurality of data bus bars 16 . In this embodiment, the data bus 16 is a two-way asynchronous two-speed parallel data bus. This is merely an embodiment of the present invention, and other ways of connecting may also be used. The computer 12e is one of the computers 12 and is not on the periphery of the array 10. That is, the four orthogonal neighboring computers of the computer 12e are 12a ' 12b ' 12c, and 12d. Here, the communication method between the computers 12 of the array 1 is explained in detail by way of an embodiment using the computer group 12a to the computer group of the computer 1 2 e. As shown in Figure 5, the internal computer 1 2 e will have four other computers 1 2 connected to each other by bus bars 16. In the following discussion, except that the computer 12 around the array 1 has only three directly connected computers, or the computer 12 in the corner has only two directly connected computers, the principles discussed will apply to all. Computer 12. Figure 6 shows Figure 5 in more detail, which shows only some computers 1 2 . In detail, these computers are computers 1 2a to 12e. Figure 6 also shows that the data bus 16 includes a read line 18, a write line 2, and a data line 22 of 3019-8669-PF 14 200809612 and a plurality of (18 in this embodiment). Data line 22 can link all bits of the 18-bit instruction word set in a bridging manner. According to the method of the present invention, the computer 12 of the computer 12 e can set one, two, three, or all four reading lines 丨 8 to ''high' so that it can be prepared separately from one, two Similarly, the computer J 2 can also set one, two, three, or all four of the write lines 20 to "high". When the write line 20 between the adjacent computers 12a, 12b, 12c, and 12d and the computer 12e is set to "high", if the computer 12e has set the corresponding read line 18 to "high", then A character will be transmitted from the computer 12a, 12b, 12c, or 12d to the computer 12e with the associated data line 22. Then, the transmitting computer 12 will release the write line 2, and the receiving computer 12 (in this embodiment, the computer 12e) will pull the write line 2 and the read line 18 to "1 ow". The subsequent action is to inform the sending computer} 2 The data has been received. In the embodiment of the present invention, as shown in Fig. 1, the computer 12 has four communication ports 38 for communicating with the neighboring computer 12. The communication bee 38 is a tri-state driver with a cut-off state, a receiving state (to drive a signal to the computer 12), and a transmitting state (to drive the computer to send a signal). If the particular computer 12 is not in an internal array (Fig. 5), such as a computer 1 2e, then the particular computer 1 2 will have at least one or more communications 埠 38 that will not be used for the reasons described above. However, the computer 12 next to the edge of the stamp may have additional circuitry for designing the exterior of the computer 12 within 3019-8669-PF 15 200809612 or the computer 12 so that the communication port 38 can be used as an external j/〇埠39 (figure 5). Such external 1/〇埠39 is not limited but may include USB (Universal Serial Bus), RS232 serial bus, parallel communication, analog to digital and/or digital to analog conversion, and Other possible changes. In Fig. 5, a phantom, computer (2) and associated interface circuit 80 is depicted which communicates with an external device 外部 using an external 1/〇埠39. Modifications of various formulas do not alter the value or range of the invention. For example, the present invention uses a special computer 12, and many or all of the forms of the present invention can be changed to other computer designs and computer-like computers. ^ & Although the present invention primarily discloses on the single-die 14, the communication between the electrical and the array 1 'the same principles and methods can be used or modified to complete the communication of other internal devices' For example, the communication of the dedicated memory of the device is the communication between the emperor and the device. The computer 12 in the array 1 is the same as the exterior, although the present invention can also be used in the single-stack acoustic crying θ^ state processor. &Processing, or 疋 more than two stacks, although the present invention has been disclosed above in the preferred embodiment, the recitation of the present invention, the (four) knowledge (four), without departing from the present = = : , when you can make some changes and retouching, so this hair; mouth ^ after the attachment, please be bound by the scope of the patent. ... vines

3019-8669-PF 16 200809612 [Simplified Schematic] FIG. 1 is a general plan block diagram of a stacked computer; FIG. 2 is a data stack according to the present invention; FIG. 3 is a single register in more detail illustrating a stack; 4 is a reply stack in accordance with the present invention; FIG. 5 is a schematic diagram of a computer array in accordance with the present invention; and FIG. 6 is a subset of the computer in FIG. 5 in more detail, and a connected data bus in FIG. 5 in more detail . [Main component symbol description] 1 0~computer array; 12,12a,12b,12c,12d,12e,12f~computer; 14~die; 16~ data bus; 18~read line; 2 0~write Line; 22~ data line; 24~RAM; 26~ROM; 29~R register; 28~ reply stack; 30~ instruction area; 32~ arithmetic logic unit; 34~ data stack; 3019-8669-PF 17 200809612 36~decode logic area; 38~communication埠; 39~external I/O埠; 4〇~ scratchpad; 40a~A register; 40b~B register; 40c~C register; 80~ interface Circuit; 82~ external device;

Ri to R8, S2 to S9~cyclic register; latch 0 to latch 17~latch; 3019-8669-PF 18

Claims (1)

200809612 X. Applying for a patent garden: 1. A stacked computer processor, comprising: a data stack, a slab, including at least one data register; and a reply stack, including 5 | and at least one reply a register; to accommodate an 18' wherein the at least one of the at least locations. Wherein the at least one of the data, wherein the reply is in the array /, each of the data stacks and the reply stack, the instruction characters of the bit. 2. The processing number as described in item 1 of the patent application - the poor material register includes the top layer of the stack (7) register. 3. If the processing number mentioned in item 2 of the patent application scope - the data register further includes the stack (8) register - the number _ 4. If the patent application scope is the first! The processor described in the item has a reply register including a top register (8). ^ 5. The processor stack as described in claim 1 further includes an array of hardware registers. 6. The processing stack as described in claim 1 of the patent application further includes an array of hardware registers. 7. The processor described in item 5 of the scope of the patent application functions in a cyclic mode. 8. The processor of claim 2, wherein the array acts in a cyclic mode. 9. A method of operating a computer processor, comprising: inputting a plurality of instruction characters to a complex instruction early element corresponding to the processor; and processing the plurality of instruction characters; 3019-8669-PF 19 200809612 wherein The method of claim 12, wherein the input includes filling all available instruction units. II. The method of claim 10, wherein the input further includes inputting additional instruction characters after all available instruction units have been filled. 1 2. The method of claim 11, wherein the input and the processing do not use an indicator of software execution. The method of claim 9, wherein the processing comprises not reloading the plurality of instruction characters, but repeatedly using the plurality of instruction characters. It is a computer processor comprising: a register array; and a shifter register; wherein the shifter register comprises a plurality of single bit shifters temporarily stored and interconnected using electronic wiring , and in which the plurality of single-bit π shifters are temporarily stored! The number of I is the same as the number of registers in the scratchpad array. The processor of claim 14 further comprising at least one register at a top level of the register array. 16. The processor of claim 14, wherein the register array further comprises a link (four) receive-read bus and an incoming bus. The processor of claim 14, wherein the register array functions in a cyclic mode. 18. The processor of claim 14, wherein the register array is stacked. The processor of claim 18, wherein the plurality of single bit shifter registers are interconnected by the electronic wiring in an alternating pattern. 2 〇 The processor of claim 14, wherein the processor is a data stack. 21. The processor of claim 20, wherein the register array comprises eight data registers. 2 2 The processor of claim 20, wherein the register array comprises a multi-element (mu 11 i p 1 e ) four data register. 2 3 The processor of claim 14, wherein the processor is a reply stack. 2 4 The processor of claim 2, wherein the register array comprises eight reply registers. 2 5 · The processor described in the second paragraph of Shen Qing patent scope, wherein the register array sentence #夕一. 干〜匕一一凡凡回四存存器. 26· A computer processor comprising: a register array; and a bidirectional shifter register, connected in a hardwired manner to the temporary storage array, wherein the two-way shifter register 1 comprises a plurality of single bits temporarily; j^ 55, ° interconnected by electronic wiring, and wherein the plurality of singles 3019-8 669-Pf 21 200809612 a number of 70 shifter registers and the register array The number of scratchpads is the same. Further, at least one register is further included in the top layer of the processor register array as described in claim 26 of the patent application. The shift register is as described in claim 26, and the processor register uses the hardware indicator for the register array. Furthermore, the processor read bus and the write bus as described in claim 26 of the patent application. 3. A processor as claimed in claim 26, wherein each of the plurality of single-bit shift register pairs is associated with a associated register of the register array. 31. The processor of claim 3, wherein each of the plurality of single bit shifts is temporarily actuated. ^ ^ 伹皙 裔 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , . Ma entered 33. The processor described in item 26 of the patent application is multiplexed with a single unit. Jiang Baguabian Temple Pingyi shift temporary storage is interconnected by electronic wiring to size the drive and the buffer. 34. As claimed in the patent scope 帛26, the electronic wiring is connected to at most one adjacent 乂Mi 乂 八 八 all adjacent one-bit shift register. 35. A processor as described in the patent scope, wherein the storage array comprises eight registers. 6. The processor of claim 26, wherein the processor is a data stack. 3. The processor of claim 26, wherein the processor is a reply stack. 3019-8669-PF 23