TW200809529A - Computer system with increased operating efficiency - Google Patents

Abstract

A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent processor. Processors can also be programmed to temporarily suspend a task to check for incoming tasks or messages.

Description

200809529 IX. Description of the Invention: [Technical Field] The present invention relates to computers and computer processing when a computer receives an instruction from an external source: 'Do not have a method and apparatus for executing an instruction, and the related two = the instruction The advantage of the device and method of the present invention that can be used for communication between the user and the computer that can be read into the computer by other computers is the ability of the " Use 曰μ + to combine the set-up computers in a single shaker. The operating efficiency of the chip is very high. It is expected to increase the operating speed by saving electricity::, so it not only improves the operating efficiency. Reducing heat production [Prior Art] The quality that is expected in the field of computer computing is the degree, and continues to find 1', processing speed in this field. Iron, and come here, the computer that is catching fast and the people who handle it, and who are familiar with this skill know the speed of adding microprocessor. (4) The proximity limit 1== Increase the processor to perform division of labor to increase the whole; Hunting is used by interest. The technology of the body-based speed is becoming more and more sensible. The use of multiple processors requires a large amount of communication between the devices. Therefore, blood data is processed. By; ° for most of the time used to transfer instructions = the execution of the parent additional instructions must: U processing delay 'Therefore, the traffic is also very important:::; Receiving the computer it and the hu:, oh °, the method includes storing the data or instructions to receive "and executing the instructions or operating the data. 3019-8670-pp 5 200809529 Similarly, in the traditional technology must not be busy with a job Note the computer. Even if the electricity seems to work, it may happen that it must make the computer leave the sensitive work request between the μ τ ^ ^, not for the yin ^ 匕 獒 for input to the computer, ;::ΐ1Γ The scope of the invention. In such an example, the computer may need to temporarily respond to the input and j: 〒 胸 = = will continue before the wheel or change its operation according to the input: even if the external input is For example, the same situation occurs when there is a potential conflict between the ALUs. For example, when receiving data and changing the state from the input/output interface, there are two effective methods for the first branch. Query (p◦(1) the connection 埠, including the state of reading the connection port at a fixed interval to determine whether any m is received is changed whether the status is changed or not, and the time and resources are better. In order to use two other work, the preferred choice is to use "interrupt,, when the interrupt is used, the processor can handle the job" and t input/output contig/spot by the received byte or state The fact that has been changed requires that the 2nd will send an interrupt request (IRQ) to the processor. Once the interrupt request is received, the current instruction will be terminated and the instruction will be placed on the stack and executed appropriately. Interrupt service routine (ISR). Once ISr is completed, the sect will return to the state before leaving. By this method, the processor will waste time to see if it needs to pay attention to the input/output device. Instead, the volume is to be used only to service the interrupt program. However, since τ is a heavy burden, in many cases it is not desirable to use the interrupt. 19—8670—PF 6 200809529 Every #interruption' computer must temporarily store certain data related to the work that it wants to complete before, load the data related to the interrupt, and then reload the previous work once the interrupt is completed. The data can be improved by using a system based on the fourth generation computer language. The fourth system can execute the execution sequence of at least one code, which is usually called the cooperative cycle method ((10) perative r〇 Mn), where f is executed using the central processing unit (the order of (10) is fixed, for example - the execution sequence 4 is always executed after the execution sequence and before the execution sequence $. = The line sequence is used to maintain the cpu and then by the call word Voluntary arrogance. Different from the need to store a large amount of content during the interrupt function, only one 35 data items should be stored in the function to save the original work. Each of the two execution sequences may have work that needs to be performed. If job 4 has a work that is stubborn and the job 3 before work 4 calls pna E, then job 4 will be woken up and work will be performed until it decides to execute again. Second right work 4 does not have the work to be performed, work 4 will pass control to work 5. ♦ T彳Λ: 4, Tian Hao call to perform the input / output function of the word %, you must wait for the greedy to 6 士, k to the wheel into the input / output, PAUSE is built in the input / output call. Predictability makes the code very efficient. The f-based cooperative loop method can provide each existing execution sequence with the opportunity to use the CPU, and its usage time is less than the preemptive multiplex (preemptlve ultitasker) to determine who is the next _ get (10) use right Execution of the %. However, specific work can be overwhelm or beyond the CPU.

3019-8670-PF 7 200809529 Effectiveness: By: Leakage current in small computer systems can be achieved in other areas of operation. While pursuing smaller devices, the insulation layer is thinner and therefore increased by two. In the near future, leakage can reach half of the effective power.休眠 Sleeping transistor can suppress leakage current. A dormant transistor behaves like a 'error' that isolates or cuts off the power and logic blocks when the logic block does not require a power supply. As disclosed in _Crepps on July 24, 2002 in ^nbedded.c(10), how to provide an effective power architecture, as disclosed in the text, can reduce the leakage current by 2_1〇〇〇. However, There are several disadvantages to using a dormant transistor. In the system, multiple factors must be considered to effectively use these transistors. The dormant transistor must have: a threshold voltage of two or more, otherwise the dormant transistor will have a large leakage current. Correct the (10)s process to provide a local critical voltage for the dormant transistor and a low-critical dust device for the logic gate. The additional power of the dormant cell will increase the area overhead and the dynamic power to turn the transistor on or off. In order to ensure the functionality of the circuit, the size of the sleep transistor must be carefully designed to reduce the voltage drop when it is turned on. The gates of the two switches at different times can share the sleep transistor. However, this method is not practical for large The circuit is therefore required to determine the best way to implement a dormant transistor in a large circuit. FarZenFaUah et al. , standby and active leakage current control, and minimization of CM〇s VLSI circuits, revealing other problems with sleepy transistors' including generating noise in the circuit and when used to ground the flip-flop from ground or supply voltage Data is lost when disconnected. Therefore, a device and/or method is needed to reduce leakage current and

3019-8670-PF 8 200809529 * For more efficient and less computer processor systems. SUMMARY OF THE INVENTION The steps of reducing transmission and reception are as long as the time and resources consumed by the data or command type are used for communication between computers. It is expected that the period of interruption can be reduced or eliminated. , Autumn 'expanded the function of the suspension to more than one system. It is obvious that the above-mentioned people think that in the prior art, the computer processor array disclosed in this document will not be minimized, and the heat consumption will be minimized. Do not perform the fall & d in the power consumer array. The processor that is being processed by the computer (also called idle and alert state. When the bit u or the core) does not consume any power, and a, a ', idle node or core line is the same as the phase The node or the connection attempt and the node will enter the startup state. After the execution enters the work, the lang point will return to the idle state. The blame is until the other work is transmitted to the node: the core is executing the core or the instruction and the phase The efficiency of the array can be achieved by the neighboring core and the execution of the core message. The core can be programmed to occasionally abort to check the incoming message 'instead of interrupting the execution of the core as in the case of a traditional computer system. If there is a waiting message, the core can be executed. After the suspension, the response to the incoming message is continued, and then the original work is continued. In order to make the objects, features, and advantages of the present invention more obvious and easy to understand, the following is a preferred embodiment and is accompanied by the accompanying drawings. DETAILED DESCRIPTION OF THE INVENTION The present invention provides a different embodiment to illustrate the features of the different embodiments of the present invention 3019-8 67 0~pp 9 200809529 L. The configuration of the various elements in the examples is not intended to limit the present invention, and the parts of the drawings in the embodiments are repetitive, and the descriptions in the case of A/r^^, ― are simplified, and do not mean different embodiments. The relationship between the above and other objects, features, and advantages will be more apparent, and the preferred embodiments will be described hereinafter with reference to the accompanying drawings. The purpose, features, and advantages of the present invention will become more apparent and obvious. The preferred embodiments are described in detail with reference to the accompanying drawings. The invention is not limited to the specific embodiments, and the components in the embodiments are not intended to limit the present invention. The relationship between the next will explain the operation of the operation and the alert state, and:: 2: and alert, or,,,,,,,,,,,,,,,,, Temporarily suspend or stop the material State. Same as Xiao, processor 1: two f: sorrow or sorrow is ready to start processing the state of the function as soon as it is instructed. When idle waking up, or, is activated, it is called when receiving processing instructions. 'called

3019-8670-PF 10 200809529 The manner in which the present invention is implemented is an array of individual computer processors. The figure shows a schematic diagram of the array 1G. The computer array 1G has a plurality (this embodiment has a "computer" computer 12 (in the array of this embodiment, there is a Japanese temple called a core or a node). In this embodiment, all of the computers 12 are disposed on a single wafer 14. According to the present invention, each computer 12 is usually a computer with independent computing power. The following will be described in more detail. The computer system is connected by multiple numbers (the number of which will be described in detail below). In this embodiment, the data bus is arranged as a two-way asynchronous high speed parallel data bus, but other interconnect devices may also be used for this purpose. The advantage of the present invention is that the array described in the embodiment is not only As the asynchronous data communication between the computers 12, the individual computers are also operated in the internal asynchronous mode. For example, since the distribution of the clock signals does not need to be 1 整个 of the entire computer array, a large amount of power is saved. Eliminating the eight-bucket clock signal avoids many timing problems that may limit the size of the array or other difficulties in the knife generation. Similarly, since the computer does not present: Therefore, when the computer does not execute the command, almost no power is used, and the asynchronous operation of the individual computer can save a lot of power. Those skilled in the art will find that the additional 14 in the wafer 14 is omitted for clearer visualization. Yuan#, Beb's 70. The additional components include power busbars, external connectors, and other common micro-processing hammers, which are not intended to limit the scope of the invention. e is a plural Wang Wang crying 9 9 τ + τ 疋殁 处理 处理 处理 处理 处理 裔 裔 12 12 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 12c and 12d of 12r w IN, which is only a dry circumference of embodiment 3019-8670-PF 11 200809529 of the present invention, and more than four adjacent processors may be used in other embodiments. Array 1G will be discussed in detail below. The communication between the processors 12 is related to the processing of the fl2a 2eii groups. As shown in the figure j, the inner processing (for example, 12e) can directly communicate with the other four processors through the bus bar 16. In the following discussion, except The processing of the 1G pin is 12, which can only communicate directly with the other three processors, and the processor 11 can only directly communicate with the other two processors. The above principle can be applied to the array. All of the processors 丨 2. Fig. 2 is a detailed illustration of a partial diagram, and only some of the processors of the processors 12a to 12e are shown in Fig. 2. As shown in Fig. 2, each of the poor The material bus 16 includes a read line 18, a write line 20, and a plurality of data lines 22 (in this embodiment, 18 data lines). The data line 22 typically transmits a octet command synchronously in a side-by-side manner. It is noted that all of the bits in the word processor 12 are mirror images of adjacent processors. However, whether the processor 12 is in the same direction or as a mirror image of an adjacent processor is not the focus of the present invention. In accordance with the method of the present invention, processor 12 (e.g., processor 12e) can set one, two, three, or all four read lines 18 to a high potential, ready to receive one, two, three, respectively. Information for all four adjacent processors 12. Similarly, processor 12 can also set all four read lines 20 of its —, two, two, or 疋 to a high potential. When one of the adjacent processors 12a, 12b, 12c or 12d sets the write line 20 between its own processor 12e to a high level, if the processor 12e has placed the corresponding read line 18 If it is set to high potential, then 3019-8670-pf 12 200809529 The processor 1 2a, 1 2b, 1 2c or 1 2d will transmit a word to the processor 12e through the associated data line 22. Next, the transfer processor 12 will place the write line 20, and the receive processor (12 in this embodiment will pull the write line 20 and the read line 18 low to a low level. Next, receive The processor 12e will respond to the delivery processor 12 informing that the data has been received. Values Note that the above description is not intended to indicate the order in which the events occurred. In the case of the operation, the receiving processor in this embodiment It can be written in the transfer processing crying U 停止 stop pulling high) write line 2. Before, try to set the write line two slightly: set to low. In such an example, while the transfer processor is releasing its write line 20, the write line 2 will be pulled low by the receive processor. It is worth noting that the data or code has been transmitted when the write line of the transfer processor 12 enters a high potential, so the receive processor (We) only needs to latch the data/code immediately. If the processor 12e attempts to write to the processor 12a, the processor i2e sets the write line set between the processor 12e and the processor 12a to a high potential. If the processor 12a does not set the read line 18 provided between the processor 仏 and the processor 12a to a high level, the processor waits for the processing 1 12a to set the read line 2G to a high level. When both the write line 20 and the read line (4) of the ^ are high, the transfer is located on the material: 22 waiting for the data to be transmitted. Thereafter, the #transfer processor 仏 releases the read line 18 between the two processors 12a and 12e, and the receive processor 12 (12a in this embodiment) sets it to a low potential. Whenever the processor 12 (for example, the processor 12e) is set to a high level in the case where the word eight write line 20 is not used, the write is as expected only 3019-8 67〇~ρρ 200809529 Wait until the request from the appropriate neighboring processing material is taken, unless the request for the data to be transmitted is set to a high potential (four)-like example to take the line u, whenever the processor 12 is not using power beaker). When at least one of the same situation of the disaster is set to a high potential, ^, ,, hard take line 18 wait until the write line 20 that is connected to the mouth of the selected processor is changed to Gudi The instruction word is transferred between the two processors 12. Under-same potential As mentioned above, many potential devices have the above functions at 12. The iron or method may cause the internals of the processor to be within the processor 12 as described in I. P pass-through non-synchronous operation (for data). That is to say, the instruction usually sends the method to the phase. When the instruction is fetched, it must be (4) until the execution of the instruction is completed (4) i action (or until the instruction is interrupted by , , reset, etc.). In the prior art, when the instruction is fetched or written, or when the read or write instruction is completed, the next instruction is executed (read _, to implement). ? The other day is to be refined by other entities. Figure 3 shows the block diagram of the first and second processors. As shown in FIG. 3, processor 12 is typically self-contained with its own RAM 24 and R〇M 26. , /, processor 12 is also commonly referred to as individual Ρ σ, in the wafer. The Weibe core, in this embodiment, is combined with a single ""; the other basic components of 2 are the return stack (with a "

28, the decoding area 30, the arithmetic logic unit (then) 32, the data stack ^, the decoding logic trough program 11 42 for decoding the instruction with 3019-8670-PF 14 200809529 耱. Those who are familiar with this technology are generally very accustomed to the operation of a computer based on a stack of computers. The processor 12 is a dual-stack processor with a sub-slope start, a 34 and an independent return stack. The first along the data stack 34 τ I θ - 、 、 、 、 、 、 τ τ τ 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及盥34a 〇" In the embodiment of the present invention, the test 10 is spoof 10 & Sapporo is 12 having four communication communication terminals 38 communicating with the adjacent processing, 12. Communication port 38 For three

The tri-state driver, | right M pH /, the buddy 4, the receiving state (driving the signal into the processor 12), and the pass-through sigh you (drive the number from the processor 丨2). Of course, if the specific processing 5|]? The open/negative state 12 is not located inside the array (Fig. 1) (e.g., processor 12e). Based on the above, at least the communication bee will not be used for the particular processor. However, these communication ports 38 adjacent to the edge of the wafer 14 may have additional circuitry (which may be placed in the processor 12 or external to the processor 丨2) so that the communication port 38 can be used as an external input/ The output port 埠39 (refer to the figure). Such external input/output ports 39 include USB ports, RS232 serial bus ports, parallel communication ports, analog to digital and/or digital to analog switching ports, and many other possible variations, but are not used The scope of the invention is defined. In this embodiment, regardless of the use of any type of additional or correction circuitry, the method of processing the instructions and/or data received by the additional input/output connection button is in accordance with the instructions received by the processing internal communication interface 38 described herein. And/or the method of operation of the data is 3019-8 670-pf 200809529. In the first drawing, the processor 12f having the associated interface circuit 8 (shown in the block diagram) disposed at the edge communicates with the external device 82 via the external input/output connection 埠39. The instruction area 3A according to the embodiment of the present invention includes a plurality of registers 40, including an A register 40a, a B register, and a p register. In this embodiment, the A register 4Ga is a full eight-bit register, and the beta register 40b and the register 4Gc are nine-bit registers. The ΐ/〇 register 47 (18-bit) is placed between the memory (ROM 26 and KAM 24) and the communication port 38. The τ will be described in detail in the sun and moon i/G register 47. The processor 12 of the example is used to execute native native forge an instruction, which is not intended to limit the cost of the present invention. Those familiar with the fourth-generation processor language understand that the complex: the withholding order (fourth generation) is built into the processing 2 according to the native processor instructions. The collection of fourth-generation words is called the dictionary (dicti〇nary). In other languages: it is also called the library (1)brary. Then, the processor will read eighteen from AM 24, ROM 26 or directly from one of the data bus 16 (Fig. 2):: The bit is described in detail. However, since the fourth generation: most of the instructions (QPeran (ess) ess instruction) directly obtain its operands from the stack Μ::34, the instruction length is usually only five bits, so that = (four) orders Can be included in a single-eighteen-bit instruction word, and a limited instruction set of three bits selects the last brother in the group. 4 shows the instruction word. 4 The instruction word 48 can include a schematic diagram of the instruction. It is worth noting that the actual data or a combination of the two. Instruction 3〇19~867〇~pp 16 200809529 The word 48 is composed of eighteen bits and five 。. Since this is a binary computer, each Bit 50 will be 〇 or 丨. As mentioned above, four of the eighteen-bit wide instruction words 48 The slot may contain up to four fingers + 52, which are slot zero 54a, slot one 54b, slot two 54c, and slot three 54d. The ten-digit instruction word 48 is always forever according to an embodiment of the present invention. Will be read as a whole. ms may have up to four instructions in instruction word 48 so the instruction set of computer 12 includes no job (n〇uction, no op) instructions for unnecessary or undesired use In the case of all available slots 54. In addition to the above registers, the command area 30 also has an 18-bit instruction register 30a for storing the currently used instruction word ", and an additional 5-bit operand is temporarily stored. _ is used to store the instructions in the currently executed special command word. : The above mentioned 'when the objection command is the 14-bit 66 system of the parent/sale 52 that does not require input or output, and is set according to whether the instruction is a read = write = command. The remaining bits 5q in instruction 52 provide the remainder of the particular transport to the instruction. In a read or write command, at least one bit can be used to indicate whether the data is to be read from or read from the data. That location is to be written to the location of the person 12 according to an embodiment of the present invention. Root "(The top data of data stack 34 is far from the T register = put it into the τ register) or other command area 3.: == The data or instructions in the example can be communicated in the way described here. Therefore, the instructions can be executed directly from the "rows 16".

3019-8 67 0-PF 17 .200809529 ^ At least one of the elements 50 will be used to indicate which port 38 is set to read or write. Subsequent operations are selectively accomplished by using at least one bit to determine the register 40, such as the scratchpad 40a, the scratchpad 40b, and the like. In such an example, the designated register will preload the data with the bits corresponding to each of the links 38 (again, the processor 12 with the potential entity can attempt to communicate with the external communication port (4) ( For example, memory _24 or _26)). For example, every four bits in a particular register 40 may correspond to each of the upper connected itching, the right connecting bee 38, the left connecting port 38, or the lower linking 38d. In this embodiment, the port 38 corresponding to the location 1 is used for communication. As described above, the embodiment of the present invention expects that the read operand can be set to at least 38 for single instruction communication. The following embodiment will assume that the processor 12e attempts to write to the processor: 2c 'to the extent that the adjacent processor in this embodiment can't pass through the processor... when executing the write command' The write line is set to a high potential (in this embodiment, the write line 2 处理器 between the processor ... and ...). _ _ ΛΑ 、, the right corresponding read line 18 is already at a high potential, Then, the data can be transmitted immediately from the selected data. Further, if the capture line 18 corresponding to the right of the communication connection 跑38 is not high, the processor 12e will stop the operation. Until the corresponding read line 18 will be described below, when the read or write is completed, the bit recovery operation is also performed when the intersection between the processor 126 and the corresponding write line ^; Line 18 will hold lines 18 and 2 respectively when held at a high potential of processing heart = 0. Weiyi 12 will release line 18 舆 20. In this embodiment

3019-8670-PF 18 200809529 The 'transfer processor 12e will hold the write line μ %拄6 a ; , . , to the potential, and the recovery processor... will maintain the read and line 20 at a high potential. . Next, the Receive Processor... will pull Lines 18 and 2() low to the upper level. Receive processor 12c may pull lines 18 and 20 low until the transfer processor releases, ^. Iron ^ ^ 18 than w κ > However 'because line 18 and 20 "" and flash lock until the lock is held high for the treatment of crying 12: line 18 with 2 ° release is possible to succeed line 18 and 2 . Pulling low to low power When the lines 18 and 2 in the data bus 16 are pulled low, the mother processors 12e and 12C will be w-shaped high. C曰 Set its internal response line 72 to be able to understand from the above description, no! 2c or the processor 12 ° first < from ... first write processing The first item takes the processor 12e, the operation is the same. The processing is based on the processors 12e and 12c are 19p. 19屯 white, the %%, and no matter which processing mgo 12c first, the first processor 12 will enter the state until the other processor After the above steps are transmitted, when the write processor 12=Sister here writes the read and read instructions from other viewpoints, the write is performed; J=the receive processor 12c respectively executes the ''processor 12e and the receive processor! 2C The ratio will enter the idle state. When reading #1D, the benefit of 12c white, the latter umbrella 18 and the write line 20 are both high potential fields, and the latter pushes the mouse almost immediately. It enters the father's easy reaction (ti*ansacti〇n reactive) ), on the other hand, the initial delivery can be until the first processor 12 can maintain the idle state until the younger one handles the pirate 12 ready to complete the procedure. The inventor believes that the main special gentleman of the response signal or asynchronous communication is effective. Politics. In the prior art, most of the devices

3019-8670-PF 19 200809529 Communication is controlled by the clock, and wa ^ ^ is not able to directly know whether the receiving device has correctly received the singularity or the error is checked by the sum operation. The correct receipt of the data, but not I, -y4 .. u. 曰, knowing that the completed message directly refers to the non-transportation device. Embodiments of the present invention are capable of providing the necessary response centroids in a manner of 1 + ^ to end and achieve non-gate abbreviations between devices to enable at least communication. Furthermore, the response state 2t is idle until a response state occurs. Of course, the response can be communicated between π 1 2 by separating the signals transmitted during the processing of crying 1 9 ° 12 (through the corpse Λ 内 , 内 枓 枓 枓 或是 或是 或是 or separate ^虎线), such a response signal does not depart from the scope of the present invention. What is missing is that 'because the embodiments of the present invention have many economic factors, the method should not use any amount of resources to influence communication. ^疋 Any of the above ranges: Sub-48 can include four instructions 52, and the entire instruction word 48 =, can communicate at the same time, thus providing the rationality of the small program in one operation, y, heart, . For example, most of the "F0R/NEXT" loops can be found in a single instruction word 48 for each phase. Brother 5 is a micro-loop 100. It is circled 1 Q Q and pot value 102 and _ command is called \ circle same 'has just command spoon rainbow (four) to command word 48 (Fig. 4) can include up to four instructions 52, single intrusion A /.丄 1 ilfi r ^ 4b / v 曰 7 to 48 may include three operational instructions 106. The command 106 can be used to execute any command that can be obtained, and the programmer may want to include it in the analog 100 circle. In the example of the general micro-loop 100, the micro-loop 1 0 0 transmitted from one processor, ϋ 12 to another processor may be read from the RAM 24 of the second processing write 12 Out or write

3019-8670-PF 20 200809529 A set of instructions for the RAM 24 of the second processor 12 such that the first processor i2 can "borrow" the available space in the RAM 24. The FOR instruction 1G2 will represent the number of iterations (iteratiQn). The value puts I back to the heap $28. That is, the value in the scratchpad 44 at the top of the data stack 34 is placed in the return stack quot"storage 29. In fact, it is usually set in the slot of instruction word 48. The three 54d #(10) instructions ι〇2 y are set in any slot 54. If the command 1〇2 is not set in slot one 54d' then the remaining command 52 in the command word 48 will enter the micro loop 1〇 Before being executed, the micro loop 1〇〇 is usually the next loaded command word 48. According to an embodiment of the invention, when the command 104 (figure 5) is set to the slot three 54d (Fig. 4) It is a specific form of ΝΕχτ instruction 1〇4. According to an embodiment of the present invention, it is assumed that all data in a specific instruction word 48 after a general τ instruction (not shown) is an address (f〇r/next lap Start Address > Regardless of whether the NEXT instruction 1〇4 is located in any of the four slots 54, the operands are the same (its The exception is: if two digits are inserted, it will be overwritten. However, since the NEXT instruction 104 de- ϊ ι ι _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The NEXT instruction in 54d is purchased with the 〇_ΝΕχτ instruction. The MICRO-NEXT instruction i〇4a uses the address of the first instruction 52 set in the slot zero 54a of the same instruction word 48. The MICRO-NEXT instruction 104a is also used. The value from the R register 29 (the value originally placed by the for instruction m) is reduced and then returned to the R register 29. When the value of the R register 29 reaches a predetermined value (e.g., zero) At the time, the MICRO-NEXT instruction 104a

3019-8670-PF 21 200809529 载入Load the NEXT instruction word 48 and continue operation. In the autumn, the value of the MICRO-NEXT command l〇4a from the R temporary storage 9Q, ,, Tian + 瞀存益29 is greater than the pre-= 勃 will be from its command word 48 slot zero 54a Re-execute the operation and execute the three fingers ♦ 52 set in slot zero to slot three. That is, in the embodiment of the present invention, the (4) (10)-deletion instruction always executes three operation instructions (10). Since all three achievable instructions are used in the "Machine" command (10) = - one or both of the slots 54 can be filled as needed. :? The intention is that the micro back to the old. . Can be used completely in a single place = 2. : The group can obtain the machine language instruction as the operation instruction ι〇6 The application of the loop is limited only by the programmer's imagination. When the entire micro-loop 100 is executed in the single instruction word 48: The processor 12 transmits the instruction word 48 to the neighboring processor 12, and the binary bus 16 will provide a powerful tool for the processor's resources when executing the instruction _= in conjunction with the processor 12. Use the state U to be included in the single-instruction word 48 of the small micro-circle _ can be directly in the processor 38 'also ^ from the receiving processor 12 communication connection 槔 入) / Ding Cong order (as contained in the instruction Any other group in word 48:). There are a variety of ways to use the micro-loop 1GG, when the processor 12 is on the face of the face, and then use the 2-to-be-storage to store the memory word of the adjacent processor 12: to the transfer instruction To the adjacent processor, telling it that it will receive the resource address, then increase the memory address, and repeat the generation (depending on the upcoming transmission)

3019-8 67 0-PF 22 200809529 Read the data, the first processor is combined... The θ hunting uses a similar micro-loop to inform the first state (here used to store the data back to the first-processing) When the data of (4) is directly executed by using the micro-return 100 architecture, when the storage: the quantity exceeds the small storage space built by each individual 12, the J: the other phase can be used. The neighboring processor 12 stores the excess amount: in the manner of (four) ux data storage, (4) the same loop 2 can be used to hunt: the other processing 1 12 performs some operations of the micro and circle 1. The neighboring processors of the device 12 share their computing resources:: store the result and repeat the predetermined number of times. It is worth noting that there are infinitely many ways to use the Ming U loop 100 architecture. The data or instructions can be ordered by the method described herein. Thus, the instructions can be executed directly from the data bus 16, that is, the instructions need not be stored in the RAM 24 and then executed in the call. In accordance with an embodiment of the present invention, Communication connection bee μ on: The word 48 and the instruction word 48 called from _ 24 or _ 26 will be treated as the same. The FETCH instruction is one of the available machine language instructions, and the η instruction is used in the scratchpad, the address on 4Ga. (4) Where to take the ΐ 8 digits. Of course, the program will provide the address of the A-scratch on the temporary storage. Since the A register is 4Ga $18-bit scratchpad, it has sufficient range to obtain. The address data can be generated between any potential sources of the capture instruction: there is a difference. That is, 'a range of addresses is assigned to ·, different addresses are assigned to RAM, and each connection# 38 and the external wheel 23 3019~867〇-pp 200809529 The input/output port 39 has a specific address. The mcH command will always capture the 18 bits set in the register 44. The important advantages here are The circle _ does not have the ability to capture. Therefore, the performance can be increased, and thus the power consumption is reduced. In contrast, the executable instruction is temporarily stored in the instruction register, and the 18-bit 兀The operation from 48 to the instruction register: there is a specific instruction. When the instruction is temporarily stored The processor 3〇a does not have an executable finger processor and will automatically retrieve the next instruction word 48. The position of the next instruction is counted by the program, 11, (the p register is the shirt. Here:: When fetching the sequence of instruction words 48 from RAM 24 or _ 26, = :4〇c usually increases automatically. However, such general rules

Also /, there are some exceptions. For example, instead of incrementing the counter, the ΤΠΜΡ + PA τ T JUMP or CALL instruction will load the data in the remainder of the current manned instruction word = the address of the current register into the P register after the jUMP or (10) instruction. When the address corresponding to at least one of the ports 38 is restored, the next instruction word 48 will load the instruction temporary number from the port 38 when the instruction word 48 is retrieved from the port 38. When it comes to the instruction register 30a, p 4Gg does not increase. Of course, m 40c will maintain the same connection itch address until a specific _ or (4) instruction is executed to change P register 40. . That is, once the processor 12 is slammed: find the next command, the computer 12 will continue to look for instructions from the same link 38 until it is told to find the pick-up (RAM 24 or ROM 26) to execute the next command word. As described above, when the current instruction word 48 does not have any executable fingers 3019-8670-PF 24 200809529, the next 18-bit instruction fetched by the processor 12 is placed in the instruction register 30a. Basically, since the remaining 18-bit instruction words after the JUMP or CALL instruction are used to represent the address mentioned in the jump or CALL instruction, the JUMP or CALL instruction (or some other here) There is no executable instruction in the current instruction word 48 after the instruction in question). In other words, the above steps are identical in many respects, i.e., several liver or CALL instructions are selectable to the port 38 rather than just to the memory address, etc., and are not intended to limit the scope of the invention. It is worth noting that processor 12 can look for the next instruction from one of ports 38 or from any port group 38. Therefore, the address provided is used to correspond to many connections. In accordance with an embodiment of the invention, when the processor is informed to fetch instructions from a port group 38, the processor 12 accepts the first fetchable command word 48 from any of the selected ports (10). If no adjacent processor 12 attempts to write to these connections 璋38. Either processor 12 will enter an idle state until the adjacent processor writes the selected port. Fig. 6 is a flow chart showing the above direct execution method 12A. The ', standard, operation flow is started when there is no executable instruction in the instruction register 30a. At this point, in the flow chart labeled "Capture Instruction," in operation 122, 1 f brain 12 will retrieve another - instruction word (notable,, 'finger page fetch,, - idle here The general idea is that the (3) instruction is not actually used. This operation is done based on the address in the scratchpad 40c (labeled as address determination operation 126 in the flowchart of the figure). If the address in the p register 4〇c is the RAM 24 or the biliary 26 address, then, from the memory, 126 3019-8670-PF 25 200809529: will be taken from the specified memory location - an instruction word 48.

Hi),,: The address in the I device is the connection bark is not the memory fish Beggar in the 攸 connection, the operation of 126 will be taken from the connection - the itching position to dig the next instruction word 48. In the above; = 2: The word 48 is placed in the operation of the "Operation Command". In the operation of the second register, in the operation of the instruction word 132, the slot 54 of the 7 sub-48 is referred to. The instructions in the system are completed in order. The operation of m _ 134 is judged according to the instruction of :: a Π (4) as a chat command or an instruction having the above other versatility. If 1 in the instruction word 48 is "peer, then the instruction word 48 is raised after the "loading of the P register" 136 is passed to the Zhan instruction (or other instruction): provided to the p temporary storage... And again back to the beginning:: the operation of sub-122 (as shown in Figure 6). If the instruction word 48 does not: the chat command or other instructions that can make the operation leave the general operation X connection 埠 address" judgment The next action in the 138 operation is determined by the connection from the port 38 or the memory address. If the previous instruction was fetched from port 38, then the scratchpad (10) does not change and returns to the beginning of the "fetch word" 122 operation. In other words, if the instruction is retrieved from the memory address RAM24 or 26), then the "fetch word" is completed 1 2 2 &gt; from 乂^ π,, Z's 刖, 6th In the figure, the operation of adding the p temporary state U0 increases the address in the P register 30a. The above description is not intended to describe the actual operational steps, but is merely a representation of the different judgments and operational results described in the embodiment of the invention 3019-8670-PF 26 200809529. This flow diagram should not be interpreted as requiring each operation to be performed in separate sequential steps. In fact, many of the operations in the flowchart of Figure 6 are actually done simultaneously. Fig. 7 shows a method for changing the processor according to the embodiment (4) of the present invention (4) &amp; $Fig. As described above, the processor U will enter the idle state when waiting for the input. As the invention is! The inputs in the embodiment of Figures 4 through may be from adjacent processors 12. Otherwise, the processor core 具有 1 having the communication port 38 adjacent to the edge of the chip 14 is disposed inside the processor 12 or adjacent to the processor 12 (so the communication port 38 can be used as an external input). / Turn out the extra circuit of connection 埠 39). In any case, the present invention additionally provides the advantage that the idle processing _ 12 is ready to be activated, and that the (four) line specifies a certain action when the (four) input is made. This process is also called worker mode (w〇rker m〇de). # Each processor 12 is programmed to jump when it begins executing instructions. An address, which will be the address of the first instruction word 48 that causes the particular processor 12 to begin its designated job. The instruction word can be set in the middle. Name Cold boot (4) After dsta (1), the processor 12 can carry a program, such as a worker mode loop program. The intermediate processor 12 and the H-phase loops at the corners are different. Moreover, some of them can have a specific work when they are activated in the relevant positions in the array 1G. Taking τ will detail the guardian mode loop. ', because such a feature can be applied to the Xu Ke Lei,, at the midnight eve, so the 7th figure shows the flow chart of the "failure method 15 。. As shown in Figure 7, but in the alert state" In operation, processor 12 will enter idle: state 3019-8670-PF 27 200809529 state, to wait for input from neighboring processor 12 (or at least one adjacent processor 12, up to four), at, The edge, processor 12 example may be an external input or a combination of other external rounds and/or inputs from adjacent processing w12. As described above, the processor 12 can enter the idle f state to wait for a read or write operation to be completed. In this embodiment, the Γ 2 is used to wait for some possible input, and it is assumed that the waiting processor will read the line 1 8 &gt; It is also a south potential, waiting for a write connection from an adjacent or external source, a Α π u Μ /, which is exactly what is expected. However, waiting for the processor 1 2 to be 1 ^ ^ ^ ^ 曰, the write line 20 is set to a high potential, so that the s adjacent or external source read device 12 wakes up H and (four) cut processing &quot; 12 o'clock Waiting for processing... is not intended to limit the scope of the invention. In the start operation 154, the device 39 has completed the waiting..., the processor 12 is either externally mounted, and is also transacti, so the idle processing number 12 is followed by the operation. If the owner is 48 ^ ii] ^ w ^ , and the code is the command word 4« to be executed, the processor 12 will continue to execute &quot;Yiyi is Bessie, then the processor 12 will be old and it can be current In the command word 48; = in the 列 列 column... command, the command in the loaded 乂 插 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54. If "will be located below - the command will start in continuous: two, use this method, then - enter. Process the wheel's choice" to handle the other at least one of the received wheels 10 Some of the internal predetermined functions, in conjunction with the array (such as the communication in the designation of the conventional technology) or the neglect of the description of the wheeled 7 diagram, act on the input I: to ignore the interrupt operation). In the first operation. It is worth noting that 3〇19-867〇-pp 28 .200809529 is that the input in some of the examples may not be so important, and in some embodiments may only be of interest to external devices attempting to communicate. A person who knows this skill knows that it will be helpful to use the above operation mode if it can be used more effectively and conveniently. When the processor 12 sets its at least one read line 18 (or write line 2A) to a high level, it can be referred to as a location, an alert, a state. In the armed state, the processor 12 is ready to immediately execute any command transmitted to the data bus corresponding to the read line 18 set to high potential or to react to the data transmitted on the data bus 16 . When the processor array (4) is obtained, any one of them can be set to the above-mentioned alert state at any time, so that any specified input combination will be driven to the action state. Since the interrupt will cause the processing to cry, store some data, load some data, etc. to respond to the interrupt request, because: It is better to use the traditional interrupt technology to get the attention of the processor. According to the present embodiment, when the processor is set to the alert state and is used to wait for input of interest, not only the single-instruction cycle is wasted at the start of execution of the instruction triggered by the input. It is worth noting that the processor in the alert state will actually be in an idle state, will not use power in the idle state, and will enter the alert state when the instant input is triggered as an action. However, even if the processor is not in an idle state, the computer may include an alert state without departing from the scope of the present invention. The alert state can be used for any sibling, in addition to traditional interrupt (software interrupt or hardware interrupt) techniques. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> Figure 3) Expected or necessary mutual 3019-8 67〇~pp 29 200809529. As shown in Figure 8, there are two separate flowcharts for processors 12f and 12g, respectively, in Figure 8, ie Used to indicate the nature of the coprocessor referred to in the present invention, except that when the interaction between the two is completed, each processor 12 has an independently achievable task. From an external input device or other location in the array... 2, the present invention also provides for the use of interrupts to process the input. As described above, the present invention allows the processor 12 to be in an idle, idle state to handle interrupts. The operation of the abort processor 12 is replaced. Because: at least one processor 12 can be used to receive input and return the input to the shore. A = processor m, completed here, enters idle and alert-like,,, and action ', (5) and, acts on the input (5) operating system and processor alert method 15 〇 "first embodiment related . However, 'due to this embodiment it is expected that the possible input between the processors 12f and 12g is that the processor 12f returns idle and MJ's. "The right does not need to be able to quit evil or other previously discussed modalities: Then the processor 12 is transferred to the other, and the communication between the processor and the processor 1 2 Go to + (4) g is in operation m. It is worth noting that

The Si slave (2) can transmit instructions, such as instructions generated by the processor 12f == the input of the device 82, or internally. In addition, the processor (2) can transmit two or more; Γ 12g, the data can be generated or hacked from the external device 82 inside the processor m. In addition, the + field processor 1 2 f receives the input from the external 3019-8 670-pp 30 .200809529 82. It is possible that all of these opportunities/processors are taken. The programmer is performing the main function, f η is executed by the shovel 162, and the processor 12g usually assumes that the processors 12 and 12 are both. However, if the program is looking for input, there is an occasional interaction in operation 166, then the "t Ji ^ #,|if ^ 设计 designer will occasionally have the processor I2g (4) have an adjacent processor attempting to communicate." Input? Π 168 168 is used to determine whether there is communication waiting for the second: = 12f has been initially processed for processing ... line write operation. If the work has been initial communication (Η), | w 1 〇, 攸 other Receive, operation 1 70 = communication will be completed. As shown in Figure 8, if there is no initial = (No), the processor 12g will return to perform its (4) function (10). fV enough other reception ', After operation 170, processor 12(4) will act on the input received in the "Input Active" operation 172. As described above, the programmer can cause processor 12g to use the instruction as a round, in such an example, processing The device i 2g will execute the instructions mentioned here. In addition, the processor 12g will be programmed to react to the data. As shown in Figure 8, after the operation of the input operation 172, the processor 12g returns to complete its main function (ie return to the "play main function" operation! 62). Of course there are more complicated examples. For example, some input from processor 12f will either abort its previously designated primary function and start a new function or simply abort to wait for further input. Those familiar with this art know that the possibilities of many reactions are limited only by the programmer's imagination. 3019-8670-PF 31 200809529 The value of thinking is due to the other Lu Tada w 1 . _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ However, it is worth noting that the processor 12, which is busy processing other tasks in the 1#, cannot be disturbed until its programming provides a 埠3δ for the input. Therefore, it is sometimes desirable to suspend processor 12 for other inputs. The concept of "stop" and its use method will be explained below. Each of the binders (10) between the two processors includes a plurality of data lines 22, a line 18, and a write line 2', which contain data bus 16 In addition to the poor material bus 丨6, ^ ^ ^ ^ ^ ^ 埠 38 also includes the handshake 2 = 1 signal. The data line 22 is set between two adjacent computers - bite: between. For example, during the RE (write) instruction, the sub or the exception may exist in the τ register 44 of the processor 12e, and then the processing of the 12 e into the green 9 π 7 I" «χ", the port is set Set to high potential. When the read line of the 3|12c is processed, the signal is sent to the processor, and the T register 44 is sent to the processor. After the transfer is completed, both the line and the write line 20 are set to a low level. Really here! The memory 40. When reading data, the data becomes an instruction. Or _2" when reading a message, the message can be data, the command is in the second... The command can be stored in the memory, so that the same processor 12 causes 'or ^ to save the connection itch 38 and let the difference =: 2 directly from The port 38 executes the instruction. If the P register in the processor 12 reads the instruction, the instruction is placed in the instruction, and the instruction is executed immediately by the 7 temporary holder 30a. Or treat the 3019-8 67〇~pf 32 .200809529 message as a data and point it to the link 埠38, see π 1 in the benefit 44. The right FETCH command bites the drought 38 'the FETCH command

Or the WL instruction points to ^6 as the data. If the JUMP is connected to 埠38, or the return command is at θ, fish 38 address, then the phase 7 of P6 is connected to the port, and the temporary storage is 4〇c. And treat the instruction as an executable code. "Considered as a view of t = 12; the message can be read from the shed, and then the message will be '', ', person. The routed message is interpreted as data and it is processed into the master. The T register 44 of the device 12, the intended receiver 'will interpret the message as a code (temporary access from P) and execute it. Therefore, if it is in the HA (definition:: The content of the A register is either (10) (defined as the contents of the read/restore A register 4〇a, and the addition of the eight registers) or 疋FETCH P+ (defined as read) The content of the p register 4 〇c of the memory is read, and the content of the p register 4 〇c is incremented by one), and the message is transmitted to the register 44 of the processor 12 to perform the reading. If the processor 12 reads a message from the scratchpad board, the message is transmitted to the instruction register 30a of the receiving processor 12. The first screen shows that the internal processor 12 is placed on the single chip 14. The array 10 is exemplified by 24 processors , 2, wherein each processor 12 has a plurality of pins disposed around the wafer 14. Each processor 12 has four ports 38. Not indicated as right, down, left, and up (rdlu). In Fig. 1, the processor 12e has four adjacent processors 12, wherein the processor 12b is disposed on the right side, and the processor i2d is disposed on the lower side. The processor 12c is disposed on the left side thereof, and the processor 12a is disposed on the upper side thereof. Even if 3019-8670-PF 33 200809529 = only side: two processing: 12: 'there are three adjacent processors and the corner processing L has four The proximity processing is such that the edge and corner processor 12 still has four ports 38 (also designated as RDLU). The first: a block diagram showing another array 10a. In the practice of the present invention: two columns have 24 Processor 12. Similarly, in the present invention: : The relative orientation of the benefits, 12 is set to ''mirror,'. Also two: "...the processor 12 of column 173 is the array 1〇a upper wide" The result of the 74 flipping 'make the lower joint Π;:, the fourth and sixth please... all paste the result of the 7-axis 178 flipping 'the right side of the right side of the array 38b array. Therefore, the processor N6, N8 , N1〇, N18, _, and N22 maintain their original rdlu direction, while processors n〇, n2, N4, N12, N14 And N16 is to invert the processor along the fork axis 174. Ν9, Ν11, ν19, Ν21μΝ23_&quot; ""78 flip (four) fruit' and the processors LN5, N13, N15 and N17 are along its X-axis 174 and the further axis 178 The result of the flip. Except for the processor placed at the edge of the corner of the array 1〇a, the result of the rotation will cause all right connections to be opposite each other, all the lower connections itch _ mutually opposite 'all left connections Oh, they are facing each other, and all the upper ports 38a are opposite each other. As will be discussed in more detail below, since the interconnect processor is a mirror image of the interconnect processor 12, the processor 12 is allowed to align and connect directly with the adjacent processor 12. In order to indicate that the direction of array 1 〇a has not changed, the inventors chose to use North, South, East, and West (NSW). Even after 3019-8 β7〇~ρρ 34 200809529, mirroring, north, south The east, west, and west directions can still maintain their relative orientations, and such an idea is very important during the routing from the processor 12 through the intermediate processor 12 to transmit messages to another non-adjacent processor 12. Direction (NSEW The system is located in the table in the ROM 26. Since the left port 38c and the upper port 38a are disposed on the periphery of the array 1a and thus are not internally connected to the array i0a, the two ports may be connected to the external input. /output port 埠 39 (figure map). When the column of the lower port 38d and the right port 38b and the block number are even, it is always connected: other processors 12. For example, the processor 7 has four orthogonal adjacent processes. The N6 is connected to the right port 38b, the N1 is connected to the right port 38d, the N8 is connected to the left port 38c, and the _ is connected to the port 38a. Figure 93 is a four node. Detailed illustration, also N7, N8, N13, and NU of Fig. 9 are marked with a right connection tan connection port 38, a left connection port 38, and an upper port 38&amp; The temporary processor 12 has a bit input/output temporary "47". The parent input/output register 47 includes an adjacent decision whether to perform a read from its port 38 or a write to the port 38: the figure is the input/output register of the processor 12. Bit_Β16 represents the read and write state of the processor 12. The input/output register 47 includes its communication fetch and write handshake state bits 5 〇. 5 β on β δ by reading these Bits, processor 12 can: two unique bits 5 〇. Interleave one of the adjacent processor systems 38 waiting to write its connection 4 3δ to perform a read operation (4), 'to be connected from its right adjacent processing Wait for the write

3019-8670-PF 35 200809529 Processor 12, then the processor 12 wheel ^ ^ ^ Input / Output Register 47 write line status bit will enter the zeta potential seven... 』, special delivery from a specific adjacent processing Write §fL interest. Similarly, the right adjacent computer of #4#様 waits to read the processor 12, and the input/output of the processing state 12 temporarily enters the south potential, and the waiting state is received. Look for the read message from the processor. The above steps will be explained with reference to the following examples of the ninth, nineth, and the following. Input/round of 卽7 轫 left _ ^ temporary storage, 47 represents right connection 埠 38b, and write status bits (minute, ^, ^, ^ 1D 兴 β15), in this embodiment The right port 38b is connected to Luli and is connected to the processing state N6. Bits B14 and B13 are read for the next connection 埠3 8 d (connected to _ ww λ energy phase _ , 埂 connected to process benefit N1) and written sorrow bit 兀, bit το B12 and B11 eight w丄士^ Knife for the connection 埠38c (connected to the treatment benefits N8) reading and writing skin energy one

Bits, bits N1〇 and N9 are the read and write status bits X of the upper port 38a (connected to the processing block M as N13), respectively. In this embodiment, 'bits A 16 to 9 always provide right, bottom, left, and top (read and write states of adjacent nodes of RDW. Next, Fu Zhidi 1. Figure for input/output temporary storage Another description of the device 47, in which a partial input/output register of point 7 is displayed. If the bit β ΐ 6 is high, there is a read request from the processor (4), and if β ΐ 5 is high, The write request ... 14 from the processor N6 has a read request from the processor N1 for high power, and the like. [7] As described above, the 'abort will cause the processor 12 to temporarily stop its processing work = hold the idle state to check the entry. Information or instructions. There are two cases here: aborting the routine. The first case occurs after the processor 12 is started from the previous idle state. The second case occurs when processing 3019-8 670-pf 36 .200809529 Execute the program but suspend the execution of the program to check the incoming message. N〇P (also known as no-op) is a no-job instruction, and is marked as dead four points (····) in the instruction code. Referring to Figure 4, Ν0Ρ can be used when it is not needed. Use some or all of the available slots 54. For example, in the message 'four, (···.) the material message header, to some extent by ^ it must safely drop the header (starting After that) and must also securely fix the I header (when the execution of the processor code has been executed or aborted), it may occur in both cases. Multiple messages must also be securely: from the same direction at the same time. When each message starts from four @Ν〇ρ, since the parent process H reads the same message header, it will not be too difficult to read at least two different messages at the same time. "Process II 12 can be specified as The main worker (wQrker) or: the production type, the processor 12. If other instructions are missing, the processor 12 is preset to the worker 'and performs the worker mode loop of the nth figure 2' The loop is set in the ROM. The worker processor 12 maintains a sleep or idle state until the start of the four-in-one loop _ is transmitted to the worker.... n uses the abort routine (Ρ Delete) worker mode returns 2QG When the worker processor 12 is in the idle state when the preset worker mode loop 200 is in the idle state, the four messages of the message header are treated as information in the read message operation 21. When the message arrives The fetch A instruction reads the words from the four adjacent processors 12 (the τ register 12 placed in the weiwriter processor 12) as data. It is read in the wake-up operation 2ΐι of the u-th image. These four will wake up the worker processor 12. The wakeup message will be 3019-8670-PF 37 200809529 will start the worker processor 12. As part of the work 200, the contents or address of the B register are preset Set/output temporary memory... So, read input/output =, mcH B instruction will read the contents of input/output register 47 to ==2 ^Review which 埠 ΐ ΐ is transmitted from which port of. In the "starting abort," operation 213, in order to prepare according to the previous step in the rounding: output of the contents read in the register 47, the check connection 214 'worker processor 12 is thus checked There is no processing activity. Next, there will be a step from the appropriate link, &amp; line message, step 215. After all the incoming messages are executed, '_ε will be at, end t stop 216 ends. At this time, the worker processor 将2 will become idle in the "sleep/idle" operation 217, and wait; to the arrival of other suffocation headers to start or wake up the worker processor 12. . All worker processors 12 are dormant and aborted. The field worker processor 12 is sleeping, waking up, and reading the input/output register 47 of all adjacent computers 12 whose write request is checked. The device 12 begins to abort and then executes the incoming message. There is a return (return;) at the 2nd end of the incoming message or a jump to the connection 埠 38. The worker processor 12 then returns to the abort routine. Program, check the input + lose Out of the other messages in the scratchpad 47 - the bit, execute the message, and then return to the worker loop and go to sleep to wait for more messages. The heart is being worked. The pAUSE will act as a wake-up and connection. The incoming message of 埠3 8 is regarded as dormant work. Figure 12 shows the second event using PAUSE, where processor 12 3019-8670-PF 38 200809529 Γ, in operation, for 22G. In "Read input/output temporarily The memory is processed as 12 and the input/output 4 is checked from time to time to check the entry status of the adjacent processor 12. If:: 47 indicates that there is an incoming message, then J will temporarily save 22%. Next, at, =, stop the processor 12 to be under; in the check for the input, the money, the money The processor 12 will check the port 38 indicated by the input/round-out buffer. If the designated port 38 has: :?" to determine the message indicated in operation 224, the processor 12 will Combine: = enter the program in the message, operation 225, including four tens. After Ding enters the message, is it, and finally the connection is completed? , judge the fall (10) to determine whether there are other connections 璋 38 waiting for the transmission of gas from ^ need to check the other connection itch possible input, it will return to the step ^ check the connection ” input operation. If the connection 埠 no input, Then, as indicated by decision step 224, in such a state, processor 12 will return to its original operation (step 22) without going to sleep. Then according to right, down, left, and up (RDLU) After sequentially checking the incoming messages of all the ports (10) and executing their code, the last port will complete the execution (step 226), and the processor 12 will return to step 22 to execute the original main function. The communication sequence processing of different processors is performed by the processor 12 group. If the neighboring processor 12 is not ready to receive the message, the transmission processor, 12胄 will enter a sleep state or perform other work and will need The pool input/output register 47 is used to find the message. However, most of the time when the group executes the different processors, the pass 3019~867〇~pp 39 200809529 sequence processing , processor 〗 12 only reads its connection port 且 38 and the adjacent processor &lt; 牧 坪 d δ. The processor can be > &gt; &gt; operation 38, then the film is taken to take all four • The genius 12 enters the rest of the country and can be used by any of the adjacent processors 12—# dormant sin until four f writes 4 亍 write, read run _ Tian Ru check input / output register 47 Becker processing benefits i2 need to check 12 to perform the write. After processing the volume, wake up which processor is in the state 1 2 is awakened to execute the Zhi can read A register 4〇a (: Bec... processor P temporarily The buffer 40c (f material or ... t register damage (data) or from the #本甘^ horse), all the % information of the capture register 40C means that it will execute all the messages including the four NOP. '... The processor 12 can be used as a worker without a m self-sufficiency&quot;, the maker's take all four ports 38, if the processor 12 is busy performing work (loops); sleep state. The first - work, "stop" (coffee) screaming to add four h to 1 to make a towel and it will read the main stop: _ material 38, and then return to be

The main work of Tit (Figure 12). The input/round-out pin connection 埠39 has a bit in the wheel-in/out connection pin and can be buried in the input/output port of the input/output port. It is read while being located. Some pins are read, only ^ / rain eight pins, and i read or write input / turn out the register ', 曰. After reading or writing or writing in the position of -&&gt; * + &amp;, the handshake is read in the input/output register 47. The pin connected to the unconnected = will not be able to be input. Temporary memory =: When the address including the wake-up pin is read, the processor will be 3019-8670-PF 40 200809529. The foot is awakened, but if the input/output register 47 is read, the processor 1 2 * will see the wake-up handshake. The wake-up pin is only connected to the wake-up circuit and not to the input/output register. Therefore, the pins must be read directly to determine if the processor 12 is woken up by the pins. If the value of the read pin is 0, then one of the other ports 38 will wake up the processor, &amp; This is how the code code in the sequencer processor works. The column processor has a serial input pin that is connected to the wheeled/output buffer that can be read as bit 70 (bit 兀! 7), but is also connected to not = pass = port 埠 ((10)p. (1) The handshake line. Reading the unconnected communication connection pin = 12 will be awakened when the data on the pin tells the processor 12 to write 5, phant〇mp〇rt. The R(10) code is After processing wake-up, the read pin is used to judge whether the processor is connected to the pin or the connection 埠 38. If the pin is low, n :::: output one, processing benefit 12 execution sequence start code ( B〇〇tc〇de). And you ^ start, read or write will pull high to read or write the handshake bit. When Γ 2 1 ☆ 12 pull high to read or write people to hold the bit On time (by the processing of the piano: there will be a bit lower), the processing... is awakened and: After the flag is sent, any read/write flag TL will be lowered. What is the name of the ?? 12 jumps to the RDLU (the address of the four adjacent ports &38 & the device will try to read and pull the flag, and then enter the sleep state of the no power mode when: processing state write this 逯 pile皇qQ七r, Tianhe# A car 38 to 〉, one and pull high write flag 3019-8 670-ρρ 41 200809529 日守,: There is a connection 埠38 flag will be reset and the first processor i2 Will be woken up. The same condition will occur when the processor 12 reads the address using the A scratchpad or the B register 40b and performs data manipulation or storage. The processing benefit 12 will go to sleep until four The data on at least one of the adjacent ports wakes up the processor. If the wake-up pin is treated as a portion of the address of the four ports 38 and the pin is not high, the processor 12 knows the processor 12 is cut by the other three adjacent ports. The sequence start in the sequence start processing of the second 12 is from the wake-up processor _ pin, the right pin is high potential, then the sequence is connected The foot loads the code and the code is started by the processor 12. It is recommended that the route is routed by using the xo packet and does not cause other conflicting methods. The XG represents the node of the execution server, The message of the black section of these paths is defined in _. The route of the message Should conflict with each other. PAUSE can make the message securely routed. The RAM servo buffer allows the incoming message of the node of the RAM feeder to be buffered at the point 6 m of m, so that it does not need to be backed up and the restriction is from the negotiation. Server message. This is the recommended routing path that does not conflict with χ〇. It is important to understand the multiplex cooperation between many processors 12. The group work is in port 38 and local memory. The job Η and pause will check all the entry executables in port 38 and treat port 38 as a work. The instructions on the port can be executed directly without loading into the processor's RAM. Even though the PAUSE routine 3019-8670-PF 42 200809529 between the multiprocessors 12 disclosed herein is related to the fourth generation computer language, the concept of the PAUSE routine between all the multiprocessors 12 can also be applied. To other programming languages. The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one skilled in the art can make a few changes without departing from the spirit and the scope of the present invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Computer Processor Array FIG. 1 is a schematic view showing an embodiment of the present invention. Figure 2 shows a detailed diagram of the sub-set of the computer processor of the first figure and the data bus of the i-th. Figure 3 shows a layout diagram of one of the processing modes in the block diagram /, and the music in the first and second diagrams. The figure shows a schematic diagram of the instruction word of the application according to the present invention. The figure shows a flow chart of a micro-loop according to the invention. Figure 6 shows the flow of the method for executing instructions from the port of the present invention. Figure 7 shows a flow of the method for modifying the processor of the present invention. Figure 8 shows a flow chart for the wake-up processor. The ninth input to the execution processor shows that the processing of the crying node in Fig. 1 uses the mirror 盥u ^ ^ car column, the processor or mirror and the adjacent processor total 3019-8 β7〇~ρρ 43 200809529 Figure 9a shows the details. Part of the figure with additional connections 埠 11th Figure 12 10 shows a portion of the input/round-out register. Figure 11 shows the flow chart of the worker mode loop. Figure 12 shows the execution map with the PAUSE routine. Flow of the processor [Main component symbol description] 10~Computer array 1 0 a~Array 12, 12a, 12b, 12c, 12d, 12e, 12f, 12g, N0-N23 Processor 14~ Wafer 16~ Data bus 1 8 ~ read line

2 0~Write line 22~Data line 24~RAM 26~_ 2 8~Stack 3 0~Command area 3 2~Arithmetic logic unit 34~Data stack 3 6~Solution

3019-8670-PF 44 200809529 38, 38a, 38b, 38c, 38d~communication port 40, 40a, 40b, 40c~ register 4 2~slot program 44~T register 46~S register 47~Input/Output Register 48~ Instruction Word 5 0~18 Bits 52~Instructions 54a, 54b, 54c, 54d~Slot 6 6~Bit i 4: 173~Second and 4th Column 1 7 4 to X axis 176 ~ second, fourth and sixth barrier 1 7 8 to y axis 3019-8670-PF 45

Claims (1)

200809529 X. Patent application scope: 1 · A general communication method, suitable for communication between a plurality of computer processors' includes: providing a first processor; providing a second processor; and transmitting the first processor Input to the second processor, wherein the transmitting does not interrupt the processing function of the first processor. 2. The communication method according to claim 1, wherein the input comprises a write function from the first processor to the second processor. 3. The communication method of claim 1, wherein each of the plurality of processors includes a plurality of communication ports. 4. The communication method according to claim 3, wherein each of the plurality of processors further includes an input/output register. 5. The communication method of claim 4, wherein each of the input/output registers includes a read and write status bit. 6. The communication method of claim 5, further comprising the step of checking the state of the above-mentioned t-buy and write status bits. 7. The communication method of claim 1, wherein the plurality of processors comprises a processor array disposed on a wafer. 8. The communication method of claim 7, wherein the transmission is achieved by a data bus between the first processor and the second processor. 9. The communication method according to claim 7, wherein the above-mentioned 3019-8670-pp 46 200809529 processing array also includes at least one internal processor 0 having four adjacent processors, 1 〇 如 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器 处理器It also includes an input/round-out status bit that is connected to the input/wheeling pin. 11 - a sharing method, applicable to work between a plurality of processors, comprising: providing a first processor; providing a second processor; providing a communication between the second processor and connecting to the first processor; From above: the first processor transmits an input to the second processor; the processor-processor receives the input from the first processor 'the processing function in which the transmitting does not interrupt the second processor. The transmission system described in item u of the patent application scope occurs when each of the j, ten, Chu-shi, and Tian Shudi processors performs a job. 13. The sharing method according to claim 12, wherein the receiving system is completed by going to μ, +, @^ and the sister: the above-mentioned second processor temporarily suspends the execution and is from the first processor In the above-mentioned transmission method, the sharing method described in claim 12, wherein the first processor transmits a round of input 4^^^, and further includes setting an input flag bit to a zeta potential. For example, the sharing method described in the patent application Fan Chu Chu ~ Gan Gudi 12, wherein borrowing 4 7 3〇19~8 67 0-PF 200809529, responding to the above receiving input by the first processor includes performing the above directly from the above connection The input code is received. 16. The method of sharing according to claim 15 wherein the code is not stored in a memory location before the code is directly executed from the port. The sharing method of the ninth aspect, further comprising: a software program, wherein the software program includes temporarily suspending execution of the second processor, and checking whether the connection material is There is an input of the first processor. The method includes: - the first processor transmits an input to a second processor, wherein the second processor is in an idle state during transmission; waking up the second The processor is configured to receive the input; the second processor checks an input/output register to determine a source of the input; and the second processor receives the second processor from the first processor The method of claim 18, wherein the method described in claim 18, wherein the method is performed by a software loop, is as follows: The method, wherein the awakening comprises a message header, and after waking up, the king removes the message header from 0 3019-8670-PF 48 200809529, wherein the reading and writing are performed. The state of the state bit 21 is as described in the scope of the patent application, including determining that the state of the adjacent processor occurs in the above-mentioned 22nd, as described in claim 21 of the scope of the patent application. The method of claim 18, wherein the reading and writing of the handshake state bit are pulled down. The method of claim 18, wherein the reaction occurs in the second The processor returns to an idle mode. 24. The method of claim 8, wherein the wake-up is caused by a multi-link read function. 25. as described in claim 18 The method of claim 1, wherein the waking is caused by a pin. The method of claim 1, wherein the receiving comprises reading the input as data. 27. The method of claim 1, wherein the method is set in a ROM. 28. The method of claim 27, wherein the method is a partial startup work in the ROM. 29. A computer readable medium for storing a code such that the electronic device performs the steps of claim 18 of the scope of the patent application. 30. A communication method, suitable for communication between a plurality of computer processors, comprising: providing a first processor; providing a second processor, wherein the second processor is located in a police 3019-8 67 0 - PF 49 200809529 ???but idle state; for each of the above plurality of computer processor providers;, input/round-out temporary storage of the first processor to transmit an input to the first port of the transmission system to enable the first-to-one processor , the sergeant k 罘 处理 处理 处理 处理 处理 ; δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ . 31. If the scope of patent application is 3rd. The communication, ..., the external item takes the input/output temporary packet of the second processor:, and determines whether additional input is transmitted to the second location ^=two people perform the above additional with the second processor Input. ... and 32. The communication input as described in claim 31 of the patent application is derived from the third processor. , the upper middle 33 · a processing system, including: · two computer processor array, each of which further includes: an input / output register; a communication port 设置, set on the four sides of the processor a transport: 'used to transmit-input to other of the above processors; and 妾 妾 来 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 :: :: :: :: :: :: :: :: :: :: :: :: :: :: :: :: :: :: :: Determining the source of the above input; and the actuator 'each of the above processors receiving the above input can return 3019-8 67 〇-pp 50 200809529 should be input as described above. 34. The processing system of claim 33, wherein: the transmitter comprises: a first port, disposed on a first processor 2: the input of the input 'the first connection system and the It is expected that the receiving processing is adjacent, and the receiver includes a _#Ii#lu, ... the —-connect 埠'4 is placed at the expected reception, and the second router is adjacent to the first processor. 35. The processing system of claim 100, wherein the receiver further comprises a noisy ... σ m /, and the upper sputum is transmitted to the second input of the second ligature. 〇 connection - 36 · if applying According to the processing system described in Item 33 of the patent scope, the g6, the crying, the, the middle, and the upper middle state of the processor may suspend the first reasoning to determine whether an input is for processing. Transmitted by the second processor. 37. The receiving processor described in the first paragraph of the patent application is directly from the transmission, 4*,,, and the first one. As stated in the application for patent scope, item 33 The transmitter can adjust the above-mentioned wheel, first, and then receive the processor. ^ k * is transferred to - non-adjacent connection 3019-8 670-PF 51