200807711 九、發明說明： 【發明所屬之技術領域】 本發明有關一種半導體裝置及其製造方法與改善方 法’特別是有關一種MOS電晶體元件及其製造方法與改善 汲極電流之方法。 【先前技術】 隨著金氧半導體電晶體(M〇SFET)朝向微細化尺寸之 發展，進入到深次微米時代，例如65奈米（nm)以下之製 私，對於MOS電晶體元件的驅動電流(drive current)的提昇 已顯得日益重要。 已知有使用應變矽（strained silicon)的概念增加電洞或 電子的遷移率（mobility)，以增進金氡半導體電晶體元件之 性能。例如，利用矽鍺層的晶格常數與矽不同導致當矽磊 晶在矽鍺層上時產生結構上應變的原理，使鬆弛的矽（si) 鍺(Ge)層成長在絕緣矽(801)的基底上或傳統的矽基底上， 再於鬆弛的矽鍺層上成長矽磊晶，形成應變矽。由於矽鍺 層的晶格常數(lattice constant)比矽大，這使得矽的帶結構 (band structure)發生改變，而造成载子移動性增加。 另外，亦有使用選擇性磊晶成長方法，於閘極形成之 . 後，在源極7汲極區域中嵌入摻雜鍺，形成受壓擠的應變矽 6 200807711 的電子遷移率。或在N刪製程中進行 應鐵相轉性Μ以祕/錄11域巾，形成技伸的 、’以增進電子遷移率。 顯示複數個習知之題電晶體元件之頂視示意 CMOS __顯示第1圖中沿著ΑΑ’線段的剖面示意圖，以 一 兀件結構做說明。CMOS半導體元件丨包括一半導 體=，其具抑層12，铸縣底包括有—主動區Η 及1^離區16，隔離區16圍繞主動區13以將主動區予以 電絕緣。1極結構，設於主動區13上。_結構包. H邑彖層18、一閘極電極層20、及一間隙壁22。主動 區可包括-摻雜井14或15。因此，其通道寬度即為閉 ，電極層與主動區交疊時之寬度，亦即，此種習知M〇s電 晶體兀件結構之通道寬度係侷限於主動區13的寬度。 由上述知道有許多增進載子遷移率之方法，例如，第 3圖顯示另—習知之M〇s電晶體元件之剖面示意圖，其進 一步具有自對準金屬矽化物層25及接觸洞蝕刻停止層 (contact etch stop layer，CESL) 2!。藉由應力的施加，使半 導體基底上的通道產生拉伸或擠壓的應變，而改進遷移 率。然而，就目前改良载子遷移率的技術而言，其通道之 大小，終究仍遷就而侷限於既有的技術極限所製得的元件 尺寸大小’例如微影、飿刻的極限及製造淺溝槽隔離結構 7 200807711 時填溝的極限等。 因此，仍需要一種MOS電晶體元件及其製造方法，以 較習知技術更進一步增進元件性能。 【發明内容】 本發明之目的係提供一種金氧半導體(MOS)電晶體元 件、一種製造MOS電晶體元件之方法、及一種改良MOS 電晶體元件之汲極電流之方法。本發明之MOS電晶體包括 一磊晶層位於閘極結構與半導體基底之主動區之間，並且 磊晶層的一周邊部分覆蓋在隔離區的一周邊部分的上方， 使得閘極下方的通道寬度能較原本的主動區寬度還寬，因 此，能使没極電流增加。 依據本發明之MOS電晶體元件，包含有一半導體基 底、一閘極結構、及一選擇性磊晶層。半導體基底包括一 主動區及一隔離區，隔離區圍繞主動區以將主動區予以電 絕緣。閘極結構係設於主動區上。磊晶層是位於主動區與 閘極結構之間，並且磊晶層的一周邊部分係覆蓋在隔離區 的一周邊部分的上方。 依據本發明之製造MOS電晶體元件之方法，包括下述 步驟。首先提供一半導體基底。其次，於半導體基底中形 200807711 成一隔離區，俾界定出隔離區與一主動區，其中，主動區 係與隔離區相鄰且經由隔離區而電絕緣。接著，進行一選 擇性磊晶製程，以於主動區表面上形成一磊晶層，同時磊 晶層橫向成長而延伸至隔離區之周邊部分之表面上。然 後，於主動區之半導體基底中形成一摻雜井。於磊晶層上 形成一閘極結構。最後，於閘極結構兩侧之摻雜井及磊晶 層中形成一源極/汲極區域。 又，依據本發明之製造MOS電晶體元件之方法，包括 下述步驟。首先，提供一半導體基底。其次，於半導體美 底中形成一隔離區及一摻雜井，並使摻雜井被隔離區圍 繞。然後，進行一選擇性磊晶製程，可以於摻雜井之表面 上形成一磊晶層，同時磊晶層橫向成長而延伸至隔離區之 =邊部分之表面上。，然後’於蠢晶層上形成—鬧極結構。 最後，於閘極結構兩侧之摻雜井及磊晶層中形成一源極/汲 極區域。 依據本發明之改善MOS電晶體元件汲極電流之方 法’ MOS電晶體元件係包括—半導體基底及—閘極結構， 其中半導體基底包括-崎區及一主動區，隔離區圍繞主 動區以使其電絕緣。此方法包括下述步驟。首先，於:成 隔離區之後及形成閘極結構之前，於主動區上形成一選擇 性磊晶層，並使磊晶層橫向成長而延伸至隔離區之周邊部 200807711 分之表面上，藉以增加M0S電晶體元件之通道寬度。 【實施方式】 依據本發明之MOS電晶體元件，可為NMOS、PMOS、 或CMOS。第4圖顯示複數個依據本發明之M〇s電晶體元 件之頂視示意圖，第5圖是顯示第4圖中沿著BB，線段的 剖面不意圖，以CMOS元件結構做說明。其中相同的元件 或部位仍沿用相同的符號來表示。需注意的是圖式僅以說 明為目的，並未依照原尺寸作圖。CM〇s電晶體元件丨〇包 括一半導體基底。半導體基底包括主動區13及隔離區16, 隔離區16圍繞主動區13，以將主動區13予以電絕緣。一 閘極結構，例如包括閘極絕緣層18、閘極電極層2〇、及間 隙壁22，没於主動區13上方。一遙晶層24位於主動區13 與閘極結構之間，並且磊晶層24的一周邊部分24a係覆蓋 在隔離區16的一周邊部分的上方。 於CMOS電晶體元件10中，半導體基底一般可包含有矽層 12 ’例如石夕基底或者是石夕覆絕緣(仙⑺卜如丨仍业⑽，SOJ)基 底，此並無特別限制。隔離區16可為例如淺溝槽隔離結構 (shallow trench is〇lation，STI)，其可包括例如氧化矽之材 質，以將其所包圍的主動區13電絕緣。主動區13可包括 一 P型摻雜井或N型摻雜井，於NM0S元件中，則為p型 . 摻雜井14，於pM〇S元件中，為N型摻雜井15。主動區 200807711 13内尚可包括源極/沒極區域％、27、或28、29，分別仅 於閘極結構兩侧的摻雜井14或15及磊晶層24中。於 兀件中，源極/汲極區域26及27為N型摻雜，於PM〇S 兀件中，源極/汲極區域28及29為P型摻雜。源極/汲極區 域亦可進一步包括一輕摻雜汲極(LDD)區域。磊晶層24係 位於主動區13之上方及閘極結構之下方，即，位於摻雜井 14與閘極結構之間，以及摻雜井15與閘極結構之間。應 注意的是，磊晶層24並不覆蓋整個隔離區16，而是經由 選擇性的形成於具有晶體結構的基底表面上，僅以周邊部 分24a延伸至隔離區16之一周邊部分之上方。 如此的結構，由第4圖可清楚看到，通道寬度w相較 於僅以主動區13為寬度的先前技術的通道寬度，是較為增 加的，使得Id值更增加，而達到增進元件效能之目的。於 PMOS元件中，磊晶層可包括Si、Sic、或此二者之混合物 等。於NMOS元件中，磊晶層可包括si、siGe、或此二者 之混合物等。亦可將磊晶層進一步予以輕摻雜。磊晶層的 厚度，並無嚴格的限制，可依需要而定，例如可在5〇A至 5〇〇A之間’蟲晶層越厚，其周邊部分延伸到隔離區的周邊 部分上方的寬度也會越寬，相對獲得的通道寬度會越寬。 但疋值％•注意的是’於-5¾離層上來自相鄰M〇s電晶體元 件的蠢晶層之周邊部分不能會合而彼此接觸到，或是相距 過近，以免影響二個腦電晶體元件之間的電絕緣需求。 200807711 閘極結構可包括— 20’閘極絕緣層可為例如錢化物等介 層可為例如多晶矽材料等導電材料。可 4一閘極電極層 介電材料，閘極電極 可進一步包括一間隙 一閘極絕緣層18及 ^ τρτ ^ 间障 土 22’間隙壁疋用來形成祕級極區域的輕摻雜延伸區 或之後可邊存於結構中，或是移除。閘極結構亦可進 一步包括一 L形襯墊層（liner)形成於間隙壁與閘極電極 層、半導體基底之間（未示出）。 依據本發明之MOS電晶體元件之結構，特徵在於閘極 結構與半導體基底之主動區之間具有一磊晶層，磊晶層的 周邊部分延伸至與主動區相鄰的隔離區周邊部分之上方， 111此能使通道寬度增加。 由於已知電晶體的汲極電流大小是依製程中所製得之 通道長度（L)和寬度（W)來計算的。當電晶體在飽和模 气下運作，》及極電流Id的大小在通道的長度和見度決定後 就保持固定，如下列公式所示：BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of fabricating the same, and an improvement method, and more particularly to a MOS transistor element, a method of fabricating the same, and a method of improving a gate current. [Prior Art] As the metal oxide semiconductor transistor (M〇SFET) progresses toward the miniaturized size, it enters the deep submicron era, for example, a purity of 65 nm or less, and the driving current for the MOS transistor element. The promotion of (drive current) has become increasingly important. It is known to use the concept of strained silicon to increase the mobility of holes or electrons to enhance the performance of the iridium semiconductor transistor components. For example, using the lattice constant of the tantalum layer to differ from tantalum causes the principle of structural strain when the tantalum epitaxial layer is on the tantalum layer, so that the relaxed germanium (si) germanium (Ge) layer grows in the insulating germanium (801). On the substrate or on the conventional tantalum substrate, the tantalum is grown on the relaxed tantalum layer to form strain enthalpy. Since the lattice constant of the 矽锗 layer is larger than that of 矽, this causes the band structure of 矽 to change, resulting in an increase in carrier mobility. In addition, a selective epitaxial growth method is also used to form the gate electrode. After the doping yttrium is embedded in the source 7 drain region, the electron mobility of the squeezed strain 矽 6 200807711 is formed. Or in the N-deletion process, the iron-transferable Μ / / / 录 11 domain towel, forming a technical extension, to increase the electron mobility. A top view of a plurality of conventionally known transistor elements is shown. CMOS __ shows a cross-sectional view along line ΑΑ' in Figure 1, which is illustrated by a 兀 structure. The CMOS semiconductor device includes one half of the conductor = which has a layer 12, and the base of the cast county includes an active region Η and a drain region 16 surrounding the active region 13 to electrically insulate the active region. The 1-pole structure is disposed on the active area 13. _ Structure package. H layer 18, a gate electrode layer 20, and a spacer 22. The active region can include a doping well 14 or 15. Therefore, the width of the channel is closed, and the width of the electrode layer overlaps with the active region, that is, the channel width of the conventional M〇s transistor element structure is limited to the width of the active region 13. It is known from the above that there are many ways to enhance the mobility of the carrier. For example, Figure 3 shows a schematic cross-sectional view of another conventional M〇s transistor element, which further has a self-aligned metal telluride layer 25 and a contact hole etch stop layer. (contact etch stop layer, CESL) 2!. By applying stress, the channel on the semiconductor substrate is strained by stretching or extrusion, and the mobility is improved. However, in the current technology for improving carrier mobility, the size of the channel is still accommodating and limited to the size of the components produced by the existing technical limits, such as lithography, engraving limits, and manufacturing shallow trenches. Slot isolation structure 7 200807711 The limit of filling trenches, etc. Accordingly, there is still a need for a MOS transistor component and method of fabricating the same that further enhances component performance over conventional techniques. SUMMARY OF THE INVENTION An object of the present invention is to provide a metal oxide semiconductor (MOS) transistor element, a method of fabricating a MOS transistor element, and a method of improving the gate current of a MOS transistor element. The MOS transistor of the present invention includes an epitaxial layer between the gate structure and the active region of the semiconductor substrate, and a peripheral portion of the epitaxial layer overlies a peripheral portion of the isolation region such that the channel width below the gate It can be wider than the original active area width, and therefore, the immersion current can be increased. The MOS transistor device according to the present invention comprises a semiconductor substrate, a gate structure, and a selective epitaxial layer. The semiconductor substrate includes an active region and an isolation region surrounding the active region to electrically insulate the active region. The gate structure is disposed on the active area. The epitaxial layer is between the active region and the gate structure, and a peripheral portion of the epitaxial layer overlies a peripheral portion of the isolation region. The method of manufacturing a MOS transistor element according to the present invention comprises the following steps. A semiconductor substrate is first provided. Secondly, in the semiconductor substrate, 200807711 is formed into an isolation region, and the isolation region defines an isolation region and an active region, wherein the active region is adjacent to the isolation region and electrically insulated via the isolation region. Next, a selective epitaxial process is performed to form an epitaxial layer on the surface of the active region while the epitaxial layer grows laterally to extend to the surface of the peripheral portion of the isolation region. A doped well is then formed in the semiconductor substrate of the active region. A gate structure is formed on the epitaxial layer. Finally, a source/drain region is formed in the doped well and the epitaxial layer on both sides of the gate structure. Further, a method of manufacturing a MOS transistor element according to the present invention includes the following steps. First, a semiconductor substrate is provided. Secondly, an isolation region and a doping well are formed in the semiconductor substrate, and the doping well is surrounded by the isolation region. Then, a selective epitaxial process is performed to form an epitaxial layer on the surface of the doped well while the epitaxial layer grows laterally and extends to the surface of the side portion of the isolation region. And then 'formed on the stupid layer - the pole structure. Finally, a source/drain region is formed in the doped well and the epitaxial layer on both sides of the gate structure. According to the present invention, a method for improving the drain current of a MOS transistor component includes a semiconductor substrate and a gate structure, wherein the semiconductor substrate includes a region and an active region, and the isolation region surrounds the active region to Electrical insulation. This method includes the following steps. First, after the isolation region is formed and before the gate structure is formed, a selective epitaxial layer is formed on the active region, and the epitaxial layer is laterally grown to extend to the surface of the peripheral portion of the isolation region 200807711, thereby increasing The channel width of the M0S transistor component. [Embodiment] A MOS transistor element according to the present invention may be an NMOS, a PMOS, or a CMOS. Fig. 4 is a top plan view showing a plurality of M〇s transistor elements in accordance with the present invention, and Fig. 5 is a cross-sectional view along line BB in Fig. 4, which is not intended to be illustrated by a CMOS device structure. The same elements or parts are still indicated by the same symbols. It should be noted that the drawings are for illustrative purposes only and are not plotted in the original size. The CM〇s transistor component includes a semiconductor substrate. The semiconductor substrate includes an active region 13 and an isolation region 16 surrounding the active region 13 to electrically insulate the active region 13. A gate structure, for example, including a gate insulating layer 18, a gate electrode layer 2A, and a spacer wall 22, is absent from the active region 13. A remote layer 24 is positioned between the active region 13 and the gate structure, and a peripheral portion 24a of the epitaxial layer 24 overlies a peripheral portion of the isolation region 16. In the CMOS transistor element 10, the semiconductor substrate may generally comprise a germanium layer 12' such as a stone base or a base of a stone insulating (10), which is not particularly limited. The isolation region 16 can be, for example, a shallow trench islation (STI), which can include a material such as hafnium oxide to electrically insulate the active region 13 it surrounds. The active region 13 may comprise a P-type doping well or an N-type doping well, and in the NMOS element, it is p-type. The doping well 14, in the pM〇S element, is an N-type doping well 15. The active region 200807711 13 may include source/drain regions %, 27, or 28, 29, respectively, in the doping wells 14 or 15 and the epitaxial layer 24 on either side of the gate structure. In the device, the source/drain regions 26 and 27 are N-type doped, and in the PM〇S device, the source/drain regions 28 and 29 are P-type doped. The source/drain regions may further include a lightly doped drain (LDD) region. The epitaxial layer 24 is located above the active region 13 and below the gate structure, i.e., between the doped well 14 and the gate structure, and between the doping well 15 and the gate structure. It should be noted that the epitaxial layer 24 does not cover the entire isolation region 16, but is selectively formed on the surface of the substrate having the crystal structure, extending only to the peripheral portion of one of the isolation regions 16 with the peripheral portion 24a. With such a structure, it can be clearly seen from FIG. 4 that the channel width w is increased compared to the prior art channel width which is only the width of the active region 13, so that the Id value is further increased to achieve improved component performance. purpose. In the PMOS device, the epitaxial layer may include Si, Sic, a mixture of the two, or the like. In the NMOS device, the epitaxial layer may include si, siGe, a mixture of the two, or the like. The epitaxial layer can also be further lightly doped. The thickness of the epitaxial layer is not critical, and may be determined as needed, for example, between 5 〇A and 5 〇〇A. The thicker the worm layer, the peripheral portion of which extends above the peripheral portion of the isolation region. The wider the width, the wider the width of the resulting channel. However, the value of 疋%• Note that the peripheral parts of the stray layer from the adjacent M〇s transistor elements on the -53⁄4 isolation layer cannot meet each other or are too close together to avoid affecting the two EEGs. Electrical insulation requirements between crystal components. 200807711 The gate structure may comprise - 20'. The gate insulating layer may be a conductive material such as a dielectric material such as a polysilicon material. 4 gate electrode layer dielectric material, the gate electrode may further comprise a gap-gate insulating layer 18 and a τρτ ^ barrier soil 22' gap wall 疋 used to form a light-doped extension region of the secret pole region Or you can save it in the structure or remove it later. The gate structure may further include an L-shaped liner formed between the spacer and the gate electrode layer and the semiconductor substrate (not shown). The structure of the MOS transistor device according to the present invention is characterized in that the gate structure has an epitaxial layer between the active region of the semiconductor substrate, and the peripheral portion of the epitaxial layer extends above the peripheral portion of the isolation region adjacent to the active region. , 111 This can increase the channel width. Since the size of the gate current of the transistor is known to be calculated according to the channel length (L) and width (W) obtained in the process. When the transistor is operating under saturated mode, the magnitude of the pole current Id remains fixed after the channel length and visibility are determined, as shown in the following equation:
(Vvt) w:通道寬度 l·通道長度 12 200807711 # :遷移率 Ca =電容值 v g:閘極電壓 vt:起始電壓 當通道寬度增加時 1讥id值增加 因此 ^ 如上述之 依據本發明之MOS電晶體元件之結構，特徵在於具有弯 性遙晶層的構造，使得通道寬度可較習知技術為寬大'(Vvt) w: channel width l·channel length 12 200807711 # : mobility Ca = capacitance value vg: gate voltage vt: starting voltage When the channel width increases, the value of 1 讥 id increases, so as described above according to the present invention The structure of the MOS transistor element is characterized by a structure having a curved crystal layer, so that the channel width can be made wider than conventional techniques'
Id值會較習知技術增加。而，於製造依據本發明之“ 曰曰體元件時，除了選擇性蠢晶層的形成之外，可利用 “ 的製程。選擇性遙晶層的形成不會對於原製程有不 有 響，卻能在基於原製程的效能基礎上，再 、衫 , 逆—步使Id值争 增加，而達到更加增進元件效能之目的。 、 再者，由於閘極絕緣層下方的通道上層3 層構成，因此，於製程中難免會擴散的摻雜:擴3磊 晶 的濃度較小，所以有利於％值的降低，如此， 值的提升 亦有利於 基於此種結構之MOS電晶體元件可適用於夕^ 之MOS電晶體元件，例如第6圖所示， 、夕種變化 J運一步包括— 對準金屬石夕化物層（salicide layer) 25，亦可進身 自 觸洞蝕刻停止層23。接觸洞蝕刻停止層23可為心丨匕括—接 均 13 200807711 勻沉積的氮化♦蓋層，其厚度較佳在3G至厕A之間。 下列請參’ 7至13圖’以進—步朗本發明之製造 MOS電晶體元件之方法。M〇s電晶體元件可為丽⑽、 PMOS、或C圓電晶體讀。第7至13圖顯示的是本發 明^製造CMOS電晶體元件之一具體實施例的方法的剖面 示意圖，其令相同的元件或部位仍沿用相同的符號來表 示。需注意的是圖式僅以說明為目的，並未依照原尺寸作圖。 請參閱第7圖，首先準備一半導體基底，其包含有石夕 層12於矽層12上形成隔離區16，隔離區可為例如淺溝 槽隔離結構，形成淺溝槽隔離結構的步驟可包括首先在石夕 層12上利用高溫氧化而於石夕層12纟面上生成一氧化物阻 障層’以保護主動區。接著’可經由化學氣相沉積形成一 石夕氮化物層於氧化阻障層上，然後進行一微影製程以形成 -光阻圖形於⑦氮化物層上’進行溝槽之細。於清洗及 乾知後，進行-低壓化學氣相沉積以將溝槽填滿氧化物， 然後’可進行化學機械研磨以將多餘的氧化物層移除，再 以例如熱磷酸將矽氮化物層去除，露出矽層12。如此，形 成隔離區16,隔離區16係圍繞主動區，以將主動區電絕緣^ 於本發明之方法中，磊晶層係在形成隔離區16且去除 矽氮化物層而露出石夕層12之後進行，而可在摻雜井形成之 14 200807711 前或之後進行。而較佳在露出矽層12之後，緊接著進行 以免矽層的晶體結構被破壞而影響磊晶品質。請參閱第8 圖，第8圖顯示在隔離區16形成之後，及形成摻雜井之前， 先形成蟲晶層24於砍層12上，此係藉由進行—選擇:全石 晶製程而達成。 在本發明之較佳實施例中，選擇性磊晶製程所使用之 氣體包含有例如二氣石夕曱烧(dichlorosilane，DCS)、氯化氣 (HC1)以及氫氣，而製程溫度係低於8〇(TC，以例如減壓化 學氣相沉積方法’進行砍蟲晶層的製造。在本發明之其它 實施例中，選擇性磊晶製程亦可利用例如矽甲烷(silane， SiHO與氯氣(CD作為製程氣體。亦可使用其他方法以形成 石夕蠢晶層，例如分子束磊晶法或超高真空化學氣相沉積 法。在本發明之其它實施例中，亦可形成矽與鍺之磊晶層， 可使用例如二氯矽烷(SiH2Cl2 ;簡稱DCS)及鍺烷(GeH4)， 以低壓化學氣相沉積(LPCVD)方法，在例如5〇0至800。(：：及 低壓下進行。或是形成矽與碳之磊晶，可使用SiH4及甲基 石夕曱烧(SiHsCH3)，以低壓化學氣相沉積(LPCVD)方法，在 例如500至8〇〇它及低壓下進行。可於磊晶製程時一併略 加低濃度的摻雜物以形成磊晶，或是磊晶成長後，再經由 離子佈植方式略加低濃度的摻雜，以調整MOS之起始電壤 (Vt)〇 200807711 由於磊晶層是以晶體構造層層往上長厚，所形成之結 晶晶格係與露出之半導體基底之晶體晶格相似，而淺溝槽 隔離結構是氧化物構造，為非晶形，因此，磊晶層並不會 在隔離區16之表面上成長。因此，使用本發明之方法，係 在半導體基底上全面性進行選擇性磊晶製程，且進行一次 即已足夠，不需分段進行，也不需圖形遮罩的辅助，即能 便利的在基底之所需位置上產生磊晶層。值得注意的是， 依據本發明之方法，磊晶層除了會在主動區之表面上向上 成長之外，亦會同時在具有厚度的磊晶層侧邊逐漸往側向 成長，而使得最後獲得的磊晶層之周邊部分係延伸而跨在 m離區16的周邊部分的表面上。如此，可增加電晶體閘極 通道的寬度，增進汲極電流量。 形成磊晶層後，可進一步進行一回火製程（anneal)，以 修设有缺陷的蠢晶晶格。 接著，進行摻雜井之製作，以獲得如第1〇圖所示之結 構。亦即可利用遮罩分別使用植入方法(implantati〇n)將所 而之P型摻雜物及N型摻雜物植入矽層12中，形成P型 換雜井14或N型摻雜井15。在磊晶層24已形成後進行摻 雜’並不會對磊晶層有不良影響。或是，進一步進行一回 火處理，以修復有缺陷的磊晶晶格。 16 200807711 此外，亦可以先形成摻雜井然後再形成蠢晶層。如第 9圖顯示，在形成隔離區16之後，先不形成蠢晶層，而於 隔離區16的半導體基底中先形成摻雜井14及15。然後， 請參閱第H)圖，於摻雜井14及15之表面上進行選擇性系 晶製程，以形成如上述之磊晶層24。 選擇性磊晶層形成後，可於磊晶層上製造所需之元 件，例如，閘極結構。請參閱第U圖，首先，於隔離區 16及磊晶層24上沉積一層氧化石夕層31等之介電層，及於 氧化矽層31上沉積一多晶矽層32等之導電層，然後利用 微影與蝕刻製程，形成閘極結構，其包括氧化矽層做為閘 極絕緣層18，及多晶矽層做為閘極電極層2〇。 閘極結構形成之後，可於間極結構兩侧之蟲晶層及推 雜井中形成源極/沒極區域。例如，進行輕汲極接雜(Ldd) 製程。請參閱第13圖，分別於閘極結構兩側之磊晶層24 及摻雜井14及15中形成淺接面源/汲極延伸17以及淺接 面源/汲極延伸19。隨後，在閘極電極層20及閘極絕緣層 18的侧壁上形成間隙壁22,間隙壁可為例如氮化矽或氧化 矽等材料所構成。而在形成間隙璧22之前可先形成一襯墊 層，襯墊層可為氧化矽所構成。 ， 在形成間隙壁22之後，邛進一步進行一離子佈植製 17 200807711 程，將N型摻質物種，例如砷、銻或磷等植入石夕層12中， 或將P型摻質物種，例如湖等植入秒層12中，藉此形成 NMOS元件的源/汲極區26、27，以及pm〇s元件的源/汲 極區28、29。在完成沒極源極的摻雜後，半導體基底通常 可以進行一回火(annealing)或活化(activation)摻質的熱製 程，此步驟亦為該行業者所熟知的，不再加以陳述。 可進一步於閘極電極層20、露出的源/汲極區26、27、 28、及29上形成一物質層’例如一金屬石夕化物層（metai silicidelayer)〕5。可利用自動對準金屬矽化物（selflaligned silicide，salicide)製程來形成金屬矽化物層；例如，在形成 源極/汲極區域之後，利用濺鍍或沈積方法，再形成一金屬 層覆蓋於源極/汲極區域與閘極結構上方，然後進行一快速 南/m製私(RTP)使金屬與閘極結構、源極/汲極區域中的砍 反應，形成金屬矽化物。RTP溫度可在700°C至1000。C 之間。 間隙壁22可留在結構中或是移除，移除後僅在閘極側 壁上留下約略呈L型的襯墊層。襯墊層不一定呈L型，亦 可以進行一較溫和的蝕刻製程，略微蝕刻襯墊層，以縮減 其厚度。在其它實施例中，襯墊層可被完全去除。 可進一步進行例如應變矽之製作或其他半導體製程技 18 200807711 術。例如，可於半導體基底上形成一接觸洞蝕刻停止層23， 例如一均勻沉積的氮化矽蓋層。使接觸洞蝕刻停止層23於 沈積時先設定沈積在一壓縮應力狀態（例如，一般在_0.1 Gpa至-3 Gpa之間，對於PMOS)或一拉伸應力狀態（例如， 一般在0·1 Gpa至3 Gpa之間，對於NMOS)，如此，使得 通道區域在通道方向具有對應之壓縮應變或拉伸應變，可 改善通道中載子之遷移率，以增進Id。接觸洞兹刻停止層 應力狀態可以利用熱處理、紫外線照射、電漿增益化學氣 相沉積法、或其他習知之方法進行。 第14圖顯示一如上述之依據本發明之製造m〇s電晶 體元件之方法之可行之流程圖之一例。簡言之，依據本發 明之方法，首先，於半導體基底上進行一步驟1〇1 ,以形 成隔離區；其次，可先進行步驟102以形成選擇性磊晶層， 再進行步驟103以形成摻雜井，或是先進行步驟112以形 成摻雜井，在進行步驟113以形成選擇性磊晶層；接著， 進行步驟104，以於磊晶層上形成閘極結構；最後，進行 步驟105，以於閘極結構兩侧的半導體基底及磊晶層中形 成源極/汲極區域。 依據本發明之另一具體實施例，使蠢晶層在形成摻雜 井之後形成，則隔離區與摻雜井的形成秩序並無限定，亦 可先進行步驟112以形成摻雜井，再進行步驟1〇1，以形 19 200807711 成隔離區，然後進行步驟113以形成選擇性磊晶層。 因此，值得注意的是，本發明之形成MOS電晶體元件 之方法，其中形成選擇性磊晶層之步驟必須在形成隔離區 之後以及形成閘極結構之前進行。 · 第15圖顯示一具體實施例中磊晶層完成後之穿透式 電子顯微照片，係依據本發明之製造MOS電晶體元件之方 法中於半導體基板上選擇性形成磊晶層之結果。此選擇性 磊晶成長係使用AMAT磊晶機台（美國應用材料公司製 造）’於15托耳之壓力下，以200 seem之二氯石夕烧 (dichlorosilane (DCS))、0.04 slm (標準升/分）之 HC1、及 30 slm之H2進行減壓化學氣相沉積(reduced pressure chemical vapor deposition)。形成的磊晶層厚度T為約70nm，磊晶 層的周邊部分延伸至與主動區相鄰的淺溝槽隔離結構(STI) 之周邊之上方而覆蓋它，約140nm的延伸距離。 上述具體實施例只是可行方式的其中一例，可有許多 變化，例如，可使用分子束磊晶法或超高真空化學氣相沉 積法取代減壓化學氣相沉積、或是使用SiH4取代二氯矽烷。 使用如上述具體實施例所製得之具有選擇性磊晶層及 隔離區之晶圓編號24，製造高壓P型金氧半導體電晶體 20 200807711 (HVTPMOS)及HVTNMOS，與習知技術之由不具有選擇 性磊晶層之晶圓編號12製得之HVTPMOS與HVTNMOS 分別比較之，二者具有相同之通道長度，但晶圓編號24製 得之電晶體元件具有較寬的通道寬度。在相同的通道長度 下(Ldrawn)，如第16圖所示，晶圓編號24製得之HVT PMOS電晶體元件，於施加IV的電壓下，具有較晶圓編號 12製得之HVT PMOS為高的電流(Ion)，在Ldrawn為〇·〇7 時，增加約28%，在Ldrawn為0.12時，增加約21%。如 第17圖所示，晶圓編號24製得之HVTNMOS電晶體元 件，於施加IV的電壓下，具有分別較晶圓編號12製得之 HVT NMOS為高的電流(lon)，在Ldrawn為0.07時，增加 約9.6%，在Ldrawn為〇·12時，增加約16%。 第18圖顯示晶圓編號24製得之HTVNMOS電晶體元 件與晶圓編號12製得之HVT NMOS於各種通道長度下元 件的閉電流(IQff)對開電流(Ιοη)作圖，獲得泛曲線(universal curve)。可看出在相同i〇ff值下，依據本發明之方法製得之 電晶體元件具有較高的1〇11值。 第19圖顯示晶圓編號24製得之HTVPMOS電晶體元 件與晶圓編號12製得之HVTPMOS於各種通道長度下];〇ff 對I〇n作圖’獲得泛曲線(universal curve)。顯示在相同i〇ff • 值下，依據本發明之方法製得之電晶體元件具有較高的I(m值。 21 200807711 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖顯示一習知之MOS電晶體元件之頂視示意圖。 第2圖顯示第1圖中沿著AA’線段的剖面示意圖。 第3圖顯示另一習知之MOS電晶體元件之剖面示意圖。 第4圖顯示一依據本發明之MOS電晶體元件之具體實 施例之頂視示意圖。 第5圖顯示第4圖中沿著BB’線段的剖面示意圖。 第6圖顯示一依據本發明之MOS電晶體元件之另一具 體實施例之剖面示意圖。 第7至13圖說明依據本發明之製造MOS電晶體元件 之方法之具體實施例。 第14圖顯示一依據本發明之製造MOS電晶體元件之 方法之流程圖。 第15圖顯示一依據本發明之製造MOS電晶體元件之 方法之具體實施例中磊晶層完成後之穿透式電子顯微照片。 第16圖顯示依據本發明之方法製得之HVT PMOS電 晶體元件與習知之HVT PMOS電晶體元件之電流(Ion) 對Ldrawn作圖。 . 第17圖顯示依據本發明之方法製得之HVT NMOS電 晶體元件與習知之HVTNMOS電晶體元件之電流(Ion) 22 200807711 對Ldrawn作圖。 第18圖顯示依據本發明之方法製得之HVT NMOS電 晶體元件與習知之HVT NMOS電晶體元件之Ioff對Ion 作圖所獲得之泛曲線。 第19圖顯示依據本發明之方法製得之HVT PMOS電 晶體元件與習知之HVT PMOS電晶體元件之Ioff對Ion 作圖所獲得之泛曲線。 【主要元件符號說明】 1 習知之CMOS半導體元件 10 本發明之CMOS半導體元件 12 矽層 13 主動區 14 摻雜井 15 摻雜井 16 隔離區 17 淺接面源/汲極延伸 18 閘極絕緣層 19 淺接面源/汲極延伸 20 閘極電極層 21 接觸洞银刻停止層 22 間隙壁 23 接觸洞姓刻停止層 24 遙晶層 24a磊晶層之周邊部分 25 自對準金屬矽化物層 26、 27、28、29 源極/汲極區域 31 氧化矽層 32 多晶矽層 101 、102 、 103 、 104 、 105 、112 、113 步驟 23The Id value will increase compared to the prior art. However, in the manufacture of the "corporate element" according to the present invention, in addition to the formation of the selective stupid layer, the "process" can be utilized. The formation of the selective telecrystal layer will not be unremarkable for the original process, but on the basis of the efficiency of the original process, the I, the value of the I, will increase the Id value, and achieve the purpose of further improving the performance of the component. Furthermore, since the upper layer of the channel under the gate insulating layer is composed of three layers, the doping which is inevitably diffused during the process: the concentration of the epitaxial 3 is small, so that the value of the value is lowered, so that the value The improvement is also advantageous for the MOS transistor component based on such a structure that can be applied to the MOS transistor component of the MOS, for example, as shown in FIG. 6, the eve of the change J includes: aligning the salicide layer 25, can also enter the self-touch hole etching stop layer 23. The contact hole etch stop layer 23 may be a nitriding ♦ cap layer uniformly deposited on the core 13 200807711, preferably having a thickness between 3G and the toilet A. For the following, please refer to the method of manufacturing the MOS transistor component by the invention. The M〇s transistor component can be read by a MN (10), PMOS, or C circular transistor. Figures 7 through 13 are schematic cross-sectional views showing a method of fabricating a CMOS transistor component of the present invention, wherein the same elements or portions are denoted by the same reference numerals. It should be noted that the drawings are for illustrative purposes only and are not drawn to the original dimensions. Referring to FIG. 7, first, a semiconductor substrate is prepared, which includes a layer 12 on which an isolation region 16 is formed. The isolation region may be, for example, a shallow trench isolation structure. The step of forming a shallow trench isolation structure may include First, an oxide barrier layer is formed on the diatom layer 12 by high temperature oxidation to form an oxide barrier layer on the 12-side surface of the diatom layer to protect the active region. Then, a thin layer of nitride can be formed on the oxidation barrier layer by chemical vapor deposition, and then a lithography process is performed to form a photoresist pattern on the 7 nitride layer to perform fineness of the trench. After cleaning and drying, a low pressure chemical vapor deposition is performed to fill the trench with oxide, and then 'chemical mechanical polishing can be performed to remove the excess oxide layer, and then the tantalum nitride layer is, for example, hot phosphoric acid. Removed to expose the enamel layer 12. Thus, an isolation region 16 is formed, the isolation region 16 surrounding the active region to electrically insulate the active region in the method of the present invention, the epitaxial layer is formed in the isolation region 16 and the germanium nitride layer is removed to expose the layer This can be done later, before or after the formation of the doped well 14 200807711. Preferably, after the ruthenium layer 12 is exposed, the crystal structure of the ruthenium layer is destroyed to affect the epitaxial quality. Referring to FIG. 8, FIG. 8 shows that after the isolation region 16 is formed and before the doping well is formed, the worm layer 24 is formed on the chopping layer 12, which is achieved by performing a selection: a full stone process. . In a preferred embodiment of the present invention, the gas used in the selective epitaxial process comprises, for example, dichlorosilane (DCS), chlorinated gas (HC1), and hydrogen, and the process temperature is less than 8 TC (TC, for example, decompression chemical vapor deposition method) for the manufacture of a chopped smear layer. In other embodiments of the invention, the selective epitaxial process may also utilize, for example, silane (Si, SiO, and chlorine). As a process gas, other methods may be used to form a stony layer, such as molecular beam epitaxy or ultra-high vacuum chemical vapor deposition. In other embodiments of the invention, 矽 and 锗 磊The crystal layer may be, for example, dichloromethane (SiH2Cl2; DCS for short) and decane (GeH4), in a low pressure chemical vapor deposition (LPCVD) method, for example, at a temperature of 5 〇 0 to 800 (:: and at a low pressure). It is an epitaxial crystal formed by bismuth and carbon, which can be carried out by low pressure chemical vapor deposition (LPCVD) method using, for example, 500 to 8 Torr and low pressure using SiH4 and methyl zephyr (SiHsCH3). Add a low concentration of dopants to form epitaxial grains during the crystal process, or After the epitaxial growth, the doping is slightly added by ion implantation to adjust the initial electrode of the MOS (Vt) 〇200807711. Since the epitaxial layer is thickened by the crystal structure layer, it is formed. The crystal lattice is similar to the crystal lattice of the exposed semiconductor substrate, and the shallow trench isolation structure is an oxide structure which is amorphous, so that the epitaxial layer does not grow on the surface of the isolation region 16. Therefore, By using the method of the invention, the selective epitaxial process is comprehensively performed on the semiconductor substrate, and once it is sufficient, no segmentation is required, and no auxiliary of the pattern mask is needed, that is, it can be conveniently located on the substrate. It is necessary to produce an epitaxial layer at the position. It is worth noting that, according to the method of the present invention, in addition to the upward growth of the epitaxial layer on the surface of the active region, the epitaxial layer is gradually flanked at the side of the epitaxial layer having a thickness. The growth is made such that the peripheral portion of the finally obtained epitaxial layer extends over the surface of the peripheral portion of the m-off region 16. Thus, the width of the transistor gate channel can be increased to increase the amount of drain current. After the crystal layer, an anneal process can be further performed to repair the defective crystal lattice. Then, the doping well is fabricated to obtain the structure as shown in Fig. 1. The P-type dopant and the N-type dopant are implanted into the ruthenium layer 12 by using an implant method using an implant method to form a P-type well 14 or an N-type well 15. Doping 'after the epitaxial layer 24 has been formed does not adversely affect the epitaxial layer. Alternatively, a tempering treatment is performed to repair the defective epitaxial lattice. 16 200807711 In addition, it is also possible A doped well is formed and then a doped layer is formed. As shown in FIG. 9, after the isolation region 16 is formed, the doped layer is not formed, and the doping wells 14 and 15 are first formed in the semiconductor substrate of the isolation region 16. Then, referring to Figure H), a selective crystallization process is performed on the surfaces of the doping wells 14 and 15 to form an epitaxial layer 24 as described above. After the selective epitaxial layer is formed, the desired components, such as the gate structure, can be fabricated on the epitaxial layer. Referring to FIG. U, first, a dielectric layer such as a oxidized layer 31 is deposited on the isolation region 16 and the epitaxial layer 24, and a conductive layer such as a polysilicon layer 32 is deposited on the yttrium oxide layer 31, and then utilized. The lithography and etching process forms a gate structure including a ruthenium oxide layer as the gate insulating layer 18 and a polysilicon layer as the gate electrode layer 2 〇. After the gate structure is formed, the source/drain regions can be formed in the wormhole layer and the push well on both sides of the interpole structure. For example, perform a light-drain (Ldd) process. Referring to Fig. 13, a shallow junction source/drain extension 17 and a shallow junction source/drain extension 19 are formed in the epitaxial layer 24 and the doping wells 14 and 15 on both sides of the gate structure, respectively. Subsequently, a spacer 22 is formed on the sidewalls of the gate electrode layer 20 and the gate insulating layer 18, and the spacer may be formed of a material such as tantalum nitride or hafnium oxide. A pad layer may be formed before the gap 璧 22 is formed, and the pad layer may be made of yttrium oxide. After forming the spacers 22, further performing an ion implantation process, and implanting an N-type dopant species, such as arsenic, antimony or phosphorus, into the diatom layer 12, or a P-type dopant species, For example, a lake or the like is implanted in the second layer 12, thereby forming source/drain regions 26, 27 of the NMOS device, and source/drain regions 28, 29 of the pm?s device. After completion of the doping of the immersed source, the semiconductor substrate can typically be subjected to an annealing or activation of the thermal process, which is also well known to those skilled in the art and will not be described. Further, a material layer 'e.g., a metal stellite layer 5' may be formed on the gate electrode layer 20 and the exposed source/drain regions 26, 27, 28, and 29. A metallization layer can be formed by a self-aligned silicide (salicide) process; for example, after forming a source/drain region, a metal layer is formed over the source by sputtering or deposition. Above the gate region and the gate structure, a rapid south/m private (RTP) is applied to cause metal chelating reactions in the gate structure and source/drain regions to form metal halides. The RTP temperature can range from 700 °C to 1000. Between C. The spacers 22 may remain in the structure or be removed, leaving only a substantially L-shaped liner layer on the gate side walls. The liner layer is not necessarily L-shaped, and a gentler etching process can be performed to slightly etch the liner layer to reduce its thickness. In other embodiments, the liner layer can be completely removed. Further, for example, the production of strain enthalpy or other semiconductor process technology 18 200807711 can be performed. For example, a contact etch stop layer 23 can be formed over the semiconductor substrate, such as a uniformly deposited tantalum nitride cap layer. The contact hole etch stop layer 23 is first deposited during deposition in a compressive stress state (eg, typically between _0.1 Gpa and -3 Gpa for PMOS) or a tensile stress state (eg, typically at 0.11). Between Gpa and 3 Gpa, for NMOS), the channel region has a corresponding compressive strain or tensile strain in the channel direction, which improves the mobility of the carriers in the channel to improve Id. Contact hole stop layer The stress state can be performed by heat treatment, ultraviolet irradiation, plasma gain chemical vapor deposition, or other conventional methods. Fig. 14 shows an example of a possible flow chart of the method of manufacturing an m〇s electromorphic element according to the present invention as described above. Briefly, in accordance with the method of the present invention, first, a step 1 〇 1 is performed on a semiconductor substrate to form an isolation region; secondly, step 102 may be performed first to form a selective epitaxial layer, and then step 103 is performed to form a doping layer. a well, or step 112 is first performed to form a doping well, and step 113 is performed to form a selective epitaxial layer; then, step 104 is performed to form a gate structure on the epitaxial layer; finally, step 105 is performed. A source/drain region is formed in the semiconductor substrate and the epitaxial layer on both sides of the gate structure. According to another embodiment of the present invention, after the doped layer is formed after the doping well is formed, the order of formation of the isolation region and the doping well is not limited, and step 112 may be performed first to form a doping well. Step 1〇1, forming an isolation region in the shape of 19200807711, and then performing step 113 to form a selective epitaxial layer. Therefore, it is worth noting that the method of forming a MOS transistor element of the present invention in which the step of forming a selective epitaxial layer must be performed after forming the isolation region and before forming the gate structure. Fig. 15 is a view showing a transmission electron micrograph after the completion of the epitaxial layer in a specific embodiment, which is a result of selectively forming an epitaxial layer on a semiconductor substrate in the method of fabricating a MOS transistor element according to the present invention. This selective epitaxial growth was carried out using an AMAT epitaxial machine (manufactured by Applied Materials, Inc.) under a pressure of 15 Torr, 200 seeming dichlorosilane (DCS), 0.04 slm (standard liter /H) and H2 of 30 slm are subjected to reduced pressure chemical vapor deposition. The thickness of the epitaxial layer formed is about 70 nm, and the peripheral portion of the epitaxial layer extends over the periphery of the shallow trench isolation structure (STI) adjacent to the active region to cover it, an extension distance of about 140 nm. The above specific embodiment is only one example of a feasible manner, and there may be many variations, for example, molecular beam epitaxy or ultra-high vacuum chemical vapor deposition may be used instead of decompression chemical vapor deposition, or SiH4 may be used instead of dichlorodecane. . The high-voltage P-type MOS transistor 20 200807711 (HVTPMOS) and HVTNMOS are fabricated using the wafer number 24 having the selective epitaxial layer and the isolation region prepared as described in the above embodiments, and the conventional technology does not have The HVTPMOS and HVTNMOS prepared by wafer number 12 of the selective epitaxial layer are respectively compared to have the same channel length, but the transistor element fabricated by wafer number 24 has a wider channel width. At the same channel length (Ldrawn), as shown in Fig. 16, the HVT PMOS transistor component fabricated by wafer number 24 has a higher HVT PMOS than wafer number 12 at the voltage applied to IV. The current (Ion) increases by about 28% when Ldrawn is 〇·〇7 and about 21% when Ldrawn is 0.12. As shown in Fig. 17, the HVTNMOS transistor device fabricated by wafer number 24 has a higher current (lon) than the HVT NMOS obtained by wafer number 12 at a voltage of IV applied, and is 0.07 at Ldrawn. At the time, it increased by about 9.6%, and when Ldrawn was 〇·12, it increased by about 16%. Figure 18 shows the closed current (IQff) off current (Ιοη) of the HTV NMOS transistor fabricated in wafer number 24 and the HVT NMOS fabricated in wafer number 12 at various channel lengths to obtain a universal curve (universal). Curve). It can be seen that the transistor elements made in accordance with the method of the present invention have a higher value of 1 〇 11 at the same i 〇 ff value. Figure 19 shows the HTVPMOS transistor fabricated in wafer number 24 and the HVTPMOS fabricated in wafer number 12 at various channel lengths; 〇ff plots I〇n to obtain a universal curve. Shown at the same i 〇 ff • value, the transistor element produced according to the method of the present invention has a higher I (m value). 21 200807711 The above description is only a preferred embodiment of the present invention, and is applied according to the present invention. Equivalent changes and modifications made in the patent range are within the scope of the present invention. [Simplified Schematic] Figure 1 shows a top view of a conventional MOS transistor component. Figure 2 shows the edge in Figure 1. A schematic cross-sectional view of a line of AA'. Fig. 3 is a schematic cross-sectional view showing another conventional MOS transistor element. Fig. 4 is a top plan view showing a specific embodiment of a MOS transistor element according to the present invention. 4 is a schematic cross-sectional view along line BB'. Fig. 6 is a cross-sectional view showing another embodiment of a MOS transistor device according to the present invention. Figs. 7 to 13 illustrate a fabrication of a MOS transistor in accordance with the present invention. DETAILED DESCRIPTION OF THE INVENTION A method of fabricating a MOS transistor component in accordance with the present invention is shown in Figure 14. Figure 15 shows a method of fabricating a MOS transistor component in accordance with the present invention. A transmission electron micrograph of the finished epitaxial layer in the embodiment. Figure 16 shows the current (Ion) of the HVT PMOS transistor component and the conventional HVT PMOS transistor component produced by the method of the present invention. Figure 17 shows the current (Ion) of a HVT NMOS transistor element fabricated in accordance with the method of the present invention and a conventional HVT NMOS transistor element. 2207707711 for Ldrawn. Figure 18 shows a method according to the present invention. A general curve obtained by plotting Ioff versus Ion of a conventional HVT NMOS transistor component. Figure 19 shows a HVT PMOS transistor component fabricated in accordance with the method of the present invention and a conventional HVT PMOS transistor. Ioff of component Ioff vs. Ion. [Main component symbol description] 1 Conventional CMOS semiconductor component 10 CMOS semiconductor component 12 of the invention 矽 layer 13 active region 14 doping well 15 doping well 16 isolation region 17 Shallow junction source/drain extension 18 gate insulation layer 19 shallow junction source/drain extension 20 gate electrode layer 21 contact hole silver engraving stop layer 22 spacer 23 contact hole surviving stop layer 24 The peripheral portion 25 of the epitaxial layer of the seed layer 24a is self-aligned with the metallization layer 26, 27, 28, 29 source/drain region 31, the hafnium layer 32, the polysilicon layer 101, 102, 103, 104, 105, 112, 113 Step 23