TW200803643A - Printed multilayer solenoid delay line - Google Patents

Abstract

A printed solenoid inductor delay line system comprises discrete delay sections, where the inductor is implemented in the form of a printed, spiraling solenoid, with the solenoid axis in the plane of the multi-layer printed circuit board (PCB).

Description

200803643 IX. INSTRUCTIONS: L·J^ff Λ ^ Field of the Invention The present invention relates to a solenoid delay line. More specifically, there is a printed multilayer solenoid delay line system. c prior art 3 invention background

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Signal skew is a well-known feature in high-speed communication and video signal transmission. Signal skew also occurs on the multi-stranded pair cable that is now visible on the computer network: ring::: human. In general, skew is generally expected to be sent at the same time but the arrival of data on different signal lines is “two == phenomenon. The skew is due to different transmission rates through different pairs of electricity companies. In the case of twisted pair cables, It is usually caused by the different twist ratios used for this pair of wires. The line with a tighter twist rate causes the signal to propagate a motion Μ ^ X . The pair of electricity is often deliberately designed to have different decimations between the pair (4) lines. Crosstalk between the pair is observed. A detailed description of the specified delay line was published by Allen Aerospace's Lester Jacquesson. The "Designated Delay Line" of the Electronic Products Magazine, described in the text 20, is incorporated herein by reference. 2, 2, 8 and 2 years, on April 23, issued to Shi Duhua and others, entitled "Twisted Pairs of the Line, First and for All, and for the purpose of this article, US Patent No. 6 '377 '629' A delay line formed by the zigzag row J formed on both sides of the block printed circuit board, for example, in the third and the ninth sheds of the case 5, 200803643, line 24 to column 10, line 50. I: SUMMARY OF THE INVENTION SUMMARY OF THE INVENTION In accordance with a particular embodiment of the present invention, a spiral 5 tube delay line is specifically formed which is formed on at least two layers of a multilayer printed circuit board, the delay line comprising: one on the PCB board Forming a first plurality of discrete delay elements on the first layer; and forming a second plurality of discrete delay elements on a second layer of the PCB, the second layer being distinct from the first layer Wherein the first component vertical delay elements are each electrically connected to at least one of the second component vertical delay elements 10. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 (a) shows an embodiment in accordance with the present invention Print a solenoid in one of a delay line. Brother 1 (b) 2, 7, and 8(a)-8(c) show an alternative specific embodiment of the present invention. [Embodiment 3 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1(a) shows a multi-layer printing A solenoid delay inductor 1〇〇 formed on two layers of a circuit board (PCB) 1〇2. The solenoid delay inductor 20 1〇0 is included in the first layer of the PCB 102 a plurality of top portions 104 1-4, 104-2, . . . , 104-4 (collectively referred to as top portions 1 〇 4) formed on a portion, and portions of the PCB 1 〇 2 different layers 110 a plurality of bottom portions 106_1, 106-2 ..... 106_4 (collectively referred to as bottom portions 1〇6) formed on the portion. In the case of a two-layer PCB, the different layer 110 will be for this pcB 1〇2 Bottom 6 200803643 layers. These top portions are connected via electrical connection vias 112-1, 112-2 (collectively referred to as vias 112) formed in this PCB 102. Thus, as shown in Figure 1, the top The portion 104-1 is electrically connected to the bottom portion 5 106 via the through hole nw. In this manner, the top and bottom portions are electrically connected thereto to form a solenoid delay body, which is completed by the electrical connections. screw Tube windings. For each top portion, the length lt and width Wt of each top portion 1〇4 may be substantially the same or may be different. Similarly for 10, for each bottom portion, The length lb and the width wb of each of the bottom portions 1〇6 may be substantially the same or may be different. Each of the top portions 1〇4-j is formed with each of the bottom portions 106-j to which it is connected An angle can be the same (or substantially the same) for each top and its corresponding bottom portion, or it can be different. 15 The top and bottom portions of these connections form a delay solenoid with the solenoid axis on the plane of the PCB. Each top portion or component forms a portion of a delay line, each bottom portion or component being the same. In the example shown, there are four top portions and four bottom portions; those skilled in the art will directly understand that the number and size of such portions are determined by the amount of delay required in the 20 lines: . Further, in the example shown, only two layers are shown; however, those skilled in the art will appreciate that more than two layers can be used, and are also considered in this case. The schema is not completely proportional and the angle between the corresponding components may be adjusted to reduce the space requirements of the drawing. In addition to this, it will be appreciated by those skilled in the art that the solenoids according to embodiments of the present invention are not symmetrical. ^° The page portion (top element) 104_j does not need to be the same size as the other top elements, and similarly, all the bottom portions (bottom element) 106_k do not need this. 5 帛 1 (b) shows an alternative way of forming the lower portions 1 〇 4 · χ, 104-y such that the top portion 102 p does not have to be angled. Capacitors (1), ι6, as shown in Fig. 2, may be disposed below the solenoid 1〇〇 to match the capacitance of some other components of the circuit (e.g., a switch not shown). A specific embodiment of the present invention can use a printed capacitor 4 having a ground plane of one turn by completely omitting the capacitance crying by the inherent capacitance of each switching element. In a preferred embodiment, a substantial margin width is maintained to reduce wear and tear. However, this limits the number of saka and the amount of inductance. It is also possible to adopt other types of sub-inductor segmentation structures instead of the long-turn coupling solenoid design as shown in the above figures, such as the non-coupling or anti-coupling shown in Figures 3 and 4, respectively. Connected to the design. In the embodiment of the invention shown in Figure 3, the solenoid delay circuit includes three sections labeled SI, S2, and S3. Some embodiments of the present invention may also use a more dispersed capacitance by utilizing at least one layer of an inductor that is closely spaced from a ground plane button. Fig. 5 is a top plan view of a solenoid delay body 15A according to an embodiment of the present invention, with the inductor 122 on the inner layer and the bottom ground plane uniformly aligned. - The through holes of the column connect the top to the bottom ground plane. In order to reduce any possible circulating current, a cutting portion can be inserted to cover the inductor 8 200803643. Figure 6 depicts another layout of a solenoid retarder in accordance with an embodiment of the present invention. As shown in the figure, a solenoid delay body 16 has a star shape (the line portion is on the first layer of the PCB and the dotted portion is on the second layer 5). The π-piece on the first layer is connected to the corresponding element on the second layer via an electrical via (indicated by a circle). The configuration shown in Figure 6 allows a delay line segment to be composed of 18 〇. That is, the delay body segments can be connected to other solenoid delay segments at locations 162 and 164. For certain embodiments of the present invention, at least a delay of 32 nanoseconds (four) of 10 is required to complete - an E number. The radial or star-shaped embodiment of Figure 6 can be used with several E-segments of 30 degree angle to form a smooth resistance. Although this design may occupy a significant portion of the pCB end region as compared to the implementation of other forms of physical delays or circuitry in the end regions of the PCB, this design is still a safe way to avoid unwanted interference. This end space 15 contains five E, but those skilled in the art will appreciate that fewer or more zones can be used. Figure 7 shows an alternative configuration designed to complete one (10) segment, using one configuration of two solenoids 17, 172, 172 which are plunged and located at the center The central connection grounding fins 174 are connected. 20 & The opportunity to reduce the magnetic field interference at the end of the solenoid keeps the section directly above the central connection grounding slab 174 free of other circuitry. In order to reduce the light-weight cooperation across the segments, the main separation between the columns can be increased. In order to have a lower capacitance, the two inner segments can be staggered. In order to reduce the chance of a possible coupling with the magnetic field of the solenoid, an empty area should be left at each end of the 9 200803643 without components or cross-cuts; the dimensions implemented in the preferred embodiment are 200 mils at one end. Deep, and the other end is 1 mil deep, each empty area has a width of about 100 mils. In a preferred embodiment of the invention, the pitch between each K should be 4 mils and the spacing between the left and right segments of the coil 5 should be 65 mils. In some preferred embodiments, the wider coil turns have a width of 270 mils and the shorter turns have a width of 230 mils. A detailed description of the specific manufacturing methods and materials used in the construction of the present invention is further provided below. In some embodiments of the invention, the pcB structure has a hard core center of 59 mils and is laid on both sides with one ounce of copper. Thus, the central portion of the board can be constructed of a typical glass epoxy tree (such as FR4) of approximately 56 mils. The board has 7 mils of 7628 film and 1/2 ounces of copper on each side, which can be optionally plated to 丨 ounces. In some cases, if a larger capacity is required, a 4.5 mil 2116 gel 15 piece can be used. However, the total plate thickness is approximately 75 mils. This spiral structure has a plated through hole diameter of 15 mils. In addition, the winding is equal to about 4 nautical miles. This is done by a 31 mil outer layer, which is then separated by a 9 mil annular ring and 9 mils between the shims. More progressively, the inner layer will be 35 mils with a 1 mil ferrule ring spacer spacing. Alternatively, for each slap that is staggered on a 40 mil 袼 grid, the pitch will be 56.6 mils. Therefore there will be 25.6 mils between the shims on the top layer, allowing for a 9 mil extended or filled area of copper and 8 ft. For a grounded capacitor, a 13 mil can be used. The tooth-passing structure and the space of 6 mils. 10 200803643 Each device is wound on the inner layer of the solenoid to form a screw mil = part. In addition, each of the solenoids is used. For the two rooms (which are slightly reduced due to the angle of each ancestor, this solenoid has a side with a straight line of the slabs more = shims) and allows a good top layer on the staggered side to be connected by any error. The average value of the opening hole is the nominal amount • *25° mil. Therefore, the solenoid cross-sectional area is • square = (0.356IW). Therefore, the resulting inductance value is:

10 L = 4·46 x N2 / (0.4 X N + 0.6) nH where '疋租数. Therefore, for longer solenoids, the inductance value is β 1111 靡, while the shorter solenoid has an inductance value of 1 〇. Therefore, in one embodiment in which the end inductance is added to the solenoid for impedance matching, an inductance value of 10 nH/匝 should be used. The details of the capacitance, impedance and delay amount of the embodiment are as follows. ❿ «The capacitor's dielectric 7628 film uses a 4.7 dielectric constant • (Er). The value of the capacitance of the 3 mil-wide section extending on the inner layer to the layer on the ground plane can be defined as WpF/in. Thus, using the previously described solenoid geometry, there is a top 20 layer spacing of 8 mils between the pads and the ground plane, thus resulting in an effective capacitor length of 0.0430 inches per turn. Therefore, the capacitance value is approximately 3.2 pF/匝. For a long solenoid, the impedance is calculated to be 59 Ω (ohms), while the short solenoid is 56 Ω. The time delay for the above values is 0188 ns/匝. For a shorter solenoid, it is 0.179 ns/匝, which is approximately twice as long as the delay of the same length stripline 11 200803643. In addition, the delay rate along the length of this solenoid is 4·7 ns/in, and in the case of a short solenoid, it is 4·5 ns/in. In addition, the individual half-turn delays are short enough to support high-bandwidth signals. Further, in this embodiment, the solenoid "line width" should be 5 〇 · 325 inches · ·). Therefore, the delay density is 14.4 ns/in2. In addition, the DC resistance is mainly generated by 30 mils of copper. This 3 mil of copper is equal to one ounce of copper 'and causes the entire solenoid to produce approximately 17 πιΩ An, which is associated with 8·8 ηιΩ/匝 and 46.8 πιΩ/ns. This DC resistance reduces the signal strength, so image color may be affected. The gasket has a major copper path width of 10 20 mils. The width of the coil is 1 〇 6 mils between the center points, and there is sufficient space for the inner and outer two-way holes of the "near" coil side. In order to obtain an appropriate amount of inductance, the coil length is variable, however in some cases a square coil is also preferred. To avoid a short circuit, ground vias should not be used anywhere in the solenoid area. Those skilled in the art will appreciate that the number of turns and the length of the component will depend on the amount of delay required. It is preferred to set 2 turns (with signal entry and exit points) that are not covered by an external ground plane. These 用于 can be used to match 20 when an unloaded inductor is expected. Application Range The solenoid delay line according to an embodiment of the present invention can be applied in a large number of applications. However, they are particularly useful in keyboard, video, and mouse (KVM) applications where video data is transmitted over twisted pairs. The present invention is also incorporated in U.S. Patent Application Serial No. 10/366,695, the entire disclosure of which is incorporated herein by reference. The system described in the "Twisted Pair Communication Line System" of U.S. Patent No. 6,377,629, the entire disclosure of which is incorporated herein by reference in its entirety in its entirety herein in It is understood that the invention is not intended to be used in the disclosed embodiments.

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The following is a description of the various modifications and equivalent arrangements included in the spirit and scope of the application for the application of the scope of application. Figure 1(a) shows the embodiment of the invention according to the present invention used in a delay line. One of the printing solenoids - The first (8), 2 to 7, and 8 (8) - 8 (4) diagrams show alternative embodiments of the present invention. [Main component symbol description] α, %··· Angles 1〇2, ρ·. ·Top part 1〇4, χ, i〇4—y···lower part S1~S6···part U4,116···capacitor 122···inductor 150,160···Solenoid retarder 162, 164···Position 170, 172···Solenoid 174···Grounding pad 100···Solenoid delay inductor 102···Multilayer printed circuit board (PCB) 104, 104-1 ~ 1〇41-4, 104-j·.·top part 106,106-;[~1〇β—4, 1〇6-j··· bottom part 108···first layer 110···different layers H2, 112-1~112—2···through hole Wb, Wt...width lb, lt···length 13

Claims (1)

200803643 X. Patent application scope: 1. A solenoid delay line formed on at least two layers of a multilayer printed circuit board (PCB), the delay line including a first layer on the PCB Forming a first plurality of discrete 5 delay elements thereon; and forming a second plurality of discrete delay elements on a second layer of the 戎PCB, the second layer being distinct from the first layer, § Wherein the first component vertical delay elements are each electrically connected to at least one of the second component vertical delay elements. The solenoid delay line of claim 1, wherein the first plurality of delay elements are disposed at an angle with respect to the corresponding second plurality of delay elements. 3. The solenoid delay line of claim 3, wherein the first plurality of delay pieces are formed on a top portion of the PCB. 4. The solenoid delay line of claim 2, wherein the second _ delay element is formed on a bottom portion of the PCB. • A spiral, conduit delay line as described in the scope of the patent application, wherein the corresponding ones of the first set of delay elements are interconnected via vias formed in the PCB. The solenoid delay line of claim 7, wherein the seventh and second plurality of delay elements are printed on the PCB. The solenoid delay line of claim 6, wherein the axis of the solenoid is formed in a plane of the PCB. 8. A solenoid shut-off line formed on at least two layers of a multi-layer (four) circuit board (pcB) 200803643, the delay line comprising: a first group formed on a top portion of the PCB a plurality of delay elements; and a second plurality of delay 5 elements formed on a bottom portion of the PCB, the bottom portion being distinct from the top portion; and a plurality of vias formed in the PCB; Each of the first set of delay elements is electrically coupled to at least one of the second set of delay elements, wherein the corresponding delay elements of the first and second sets of delay elements are via the 10 through holes are interconnected, and wherein the first plurality of delay elements are disposed at an angle relative to the corresponding second plurality of delay elements. 9. A method of forming a solenoid delay line on a multilayer printed circuit board, the method comprising the steps of: forming a first plurality of delay elements on a portion of a first layer of the PCB; Forming a second plurality of delay elements on a portion of a second layer of the PCB, the second layer being distinct from the first layer; and forming a plurality of vias in the PCB; via the vias At least some of the plurality of delay elements of the first plurality of delay elements are electrically coupled to at least some of the second plurality of delay elements. 15