TW200803172A - Clock tree for programmable logic array devices - Google Patents

Abstract

A clock tree for PLAD is provided, with each logic element having an embedded circuit having a buffer connecting vertical bus wires to horizontal bus wires so that the clocks on each horizontal bus wire are synchronized, because the every horizontal wire gets the same capacitor and the same clock propagation gate delay,and the clock signals among the logic elements have the minimal clock skew.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a programmable logic array device, and more particularly to a clock tree design for a programmable logic array device. [Prior Art] A programmable logic array device (PLAD) is an electronic component that is used to construct a digital circuit. The core of this PLAD is a programmable logic array (pla) consisting of a set of programmable combined logic and flip-flops (F/F: flip-fi〇p). Because the pLA layout can be used to perform general logic functions, it can be a combination of combined logic and flip-flops. Unlike a logic gate with a fixed function, this PLAD has a function that is not fully defined at the time of manufacture. Before this PLAD can be used in a circuit it must be designed and planned. Various forms of programmable logic array devices have been developed over the years, including: PAL, GAL' epu, FPGAs, and the like. There is a high level of interest in the industry today for reconfigurable systems, including microprocessor circuits that include: some fixed functions, and other functions that can be changed by code executed on the processor. Due to the inherent design flexibility of pLAD, this is typically sold as a microprocessor with fixed core functionality surrounded by programmable logic. These devices allow the designer to focus on the design of the user without worrying about how to operate the microprocessor. The clock money is of importance and is often difficult to design for the PLAD because the clock signal is typically designed to be multiplexed, transmitted over long distances, and controlled by signals or data signals throughout the synchronization system. High speed operation. In addition, these clock signals are especially affected by the technology'. This is the reduction of the size of the transmission line. This long distance and the line impedance become quite large. This increased transmission line impedance is one of the main reasons why pulse distribution synchronization = monthly b performance is increasingly important. Finally, for the arrival of these clock signals, any 5 200803172, the control of the difference and uncertainty, will severely limit the maximum performance of this whole system. Li is now in the middle of the difference: when in the complex - digital device All clock network hybrids will cause unacceptable degradation in the overall system timing margin. This kind of problem is _ "clock offset, the problem, will cause disaster competition situation, where ^ correct data signal will be locked in the - register. The clock system of this synchronous digital system is appropriate The design must be mixed: it can meet the important timing requirements of this mosquito, and there will be no competition.

Regarding this 'Republic of China patent certificate number: 12 side 3, a method is disclosed to balance the - clock tree with _ state. The method includes: inserting a controllable buffer into a level of a clock tree, providing a controller to control a look-ahead layout of the controllable buffer to adjust two clocks that are not _ bits; and generating More currents are offset in the slow clock. This method allows the synchrophone to be turned off: the clock offset due to voltage drops or temperature changes. In addition, the Republic of China Patent Certificate No. 124 discloses a method for electronic design automation (EDA: Electr〇nic Design Aut 〇) to bypass multiple clock branches in the leg tool. The method includes measuring the delay of the pulse component at this time, and forming a buffer as a delay to the clock caused by the component. However, there is still a problem with minimizing pulse offset at this time, which is still a challenge for large-scale high-speed milk design and performance. SUMMARY OF THE INVENTION The object of the present invention is to overcome the disadvantages and disadvantages of the above-mentioned PL technology. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a circuit design for a clock tree that has minimal clock skew in a synchroscopic system. In order to achieve the above object of the present invention, the present invention provides a PUD whose buffer component has a buffer H, and the secret_hidden_hidden connection to the water system, so that the time is 200803172^=the time of the line on the line. The above-mentioned and other objects, features, aspects and advantages of the present invention will be apparent from the following detailed description. Further, the present invention can be understood in more detail by reading the following detailed description and embodiments with reference to the accompanying drawings. [Embodiment] FIG. 1 is a schematic diagram of a programmable logic array device (PLAD) according to the present invention. As in the first figure, the PLAD includes a plurality of columns and a plurality of rows of logic elements LEi, and the soil and the columns are not the first column and the jth row. The first! The real complement shown in the figure includes a logic element of 4χ4. However, the invention can be expanded to a larger size. For the array as in this embodiment, there are 8 vertical bus bars and 8 horizontal bus bars. Each row of logic elements is connected to two vertical banks _ for the input, and each contact element is connected to the two horizontal bus bars as the input. Therefore, 4x4 PUD requires vertical _ line and 8 horizontal hoist lines. Further, each of the logic elements LEi j has eight vertical bus bars and eight horizontal bus bars as inputs. Figure 2 is a schematic diagram of logic elements in a programmable logic array device in accordance with an embodiment of the present invention. As shown in FIG. 2, this logic element includes a combined logic unit 2〇1 and a clock buffer unit 202. The combined logic unit 2〇1 1 includes a plurality of combined logic and positive and negative elements to perform the desired function. For example, in FIG. 2, the embodiment of the combined logic unit 201 includes a connection: two 3_input logic units, and a positive and negative dwarf' so that the logic can perform its specific function. Instead, five inputs A, B, G, D, E, and (iv) input CAS from the previous stage are received, and the two results are output to two vertical bus lines. The clock buffer unit 2〇2 further includes two buffers, and each buffer connects eight vertical bus lines to one horizontal bus line and line. For example, each buffer can be implemented as a 7-200803172, 8- to-1 multiplexer. In practice, any vertical bus and horizontal bus lines can be used as a clock tree to transmit clock signals to the various logic elements in the PLAD. For example, if the component LEu calculates the clock signal and outputs it to the vertical bus bar 2j, the clock buffer unit 202 of each logical component transmits the clock signal on the vertical bus bar 2j. To the horizontal bus line, which can be used as a clock input to each logic element. The present invention has been described above with reference to the preferred embodiments, however, it should be understood that the invention is not limited to the details. Various alternatives and amendments are suggested in the above description, and it is claimed that there will be other alternatives and amendments to those of ordinary skill in the art. Accordingly, all of the alternatives and modifications are intended to be included in the scope of the invention as defined by the appended claims. FIG. 1 is a schematic diagram of a programmable logic array device in accordance with an embodiment of the present invention; Returning to a summary of logic elements in a programmable logic array device in accordance with an embodiment of the present invention

Figure. [Main component symbol description] 201 202 Combined logic unit Clock buffer unit 8

Claims (1)

200803172, the scope of the patent application: • - a plurality of logical elements of a logical tree dependent on the device (PLAD) configured as columns and rows; H a plurality of vertical bus lines connected to the rows of the logic elements; And a plurality of horizontal bus bars connected to the logic elements; wherein, each of the row of the rotating components is connected to the two money flow views such that the number of the vertical bus bars is in one row Logic elements are multiplied, and each of the logic elements of a column is connected to two of the horizontal bus bars ,m such that the number of the horizontal bus bars is two times the number of the logic elements in one column, and each of the logic elements has All of the vertical bus bars and the horizontal line are used as inputs. 卞汇级排2· The structure of claim 1 of the patent scope, wherein the logic component further comprises: combined logic, element, which includes multiple combinations Logic and flip-flops to perform the desired function; and ~ clock buffer s' Lin will (4) vertical sink line to the water dumping number buffer, each buffer with an N-to-丨 multiplex Implementation [3] The structure of claim 2, wherein the clock buffer unit further comprises two buffers. 4. The structure of claim 3, wherein the buffer H can be used as a direct current. Lin Qian horizontal level _ line of multi-work crying implementation. mouth ° 》· If you apply for the scope of the fourth item of the patent range, straight to the level of the Lin line has ··_capacitance, Qian Weizheng ϋ ϋ 各 输入 输入The same transmission gate delays the clock path.