200803121 九、發明說明： 【發明所屬之技術領域】 本發明已於2006年6月22日申請美國優先權，案 號60/805,480。本發明係有關於系統級晶片（s〇c)，尤 其是應用在系統級晶片中的位準轉換器與絕緣電路。 【先前技術】 第1圖係為使用-位準轉換器1〇〇的習知系統級晶 片SOC。在第一電壓域110和第二電料12〇之間 的訊號透過位準轉換器丨⑻轉換為對應的電隸圍。位 士轉換器100的做法已經有許多不同的習知技術，所以 實際的細節在此不詳述。然而在一般系統級晶片中 :電㈣m或第二電塵域120有的時候會關機或離 線，使得雛在位準轉換器丨⑼上的對應端點處於浮接 狀態⑺〇ating)。舉例來言兒，當端點Vl為浮接狀態時， 位準轉換器100可能會從端點¥2輸出一個不可測的隨機 訊號。如果第二電壓域120收到了該隨機訊號，可能使 整個系統會發生不可預期的錯誤。 【發明内容】 ，發明提出-種電壓轉換器，可將具有—第一電壓 的-第-訊號轉換為具有—第二電壓的―第二訊號。該 電壓轉換器主要包含-位準轉換器（levd s識㈦以及 -絕緣電路。該位準轉換器接收該第—訊號以產生該第 二訊號，而該絕緣電路•接於該位準轉換器的一標準輸 0758-A32291 TWF;MTKI-06-151 ;yeatsluo 5 200803121 出鳊，八電位競爭力低於該位準轉換哭山 器的輸入端在浮接狀態時，該絕緣電：幹：該：準轉換 以代替該第二訊號，而該替代訊號不受訊號 入端的浮接狀態影變。 μ位準轉換器輸 w / 曰 在-實施例中，該位準轉換器包含 -反相輸出端，兩者為邏輯互補，：輪出端和 為該標準輸出端，與該絕緣電路耦接： = 選 端包含-第—反相器和 而在則示準輸出 電路可以是—反相哭，於相益串_接。該絕緣 出端，將节第η在該第—反相器的輸 =心弟一反相器的輸出回饋到”―反相= 入化。该絕緣電路的電位競爭力低於“輸 此，當該位準轉換器的輸入端並非浮接換二藉 輪出端的電壓受到該位準轉換 二才^払準 干得拱态衫響，透過該第一和第 -反相讀出該第二訊號。當該位準轉換 ::接狀態時，該絕緣電路與該第 ：二 =貞住該第二訊號的狀態並持續輸出，即:二 端，例中，該反相輪出端被選為該標準輸出 ::純準輸出端輕接一第—反相器。其中該絕緣電 係：反相器’輸入端耦接在該第一反相器的輸出端， ★二反相器的輪出回饋到該第-反相器的輸入端。 =、巴緣電路的電位競爭力低於該位準轉換器，藉此，當 =位準轉換$的輸人端並非浮接狀態時，該標準輸出端 電虔受到該位準轉換器影響，透過該第-反相器輸出 6 〇758.A32291TWF;MTKI-〇6-151；yeatsluo 200803121 =第二訊號。當該位準轉㈣的輪 時:該絕緣電路與該第-反相器形成，鎖；電:= A弟：:::狀態並持續輸出’即成為該替代訊號。 轉換器，藉此，當該:=換=競爭力低於該位準 f弟波以位準轉換器的輪人端處於浮接狀能 :二出端的電墨受到該推捥電路的影響，鎖； 在-預_而持續輪出，即成 推 電路更進-步的可以是PMOS、NM〇s或電容亥推捥 【實施方式】 了列實施例具體的說明如何以較佳的方式 明。貫施例僅供說明—般應用的方式，而非用以： 發明的範圍。實際範圍以申請專利範圍所列為準。‘本 第2圖係為本發明實施例之—的系統級晶片 二電壓，換器2。。，具有自動絕緣功能。在第2 二 壓轉換器200具有兩個端點，端點 2 ，电 連接該第-電厂錢叫第二電壓物二^ 域110傳送至第二電厂輯no的訊號進行電麼:換 電壓轉換器包含位準轉換器1〇〇和 二轉:。该 該絕緣電路2〇2橋接於該位準轉換器1〇〇 ^路202。 二電壓域120的輸入端之間。當 别出端和第 田乐電壓域110運作於 075 8-A32291 TWF；MTKI-06-151 ;yeatsluo 7 200803121 =模式’傳送至端點V1上的訊號便 至端點V2供第二雷颅砧， 电免上丨牙、 電壓域12〇使用。但是當第一電壓域 關機日^端‘點V1京尤變成懸空的浮接狀態。此時絕緣 2 02開始發揮功效’阻止訊號從端點V2輸出。更且 體的說，絕緣帝枚^ w 甩 02提供了一替代訊號給端點V2，替 訊號已設定為具有已知的值，與端點νι的輸入狀態無 ，=緣電路202提供的可說是一種自動絕緣功能，不 的人為控制。該絕緣電路只需要耦接在位 二m 100的輸出端，並且給予一電壓源即可運作。 第3a和3b圖係為電壓轉換器3〇〇a中自動鎖閂電路 =tChmg)的實施例。在第3a圖中，電Μ轉換器30〇a ^ 了電晶體Mi，M2’ M3和M4，以及反相器1〇2, ι〇4 和、1〇6。反相輸出端a和同相輸出端B是邏輯互補的差 動對’其中之一可被選為標準輸出端。在本實施例中所 選擇的是同相輸出端B。端點V1接收到的訊號傳導至電 晶體奶和刚，而反相器、1〇4和1〇6串接在同相輸出端 B上以輸出轉換後的訊號。絕緣電路202係為一反相器 310’並聯逆接在反相器1〇4上，將反相器1〇4的輸出二 迴饋至反相器104的輸入端。反相器31〇和反相器 的組合形成一自動鎖閃電路，可以將端點C的電壓°鎖定 在一定值。反相器310在設計時刻意將其電位競爭力碉 低二當電1轉換器300a的輸入端未浮接時，會由電壓轉 換器300a決定同相輸出端B的電壓，並透過反相器1⑽ 和106將同相輸出端b的訊號傳送出去。當電壓轉換器 0758-A3229 lTWF;MTKI-06-l 51 ;yeatsluo 8 200803121 300a的輸入端成為浮接狀態時，端點v〗的電壓值變得 :可預測’於疋反相器310和反相器104所組成的自動 =電路開始發揮作用，鎖定端點C上的最後狀態而穩 〗出此即為替代訊號。值得注意的是，電壓轉換器 々做法已存在許多習知技術，在此只是舉例說明， 本發明> 並不限定使用哪一種位準轉換器。 第扑圖係為另一電壓轉換器300b的實施例，使用 !出糕a為標準輸出端。一反相器1〇8耦接在反相 1端A上用以輸出轉換後的訊號。而反相器別逆接 a反相$ 1G8的輸出再迴饋至反相器⑽的輸入端。 在山吊運作下，由於反相器31G的電位競爭力較差，所 以立而點V2的電位由娃赴v一 '由mi決疋。當端點vi處於浮接200803121 IX. INSTRUCTIONS: [Technical Field to Which the Invention Is Applicable] The present invention was filed on June 22, 2006, in the United States, with the number 60/805,480. This invention relates to system level wafers (s), particularly level shifters and isolation circuits used in system level wafers. [Prior Art] Fig. 1 is a conventional system-level wafer SOC using a - level shifter. The signal between the first voltage domain 110 and the second electrode 12A is converted to a corresponding electrical range by a level shifter 丨 (8). The practice of the semaphore converter 100 has many different conventional techniques, so the actual details are not detailed here. However, in a general system-level chip: the electric (four) m or the second electric dust domain 120 may be turned off or off, so that the corresponding end points on the level shifter 9 (9) are in a floating state (7) 〇 ating). For example, when the endpoint V1 is in a floating state, the level shifter 100 may output an untestable random signal from the endpoint ¥2. If the random signal is received by the second voltage domain 120, an unpredictable error may occur in the entire system. SUMMARY OF THE INVENTION The invention proposes a voltage converter that converts a -th signal having a first voltage into a second signal having a second voltage. The voltage converter mainly comprises a - level converter (levd s (7) and - an insulating circuit. The level converter receives the first signal to generate the second signal, and the insulating circuit is connected to the level converter A standard input 0758-A32291 TWF; MTKI-06-151; yeatsluo 5 200803121 out, the eight potential is lower than the level of the input of the crying mountain device in the floating state, the insulation power: dry: the : a quasi-conversion instead of the second signal, and the substitute signal is not affected by the floating state of the signal input. The μ level converter inputs w / 曰 In the embodiment, the level converter includes - an inverting output End, the two are logically complementary, the rounded end and the standard output are coupled to the insulated circuit: = the selected end includes a - the first inverter and the selected output circuit can be - an inverted cry, In the insulation output terminal, the output of the section η is fed back to the output of the inverter of the first inverter, "inverted = in." The potential competition of the insulated circuit The force is lower than "losing this, when the input of the level converter is not floating for two borrowing wheels The voltage of the terminal is subjected to the level conversion, and the second signal is read through the first and the first phase. When the level is switched: the state is connected, the insulation circuit is The second: the second = the state of the second signal and continues to output, that is: the second end, in the example, the output of the reverse wheel is selected as the standard output:: pure quasi-output end is connected to a first - inverting Wherein the insulated electrical system: the input end of the inverter is coupled to the output end of the first inverter, and the turn-off of the two inverters is fed back to the input end of the first-inverter. The potential competitiveness of the edge circuit is lower than the level converter, whereby when the input terminal of the = level conversion is not in a floating state, the standard output terminal is affected by the level converter, through the - Inverter output 6 〇 758.A32291TWF; MTKI-〇6-151; yeatsluo 200803121 = second signal. When the position is turned to (four) wheel: the insulation circuit is formed with the first-inverter, lock; := A brother:::: state and continue to output 'that becomes the replacement signal. Converter, by this, when: ===competition is lower than the level The wheel end of the quasi-converter is in a floating state: the electric ink of the second end is affected by the push circuit, and the lock is turned on; and the turn-on is performed in the pre-pre-, that is, the push-in circuit can be a PMOS, NM〇s or capacitors 实施 实施 实施 实施 实施 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥 捥The present invention is based on the scope of the patent application. 'This second figure is a system-level chip two voltage, converter 2 of the embodiment of the invention, with automatic insulation function. The second two-voltage converter 200 has two End point, end point 2, electrically connected to the first power plant money called the second voltage object 2 ^ domain 110 transmitted to the second power plant series no signal to power: the voltage converter includes a level shifter 1〇 〇 and two turns: The insulating circuit 2〇2 is bridged to the level converter 1 . Between the inputs of the two voltage domains 120. When the singularity and the Horizon voltage domain 110 operate at 075 8-A32291 TWF; MTKI-06-151; yeatsluo 7 200803121 = mode 'transmitted to the signal on the endpoint V1 to the end point V2 for the second thunder skull , electric free of fangs, voltage domain 12 〇 use. However, when the first voltage domain is turned off, the end point ‘point V1 Jingyu becomes a floating state. At this time, the insulation 2 02 starts to function. The blocking signal is output from the terminal V2. More specifically, the insulation element ^ w 甩 02 provides an alternative signal to the terminal V2, the signal has been set to have a known value, and the input state of the endpoint νι is not available, the edge circuit 202 provides Said to be an automatic insulation function, not artificial control. The insulation circuit only needs to be coupled to the output of the two m 100 and is operated by a voltage source. Figures 3a and 3b are embodiments of automatic latch circuit =tChmg in voltage converter 3A. In Fig. 3a, the power converter 30〇a ^ transistors Mi, M2' M3 and M4, and inverters 1〇2, ι〇4 and 1,〇6. The inverted output a and the non-inverting output B are logically complementary differential pairs, one of which can be selected as the standard output. The in-phase output terminal B is selected in this embodiment. The signal received by the terminal V1 is transmitted to the transistor milk and the battery, and the inverters, 1〇4 and 1〇6 are connected in series to the non-inverting output terminal B to output the converted signal. The insulating circuit 202 is an inverter 310' connected in parallel to the inverter 1〇4, and the output 2 of the inverter 1〇4 is fed back to the input terminal of the inverter 104. The combination of inverter 31 〇 and inverter forms an automatic lock flash circuit that locks the voltage ° of terminal C to a certain value. The inverter 310 intends to lower its potential competitiveness at the design time. When the input end of the power 1 converter 300a is not floating, the voltage of the non-inverting output terminal B is determined by the voltage converter 300a and passed through the inverter 1 (10). And 106 transmits the signal of the non-inverting output b. When the input of the voltage converter 0758-A3229 lTWF; MTKI-06-l 51; yeatsluo 8 200803121 300a becomes the floating state, the voltage value of the end point v becomes: predictable 'in the inverter 310 and the opposite The auto=circuit formed by the phaser 104 begins to function, locking the last state on the end point C and stabilizing this as a substitute signal. It is to be noted that there are many conventional techniques for voltage converters, and are merely illustrative here, and the present invention does not limit which level converter is used. The first map is an embodiment of another voltage converter 300b, using a cake a as a standard output. An inverter 1〇8 is coupled to the inverting terminal A for outputting the converted signal. The inverter is not reversed. The output of the inverting $1G8 is fed back to the input of the inverter (10). Under the operation of the mountain hoist, since the potential of the inverter 31G is less competitive, the potential of the V2 is set to go to the v-by-mi. When endpoint vi is floating
二'^不穩定且不可測，則反相器310開始發揮 的影響力超越M1和M3而主宰了反相輸出端A 準是端點V2的電壓被鎖定在最近一次訊號的位 半成為一種替代訊號而持續輸出。 ^ ^圖的貝施例介紹的是輕接於電壓轉換哭 中，〜ί 路（PUllmgCirCUlt)。在第如圖 中絶緣電路202係由—推婉電路41 供應電壓VCC和同相輪 ^麵接在 和M4 ^ 之間，具有比電晶體M2 的輪入端並沒有rf 爷運作時，電盧轉換器 電曰曰f:: 所以同相輸出端B的電壓由 _ σ M4主辛’以輸出轉換後的訊號。當電壓轉 9 0758-A3229 lTWF；MTKI-06-l 51 ;yeatsluo 200803121 的輸广端成為浮接狀態時，推捥電路4】0開始 二卢’主辛同相輸出端β的電壓’藉此輸出-替代 汛唬至端點V2。 Λ 的實施例。&的况明由PM0S組成一推捥電路410 接ί:應電壓ν〇^1Γ5的間極接地，源極和汲極個別輕 ^电土 和同相輸出端Β。如此的安排可持續 的將同相輸出端Β的電屬 、 PMOS的電位競爭力^拉升至供應㈣VCC。為了讓 晋η 对力柄，可將卩刪設計為長通道裝 置猎此，在正常運作時，同;f：目_屮被 體奶和M4主宰，而相輪“B的電位由電晶 接壯^ 辛“電屬轉換器彻a的輸入端為浮 至供：：：相輸出端B的電壓即被推捥電路41〇拉升The second '^ is unstable and unmeasurable, then the inverter 310 begins to exert its influence beyond M1 and M3 and dominates the inverting output A. The voltage at the end point V2 is locked in the bit half of the most recent signal. The signal continues to output. The ^^ figure of the example of the introduction is lightly connected to the voltage conversion cry, ~ί Road (PUllmgCirCUlt). In the figure, the insulating circuit 202 is connected between the supply voltage VCC and the in-phase wheel surface and M4^, and has no more than the rf operation of the transistor M2. The device 曰曰f:: Therefore, the voltage of the non-inverting output terminal B is outputted by _ σ M4 main symplectic signal. When the voltage turns to 9 0758-A3229 lTWF; MTKI-06-l 51; yeatsluo 200803121 when the wide end of the transmission becomes the floating state, the push circuit 4] 0 starts the second voltage 'the voltage of the main symplectic phase output terminal β' - Replace 汛唬 to endpoint V2.实施 embodiment. The condition of & is composed of PM0S. A push circuit 410 is connected to ί: the voltage between the ν〇^1Γ5 is grounded, the source and the drain are lightly electric and the non-inverting output is Β. Such an arrangement can continuously pull the potential of the non-inverting output terminal and the potential competitiveness of the PMOS to supply (four) VCC. In order to make Jin η the force handle, the 卩 卩 can be designed as a long-channel device to hunt this, in normal operation, the same; f: _ _ _ is dominated by body milk and M4, while the phase wheel "B potential is strengthened by electro-crystal ^ The input of the symplectic "electrical converter" is floating for supply::: The voltage at the output terminal B is pulled up by the push circuit 41
至供應電壓VCC。 V 第4C目係以電容實作推捥電路41〇的實施例。該電 :的兩鳊個別耦接同相輸出端B和供應電壓vcc…亥 =轉換器4_的輸人端浮接時，電晶體M2和 :位㈣力減弱而無法驅動同相輸 =叫透過電晶體M2)將同相輸出端 =rrc的位準:換言之同相輸出端b是:在= 出端β 的狀恶° #此方式’該電容可使同相輸 ^呆持在一個位準，不受到電壓轉換器條 子接衫響。為了確保推捥電路410中電容的電 ===影響位準轉換器⑽的正常運作，該電容容 些。藉此，在正常運作時，同相輸出端B 电位疋由電晶體M2和M4決定。當電壓轉換器她 〇758-A32291TWF；MTKl-〇6- 15l；yeatsluo 10 200803121 =相輸出端B的電位即可被該推婉電 峪410拉升至供應電壓vcc。 在第4d圖的實施例中說明由推捥 絕緣電路2 02。該絕緣電路2 路4 2 〇所貝作的 ^ π 0 ^ Μ ^ ^ ^ 耦接地線和同相輸出端Β :推^===的電位競爭力比電壓轉換器4_ 運作是相同的，㈣壓的電位接地。基本 電晶體Μ2和Μ4γ宰了轉^：0；：的輸入端未浮接時， 當電壓轉換器400b的輸二端、i接，β的電#。相對的， 發揮功效，主宰了二:接:電 1立=拉至地線電a。此即為推按電路猶所產生的替 弟4e圖係為推捥電路42〇由 例。其中麵s的閉_接供應_ vee^ 一貝細 個別接至地線和同相輸出端β 〜及極 端B的電位被下拉至地線電愿。為=== ，爭力舜弱，可採用長通道架構來設計位 ιΓ主屋宰轉了換同"相：山的輸入端未浮接時 Μ4主辛了冋相輸出端Β的 ^ 4_的輸入端浮接時，推捥^ ^對的，當電屋轉換器 宰了同相輸出端Β的電:叫 線電壓。 心點V2的電位被下拉至地 二4f圖係為由電容實作推摘電路働的另一 ”中電容的兩端個勒接同相輸出端B和地線^ 0758.A32291TWF;MTKI-06-151;yeatsluo 11 200803121 該電壓轉換器400b的輸入端浮接時，電晶體M2和M4 的電位競爭力減弱而無法驅動同相輸出端B，於是該推 捥電路420 (透過電晶體M4)將同相輸出端B拉降至接 近地線電壓。換言之同相輸出端B是處在邏輯低電位（bit 〇)的狀態。藉此方式，該電容可使同相輸出端B的電位 保持在一個位準，不受到電壓轉換器400b輸入端的浮接 影響。為了確保推捥電路410中電容的電位競爭力不影 響位準轉換器1〇〇的正常運作，該電容容量可以設小一 些。藉此，在正常運作時，同相輸出端B的電位是由電 晶體M2和M4決定。當電壓轉換器400b的輸入端浮接 時，同相輸出端B的電位即可被該推捥電路420拉降至 地。在上述實施例中，推捥電路410和420不限定是由 電容、NMOS或PMOS組成。其精神是一種能產生與端 點VI無關的固定電壓的電路。 第5a和5f圖的實施例介紹的是耦接於電壓轉換器 500a另一反相輸出端A的推捥電路架構。由於反相輸出 端A輸出的電壓與端點V1是反相的，所以使用一反相 器108 |馬接在反相輸出端A，進行一次反相後由端點V2 輸出轉換後的電壓。推捥電路510特意設計成具備較弱 的電位競爭力，可在特定情況下將反相輸出端A的電位 拉至固定位準。與第4a圖相似地，在第5a圖中，在正 常運作時，電壓轉換器500a的輸入端並沒有浮接，所以 反相輸出端A的電壓由電晶體Ml和M3主宰，並透過反 相器108輸出轉換後的訊號。當電壓轉換器500a的輸入 0758-A32291TWF;MTKI-06-151;yeatsluo 12 200803121 . 端成為浮接狀態時，推捥電路510開始發揮作用，主宰 反相輸出端A的電壓，藉此輸出一替代訊號至端點V2。 第5b圖更具體的說明由PMOS組成一推捥電路510 的實施例。其中PMOS的閘極接地，源極和汲極個別麵 接至供應電壓VCC和反相輸出端A。如此的安排可持續 的將反相輸出端A的電壓拉升至供應電壓VCC。為了讓 PMOS的電位競爭力減弱，可將PMOS設計為長通道裝 置。藉此，在正常運作時，反相輸出端A的電位由電晶 體Ml和M3主宰，而當電壓轉換器500a的輸入端為浮 接狀態時，反相輸出端A的電壓即被推捥電路510拉升 至供應電壓VCC而成為一種替代訊號，接著透過反相器 108輸出至端點V2。 第5c圖係以電容實作推捥電路510的實施例。該電 容的兩端個別耦接反相輸出端A和供應電壓VCC。當該 電壓轉換器500a的輸入端浮接時，電晶體Ml和M3的 電位競爭力減弱而無法驅動反相輸出端A，於是該推捥 電路510 (透過電晶體Ml)將反相輸出端A拉升至接近 供應電壓VCC的位準。換言之反相輸出端A是處在邏輯 高電位（bit 1)的狀態。藉此方式，該電容可使反相輸 出端A的電位保持在一個位準，不受到電壓轉換器500a 輸入端的浮接影響。為了確保推捥電路510中電容的電 位競爭力不影響位準轉換器100的正常運作，該電容容 量可以設小一些。藉此，在正常運作時，反相輸出端A 的電位是由電晶體Ml和M3決定。當電壓轉換器500a 0758-A3229 lTWF;MTKI-06-l 51 ;yeatsluo 13 200803121 ， 的輸入端浮接時，反相輸出端A的電位即可被該推捥電 路510拉升至供應電壓Vcc。而透過反相器1〇8，在端點 V2知輸出的是反相後具有地線電位的替代訊號。 在第5d圖的實施例中說明由推捥電路520所實作的 絕緣電路202。該絕緣電路202耦接地線和反相輸出端a 之間。該推捥電路520的電位競爭力比電壓轉換器500b 弱。推捥電路520可將反相輸出端A的電位接地。基本 運作是相似的，當電壓轉換器500b的輸入端未浮接時， 電晶體Ml和M3主宰了反相輸出端A的電位。相對的， 當電壓轉換器500b的輸入端浮接時，推捥電路520開始 發揮功效，主宰了反相輸出端A的電位，使反相輸出端 A的電位被下拉至地線電壓。接著透過反相器1〇8，在端 點V2端輸出的是反相後具有供應電壓VCC的替代訊號。 弟5 e圖係為推婉電路5 2 0由ΝΜ Ο S組成的一實施 例。其中NMOS的閘極编接供應電壓VCC，源極和没極 個別接至地線和反相輸出端A。如此設計可使反相輸出 端A的電位被下拉至地線電壓。為了確保NMOS的電位 競爭力夠弱，可採用長通道架構來設計NMOS。藉此， 當電壓轉換器500b的輸入端未浮接時，電晶體Ml和 M3主宰了反相輸出端A的電位。相對的，當電壓轉換器 500b的輸入端浮接時，推捥電路520開始發揮功效，主 宰了反相輸出端A的電位，使反相輸出端A的電位被下 拉至地線電壓。 第5f圖係為由電容實作推捥電路520的另一實施 0758-A32291TWF;MTKI-06-151;yeatsluo 14 200803121 例。其中電容的兩端個別耦接反相輸出端A和地線。當 該電壓轉換器500b的輸入端浮接時，電晶體Ml和M3 的電位競爭力減弱而無法驅動反相輸出端A，於是透過 電晶體M3，反相輸出端A被拉降至接近地線電壓。換言 之反相輸出端A是處在邏輯低電位（bit 0 )的狀態。藉 此方式，該電容可使反相輸出端A的電位保持在一個位 準，不受到電壓轉換器500b輸入端的浮接影響。為了確 保推捥電路520中電容的電位競爭力不影響位準轉換器 100的正常運作，該電容容量可以設小一些。藉此，在正 常運作時，反相輸出端A的電位是由電晶體Ml和M3 決定。當電壓轉換器500b的輸入端浮接時，反相輸出端 A的電位即可被該推捥電路520拉降至地。在上述實施 例中，推捥電路5 10和推捥電路520不限定是由電容、 NMOS或PMOS組成。其精神是一種能產生與端點VI 無關的固定電壓的電路。 上述位準轉換器可以是單向或雙向，其架構不限於 實施例所述。有了自動絕緣電路，系統級晶片便能達成 高品質、高效能與低成本的要求。雖然本發明以較佳實 施例說明如上，但可以理解的是本發明的範圍未必如此 限定。相對的，任何基於相同精神或對習知技術者為顯 而易見的改良皆在本發明涵蓋範圍内。因此專利要求範 圍必須以最廣義的方式解讀。 【圖式簡單說明】 0758-A32291TWF;MTKI-06-151;yeatsluo 15 200803121 . 第1圖係為一習知的系統級晶片，採用一位準轉換 器 100 ; 第2圖係為本發明實施例之一的系統級晶片，採用 包含絕緣電路的一電壓轉換器； 第3a和3b圖係為電壓轉換器200中自動鎖閂電路 的實施例； 第4a到4f圖係為位準轉換器100中推捥電路耦接 到同相輸出端的實施例；以及 第5a到5f圖係為位準轉換器100中推捥電路反相 輸出端的實施例。 【主要元件符號說明】 100〜位準轉換器； 102〜反相器； 104〜反相器； 106〜反相器； 108〜反相器； 110〜第一電壓域； 120〜第二電壓域； 200〜電壓轉換器； 202〜絕緣電路； 300a〜電壓轉換器； 300b〜電壓轉換器； 310〜反相器； 400a〜電壓轉換器； 400b〜電壓轉換器； 410〜推捥電路； 420〜推捥電路； 500a〜電壓轉換器； 510〜推婉電路； 520〜推捥電路。 0758-A32291TWF;MTKI-06-151 ;yeatsluo 16To supply voltage VCC. V No. 4C is an embodiment in which a capacitor is implemented as a push circuit 41A. The two poles of the electric coupling are connected to the non-inverting output terminal B and the supply voltage vcc...hai = converter 4_ is connected to the input terminal, the transistor M2 and the: bit (four) force are weakened and cannot drive the in-phase transmission = called transmission Crystal M2) will be the output of the non-inverting output = rrc: in other words, the non-inverting output b is: at the = end of the β-like ° ° This way the capacitor can make the in-phase output hold a level, not subject to voltage The converter slivers. To ensure that the power of the capacitor in the push circuit 410 === affects the normal operation of the level converter (10), the capacitance is more. Thereby, during normal operation, the non-inverting output terminal B potential is determined by transistors M2 and M4. When the voltage converter is 〇758-A32291TWF; MTKl-〇6- 15l; yeatsluo 10 200803121 = the potential of the phase output terminal B can be pulled up to the supply voltage vcc by the push 婉 410. In the embodiment of Fig. 4d, the insulating circuit 222 is described. The π 0 ^ Μ ^ ^ ^ of the insulated circuit 2 is connected to the ground line and the non-inverting output terminal Β: the potential competitiveness of the push ==== is the same as that of the voltage converter 4_, (4) The potential is grounded. The basic transistor Μ2 and Μ4γ are slaughtered. When the input terminal of the converter is not floating, when the input terminal of the voltage converter 400b is connected to the second terminal, the power of the beta is #. Relatively, play the role, dominate the second: connect: electricity 1 vertical = pull to ground wire a. This is the case where the pusher circuit 4e is a push-pull circuit 42. The closing _ supply _ vee^ one of the surface s is connected to the ground and the non-inverting output terminals β ～ and the potential of the terminal B are pulled down to the ground. For ===, the competition is weak, and the long-channel architecture can be used to design the position ιΓ主屋宰转转同同"phase: the input end of the mountain is not floating when Μ4 main 辛 冋 phase output terminal ^ ^ 4 When the input terminal of _ is floating, push 捥 ^ ^, when the electric house converter kills the electricity of the non-inverting output terminal: called the line voltage. The potential of the heart point V2 is pulled down to the ground 2f. The figure is the other one of the capacitors. The two ends of the middle capacitor are connected to the in-phase output terminal B and the ground line ^ 0758.A32291TWF; MTKI-06- 151;yeatsluo 11 200803121 When the input terminal of the voltage converter 400b is floating, the potential competitiveness of the transistors M2 and M4 is weakened and the non-inverting output terminal B cannot be driven, so the push circuit 420 (transmitted through the transistor M4) outputs the same phase. The terminal B is pulled down to the ground voltage. In other words, the non-inverting output terminal B is in a state of logic low (bit 〇). In this way, the capacitor can maintain the potential of the non-inverting output terminal B at a level, without being affected by The floating connection effect of the input terminal of the voltage converter 400b. In order to ensure that the potential competitiveness of the capacitor in the push circuit 410 does not affect the normal operation of the level converter 1〇〇, the capacitance capacity can be set smaller. The potential of the non-inverting output terminal B is determined by the transistors M2 and M4. When the input terminal of the voltage converter 400b is floating, the potential of the non-inverting output terminal B can be pulled down to the ground by the push circuit 420. In the example, the push circuit 410 420 is not limited to being composed of a capacitor, an NMOS or a PMOS. Its spirit is a circuit capable of generating a fixed voltage independent of the endpoint VI. The embodiments of Figures 5a and 5f illustrate another coupling coupled to the voltage converter 500a. The push-pull circuit architecture of the phase output terminal A. Since the voltage output from the inverting output terminal A is inverted from the terminal V1, an inverter 108 is used to connect the inverter to the inverting output terminal A for inversion. The converted voltage is output by the terminal V2. The push circuit 510 is deliberately designed to have a weak potential competitiveness, and the potential of the inverting output terminal A can be pulled to a fixed level in a specific case. Similarly to Fig. 4a In Fig. 5a, during normal operation, the input terminal of the voltage converter 500a is not floating, so the voltage of the inverting output terminal A is dominated by the transistors M1 and M3, and the converted output is output through the inverter 108. When the voltage converter 500a is input 0758-A32291TWF; MTKI-06-151; yeatsluo 12 200803121. When the terminal is in the floating state, the push circuit 510 starts to function, and the voltage of the inverting output terminal A is dominated, thereby outputting An alternate signal to endpoint V2. 5b The figure more particularly illustrates an embodiment in which a PMOS circuit is formed by a PMOS. The gate of the PMOS is grounded, the source and drain are individually connected to the supply voltage VCC and the inverting output A. Such an arrangement will be sustainable. The voltage at the inverting output terminal A is pulled up to the supply voltage VCC. In order to weaken the potential competitiveness of the PMOS, the PMOS can be designed as a long channel device. Thereby, in normal operation, the potential of the inverting output terminal A is made up of a transistor. Ml and M3 dominate, and when the input terminal of the voltage converter 500a is in a floating state, the voltage of the inverting output terminal A is pulled up by the push circuit 510 to the supply voltage VCC to become a substitute signal, and then passed through the inverter. 108 outputs to endpoint V2. Figure 5c shows an embodiment of a push-pull circuit 510 implemented as a capacitor. Both ends of the capacitor are individually coupled to the inverting output terminal A and the supply voltage VCC. When the input terminal of the voltage converter 500a is floating, the potential competitiveness of the transistors M1 and M3 is weakened and the inverting output terminal A cannot be driven, so the push circuit 510 (through the transistor M1) will invert the output terminal A. Pull up to a level close to the supply voltage VCC. In other words, the inverting output terminal A is in a state of logic high (bit 1). In this way, the capacitor maintains the potential of the inverting output terminal A at a level that is not affected by the floating connection at the input of the voltage converter 500a. In order to ensure that the potential competitiveness of the capacitor in the push circuit 510 does not affect the normal operation of the level converter 100, the capacitance can be set smaller. Thereby, in normal operation, the potential of the inverting output terminal A is determined by the transistors M1 and M3. When the input terminal of the voltage converter 500a 0758-A3229 lTWF; MTKI-06-l 51; yeatsluo 13 200803121 is floated, the potential of the inverting output terminal A can be pulled up to the supply voltage Vcc by the push circuit 510. And through the inverter 1 〇 8, at the end point V2, the output is an alternate signal having a ground potential after the inversion. The insulating circuit 202 implemented by the push circuit 520 is illustrated in the embodiment of Fig. 5d. The insulating circuit 202 is coupled between the ground line and the inverting output terminal a. The potential of the push circuit 520 is weaker than that of the voltage converter 500b. The push circuit 520 can ground the potential of the inverting output terminal A. The basic operation is similar. When the input of the voltage converter 500b is not floating, the transistors M1 and M3 dominate the potential of the inverting output A. In contrast, when the input terminal of the voltage converter 500b is floating, the push circuit 520 starts to function, and the potential of the inverting output terminal A is dominated, so that the potential of the inverting output terminal A is pulled down to the ground line voltage. Then, through the inverter 1〇8, the output at the terminal V2 terminal is an alternate signal having the supply voltage VCC after the inversion. The 5 e diagram is an embodiment in which the push circuit 5 2 0 is composed of ΝΜ Ο S. The gate of the NMOS is connected to the supply voltage VCC, and the source and the gate are individually connected to the ground and the inverting output A. This is designed so that the potential of the inverting output terminal A is pulled down to the ground line voltage. To ensure that the potential of the NMOS is weak enough, a long channel architecture can be used to design the NMOS. Thereby, when the input terminal of the voltage converter 500b is not floating, the transistors M1 and M3 dominate the potential of the inverting output terminal A. In contrast, when the input terminal of the voltage converter 500b is floating, the push circuit 520 starts to function, and the potential of the inverting output terminal A is dominated, so that the potential of the inverting output terminal A is pulled down to the ground line voltage. Figure 5f is another implementation of a push-pull circuit 520 implemented by a capacitor 0758-A32291TWF; MTKI-06-151; yeatsluo 14 200803121. The two ends of the capacitor are individually coupled to the inverting output terminal A and the ground. When the input terminal of the voltage converter 500b is floating, the potential competitiveness of the transistors M1 and M3 is weakened and the inverting output terminal A cannot be driven, so that the inverting output terminal A is pulled down to the ground through the transistor M3. Voltage. In other words, the inverting output terminal A is in a state of logic low (bit 0). In this way, the capacitor maintains the potential of the inverting output terminal A at a level that is not affected by the floating connection at the input of the voltage converter 500b. In order to ensure that the potential competitiveness of the capacitor in the push circuit 520 does not affect the normal operation of the level converter 100, the capacitance capacity can be set smaller. Thereby, during normal operation, the potential of the inverting output terminal A is determined by the transistors M1 and M3. When the input of the voltage converter 500b is floating, the potential of the inverting output terminal A can be pulled down to the ground by the push circuit 520. In the above embodiment, the push circuit 5 10 and the push circuit 520 are not limited to being composed of a capacitor, an NMOS or a PMOS. The spirit is a circuit that produces a fixed voltage that is independent of the endpoint VI. The level converter described above may be unidirectional or bidirectional, and the architecture thereof is not limited to the embodiment. With automatic insulation, system-level wafers are capable of high quality, high efficiency and low cost. While the invention has been described above by way of a preferred embodiment, it is understood that the scope of the invention is not necessarily limited. In contrast, any improvement that is obvious to those skilled in the art or to those skilled in the art is within the scope of the invention. Therefore, the scope of patent claims must be interpreted in the broadest sense. [Simple diagram] 0758-A32291TWF; MTKI-06-151; yeatsluo 15 200803121. Figure 1 is a conventional system-level chip using a one-bit converter 100; Figure 2 is an embodiment of the present invention One of the system level wafers uses a voltage converter including an insulating circuit; the 3a and 3b diagrams are embodiments of the automatic latch circuit in the voltage converter 200; the 4a to 4f diagrams are in the level shifter 100 An embodiment in which the push circuit is coupled to the non-inverting output; and the 5a through 5f are embodiments of the inverting output of the push circuit in the level shifter 100. [Main component symbol description] 100~bit level converter; 102~inverter; 104~inverter; 106~inverter; 108~inverter; 110~first voltage domain; 120~second voltage domain 200~voltage converter; 202~insulated circuit; 300a~voltage converter; 300b~voltage converter; 310~inverter; 400a~voltage converter; 400b~voltage converter; 410~push circuit; 420~ Push circuit; 500a~ voltage converter; 510~ push circuit; 520~ push circuit. 0758-A32291TWF; MTKI-06-151; yeatsluo 16