TW200802574A - Method of minimizing delamination of a layer - Google Patents

Method of minimizing delamination of a layer

Info

Publication number
TW200802574A
TW200802574A TW096109431A TW96109431A TW200802574A TW 200802574 A TW200802574 A TW 200802574A TW 096109431 A TW096109431 A TW 096109431A TW 96109431 A TW96109431 A TW 96109431A TW 200802574 A TW200802574 A TW 200802574A
Authority
TW
Taiwan
Prior art keywords
layer
corner
angle
slanted edge
degrees
Prior art date
Application number
TW096109431A
Other languages
Chinese (zh)
Inventor
Kevin Cooper
Srdjan Kordic
Maurice Rivoire
Original Assignee
Freescale Semiconductor Inc
St Microelectronics Crolles 2
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, St Microelectronics Crolles 2 filed Critical Freescale Semiconductor Inc
Publication of TW200802574A publication Critical patent/TW200802574A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B9/00—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
    • B24B9/02—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
    • B24B9/06—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
    • B24B9/065—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

A method of minimizing delamination of a layer (14, 16, or 18), the method includes providing a semiconductor substrate (12), forming a first layer (14) over the semiconductor substrate, wherein the first layer has a first corner (20) and the first corner has a first angle of approximately 90 degrees; forming a second layer (16) over the first layer, wherein the second layer has a second corner (20) and the second corner has a second angle of approximately 90 degrees, and modifying the first and second corners to form a first slanted edge (50, 60, or 70) of the second layer, wherein the first slanted edge and the second slanted edge are continuous with each other and the first slanted edge forms a third angle with respect to the semiconductor substrate, wherein the third angle is less than 30 degrees.
TW096109431A 2006-03-17 2007-03-19 Method of minimizing delamination of a layer TW200802574A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2006/004034 WO2007107176A1 (en) 2006-03-17 2006-03-17 Method of reducing risk of delamination of a layer of a semiconductor device

Publications (1)

Publication Number Publication Date
TW200802574A true TW200802574A (en) 2008-01-01

Family

ID=37499349

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096109431A TW200802574A (en) 2006-03-17 2007-03-19 Method of minimizing delamination of a layer

Country Status (2)

Country Link
TW (1) TW200802574A (en)
WO (1) WO2007107176A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110875241A (en) * 2018-08-29 2020-03-10 台湾积体电路制造股份有限公司 Method for forming a semiconductor-on-insulator (SOI) substrate

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2213415A1 (en) * 2009-01-29 2010-08-04 S.O.I. TEC Silicon Device for polishing the edge of a semiconductor substrate
JP7018873B2 (en) 2016-05-27 2022-02-14 浜松ホトニクス株式会社 Fabry-Perot Interference Filter Manufacturing Method
JP6341959B2 (en) 2016-05-27 2018-06-13 浜松ホトニクス株式会社 Manufacturing method of Fabry-Perot interference filter
CN109477958A (en) * 2016-08-24 2019-03-15 浜松光子学株式会社 Fabry-Perot interference optical filter
KR102299845B1 (en) * 2016-08-24 2021-09-09 하마마츠 포토닉스 가부시키가이샤 Fabry-Perot interference filter

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188921A (en) * 1983-04-12 1984-10-26 Nec Corp Manufacture of dielectric isolation substrate
JP2001044147A (en) * 1999-08-04 2001-02-16 Mitsubishi Materials Silicon Corp Method of forming beveled surface of semiconductor wafer
US6328641B1 (en) * 2000-02-01 2001-12-11 Advanced Micro Devices, Inc. Method and apparatus for polishing an outer edge ring on a semiconductor wafer
KR100789205B1 (en) * 2000-03-29 2007-12-31 신에쯔 한도타이 가부시키가이샤 Production method for silicon wafer and soi wafer, and soi wafer
US6936546B2 (en) * 2002-04-26 2005-08-30 Accretech Usa, Inc. Apparatus for shaping thin films in the near-edge regions of in-process semiconductor substrates
DE10220647C1 (en) * 2002-05-08 2003-08-21 Infineon Technologies Ag Semiconductor wafer peripheral edge shaping method has material removed from peripheral edge of wafer until surface layer applied to inner part of one of its major surfaces is reached
JP2006093402A (en) * 2004-09-24 2006-04-06 Fujitsu Ltd Method for manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110875241A (en) * 2018-08-29 2020-03-10 台湾积体电路制造股份有限公司 Method for forming a semiconductor-on-insulator (SOI) substrate
TWI754161B (en) * 2018-08-29 2022-02-01 台灣積體電路製造股份有限公司 A semiconductor-on-insulator (soi) substrate and method for forming the same
CN110875241B (en) * 2018-08-29 2023-09-19 台湾积体电路制造股份有限公司 Method for forming a semiconductor-on-insulator (SOI) substrate

Also Published As

Publication number Publication date
WO2007107176A1 (en) 2007-09-27

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