TW200739419A - Prediction mechanism of a program backward jump instruction - Google Patents

Prediction mechanism of a program backward jump instruction

Info

Publication number
TW200739419A
TW200739419A TW095112523A TW95112523A TW200739419A TW 200739419 A TW200739419 A TW 200739419A TW 095112523 A TW095112523 A TW 095112523A TW 95112523 A TW95112523 A TW 95112523A TW 200739419 A TW200739419 A TW 200739419A
Authority
TW
Taiwan
Prior art keywords
branch
queue
prediction
loop
net type
Prior art date
Application number
TW095112523A
Other languages
English (en)
Other versions
TWI307040B (zh
Inventor
Lei Wang
Original Assignee
Univ Feng Chia
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Feng Chia filed Critical Univ Feng Chia
Priority to TW095112523A priority Critical patent/TW200739419A/zh
Priority to US11/500,298 priority patent/US20070239975A1/en
Publication of TW200739419A publication Critical patent/TW200739419A/zh
Application granted granted Critical
Publication of TWI307040B publication Critical patent/TWI307040B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
TW095112523A 2006-04-07 2006-04-07 Prediction mechanism of a program backward jump instruction TW200739419A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW095112523A TW200739419A (en) 2006-04-07 2006-04-07 Prediction mechanism of a program backward jump instruction
US11/500,298 US20070239975A1 (en) 2006-04-07 2006-08-08 Programmable backward jump instruction prediction mechanism

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095112523A TW200739419A (en) 2006-04-07 2006-04-07 Prediction mechanism of a program backward jump instruction

Publications (2)

Publication Number Publication Date
TW200739419A true TW200739419A (en) 2007-10-16
TWI307040B TWI307040B (zh) 2009-03-01

Family

ID=38576945

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095112523A TW200739419A (en) 2006-04-07 2006-04-07 Prediction mechanism of a program backward jump instruction

Country Status (2)

Country Link
US (1) US20070239975A1 (zh)
TW (1) TW200739419A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8612944B2 (en) 2008-04-17 2013-12-17 Qualcomm Incorporated Code evaluation for in-order processing

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7984279B2 (en) * 2006-11-03 2011-07-19 Qualcomm Incorporated System and method for using a working global history register
FR2910144A1 (fr) * 2006-12-18 2008-06-20 St Microelectronics Sa Procede et dispositif de detection errones au cours de l'execution d'un programme.
US8438003B2 (en) * 2007-04-12 2013-05-07 Cadence Design Systems, Inc. Methods for improved simulation of integrated circuit designs
US8160981B2 (en) * 2007-09-25 2012-04-17 Saffron Technology, Inc. Event-based anticipation systems, methods and computer program products for associative memories wherein times of future events occurring are predicted
US10698859B2 (en) 2009-09-18 2020-06-30 The Board Of Regents Of The University Of Texas System Data multicasting with router replication and target instruction identification in a distributed multi-core processing architecture
JP5707011B2 (ja) 2010-06-18 2015-04-22 ボード・オブ・リージエンツ，ザ・ユニバーシテイ・オブ・テキサス・システム 統合分岐先・述語予測
WO2013100998A1 (en) * 2011-12-28 2013-07-04 Intel Corporation Processor with second jump execution unit for branch misprediction
US9507600B2 (en) * 2014-01-27 2016-11-29 Texas Instruments Deutschland Gmbh Processor loop buffer
US10402200B2 (en) 2015-06-26 2019-09-03 Samsung Electronics Co., Ltd. High performance zero bubble conditional branch prediction using micro branch target buffer
US11016770B2 (en) 2015-09-19 2021-05-25 Microsoft Technology Licensing, Llc Distinct system registers for logical processors
US10936316B2 (en) 2015-09-19 2021-03-02 Microsoft Technology Licensing, Llc Dense read encoding for dataflow ISA
US10198263B2 (en) 2015-09-19 2019-02-05 Microsoft Technology Licensing, Llc Write nullification
US10678544B2 (en) 2015-09-19 2020-06-09 Microsoft Technology Licensing, Llc Initiating instruction block execution using a register access instruction
US10871967B2 (en) 2015-09-19 2020-12-22 Microsoft Technology Licensing, Llc Register read/write ordering
US10452399B2 (en) 2015-09-19 2019-10-22 Microsoft Technology Licensing, Llc Broadcast channel architectures for block-based processors
US20170083327A1 (en) 2015-09-19 2017-03-23 Microsoft Technology Licensing, Llc Implicit program order
US10776115B2 (en) 2015-09-19 2020-09-15 Microsoft Technology Licensing, Llc Debug support for block-based processor
US10180840B2 (en) 2015-09-19 2019-01-15 Microsoft Technology Licensing, Llc Dynamic generation of null instructions
US11126433B2 (en) 2015-09-19 2021-09-21 Microsoft Technology Licensing, Llc Block-based processor core composition register
US10768936B2 (en) 2015-09-19 2020-09-08 Microsoft Technology Licensing, Llc Block-based processor including topology and control registers to indicate resource sharing and size of logical processor
US11681531B2 (en) 2015-09-19 2023-06-20 Microsoft Technology Licensing, Llc Generation and use of memory access instruction order encodings
US10719321B2 (en) 2015-09-19 2020-07-21 Microsoft Technology Licensing, Llc Prefetching instruction blocks
GB2563582B (en) * 2017-06-16 2020-01-01 Imagination Tech Ltd Methods and systems for inter-pipeline data hazard avoidance
CN111240682A (zh) * 2018-11-28 2020-06-05 深圳市中兴微电子技术有限公司 一种指令数据的处理方法及装置、设备、存储介质
US11550623B2 (en) * 2018-12-28 2023-01-10 Beijing Voyager Technology Co., Ltd. Distributed system task management using a simulated clock
WO2020139967A1 (en) 2018-12-28 2020-07-02 Didi Research America, Llc Distributed system execution using a serial timeline
CN110457208B (zh) * 2019-07-16 2023-01-06 百度在线网络技术（北京）有限公司 符号执行的引导方法、装置、设备及计算机可读存储介质
US11809790B2 (en) * 2020-09-22 2023-11-07 Beijing Voyager Technology Co., Ltd. Architecture for distributed system simulation timing alignment
US11740906B2 (en) * 2021-02-25 2023-08-29 Huawei Technologies Co., Ltd. Methods and systems for nested stream prefetching for general purpose central processing units
CN113868899B (zh) * 2021-12-03 2022-03-04 苏州浪潮智能科技有限公司 一种分支指令处理方法、系统、设备及计算机存储介质

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5909573A (en) * 1996-03-28 1999-06-01 Intel Corporation Method of branch prediction using loop counters
US5752014A (en) * 1996-04-29 1998-05-12 International Business Machines Corporation Automatic selection of branch prediction methodology for subsequent branch instruction based on outcome of previous branch prediction
US7085920B2 (en) * 2000-02-02 2006-08-01 Fujitsu Limited Branch prediction method, arithmetic and logic unit, and information processing apparatus for performing brach prediction at the time of occurrence of a branch instruction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8612944B2 (en) 2008-04-17 2013-12-17 Qualcomm Incorporated Code evaluation for in-order processing

Also Published As

Publication number Publication date
TWI307040B (zh) 2009-03-01
US20070239975A1 (en) 2007-10-11

Similar Documents

Publication Publication Date Title
TW200739419A (en) Prediction mechanism of a program backward jump instruction
KR102102166B1 (ko) 심드 구조 기반의 쓰레드 분기 관리 장치 및 방법
Volkov Understanding latency hiding on GPUs
US7917789B2 (en) System and method for selecting optimal processor performance levels by using processor hardware feedback mechanisms
RU2008144192A (ru) Многопоточная обработка электронных таблиц с использованием уровней зависимости
JP4526560B2 (ja) プロセッサおよび信号処理方法
US10049043B2 (en) Flushing control within a multi-threaded processor
CA2533741A1 (en) Programmable delayed dispatch in a multi-threaded pipeline
DE602006007825D1 (de) Fehlertolerantes Steuersystem
JP2006338656A5 (zh)
TW201433979A (zh) 在提前執行中資料的選擇性污染
Inci et al. The architectural implications of distributed reinforcement learning on CPU-GPU systems
Puschner Experiments with WCET-oriented programming and the single-path architecture
WO2007008749A3 (en) System and method of controlling multiple program threads within a multithreaded processor
JP6218645B2 (ja) プログラム解析装置及びプログラム解析方法及びプログラム
EP2418582A3 (en) Apparatus and method for thread progress tracking using deterministic progress index
Chen et al. Temperature management for heterogeneous multi-core FPGAs using adaptive evolutionary multi-objective approaches
Zhang et al. Autonomous control of issue queue utilization for simultaneous multi-threading processors
CN105094750B (zh) 一种多线程处理器的返回地址预测方法和装置
WO2006110905A8 (en) System and method of using a predicate value to access a register file
Guo et al. Run-time phase prediction for a reconfigurable VLIW processor
Harris et al. Microarchitecture
Mitrevski et al. On the performance potential of speculative execution based on branch and value prediction
Alkohlani et al. Accurate statistical performance modeling and validation of out-of-order processors using Monte Carlo methods
Srinivasan et al. A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees