TW200736919A - Directory-based data transfer protocol for multiprocessor system - Google Patents

Directory-based data transfer protocol for multiprocessor system

Info

Publication number
TW200736919A
TW200736919A TW095145022A TW95145022A TW200736919A TW 200736919 A TW200736919 A TW 200736919A TW 095145022 A TW095145022 A TW 095145022A TW 95145022 A TW95145022 A TW 95145022A TW 200736919 A TW200736919 A TW 200736919A
Authority
TW
Taiwan
Prior art keywords
processor
directory
data line
multiprocessor system
data transfer
Prior art date
Application number
TW095145022A
Other languages
English (en)
Other versions
TWI386810B (zh
Inventor
Chris Dombrowski
Marcus L Kornegay
Ngan N Pham
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200736919A publication Critical patent/TW200736919A/zh
Application granted granted Critical
Publication of TWI386810B publication Critical patent/TWI386810B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW095145022A 2005-12-30 2006-12-04 多處理器系統以目錄為主之資料傳輸協定 TWI386810B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/322,955 US7404045B2 (en) 2005-12-30 2005-12-30 Directory-based data transfer protocol for multiprocessor system

Publications (2)

Publication Number Publication Date
TW200736919A true TW200736919A (en) 2007-10-01
TWI386810B TWI386810B (zh) 2013-02-21

Family

ID=38214060

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095145022A TWI386810B (zh) 2005-12-30 2006-12-04 多處理器系統以目錄為主之資料傳輸協定

Country Status (4)

Country Link
US (2) US7404045B2 (zh)
JP (1) JP4959279B2 (zh)
CN (1) CN100461136C (zh)
TW (1) TWI386810B (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7404045B2 (en) * 2005-12-30 2008-07-22 International Business Machines Corporation Directory-based data transfer protocol for multiprocessor system
CN101470669B (zh) * 2007-12-28 2011-02-16 无锡江南计算技术研究所 多缓存数据一致性的处理方法及主存处理机
CN101794271B (zh) * 2010-03-31 2012-05-23 华为技术有限公司 多核内存一致性的实现方法和装置
US9274955B2 (en) 2012-08-17 2016-03-01 Futurewei Technologies, Inc. Reduced scalable cache directory
US9298623B2 (en) 2013-09-26 2016-03-29 Globalfoundries Inc. Identifying high-conflict cache lines in transactional memory computing environments
US9292444B2 (en) 2013-09-26 2016-03-22 International Business Machines Corporation Multi-granular cache management in multi-processor computing environments
US9329890B2 (en) 2013-09-26 2016-05-03 Globalfoundries Inc. Managing high-coherence-miss cache lines in multi-processor computing environments
US9298626B2 (en) 2013-09-26 2016-03-29 Globalfoundries Inc. Managing high-conflict cache lines in transactional memory computing environments
US9086974B2 (en) 2013-09-26 2015-07-21 International Business Machines Corporation Centralized management of high-contention cache lines in multi-processor computing environments
US9864584B2 (en) 2014-11-14 2018-01-09 Cavium, Inc. Code generator for programmable network devices

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US5564035A (en) * 1994-03-23 1996-10-08 Intel Corporation Exclusive and/or partially inclusive extension cache system and method to minimize swapping therein
JPH09305489A (ja) * 1996-05-14 1997-11-28 Canon Inc 情報処理システム及びその制御方法
US5892970A (en) * 1996-07-01 1999-04-06 Sun Microsystems, Inc. Multiprocessing system configured to perform efficient block copy operations
US6052762A (en) 1996-12-02 2000-04-18 International Business Machines Corp. Method and apparatus for reducing system snoop latency
US6078997A (en) * 1996-12-09 2000-06-20 Intel Corporation Directory-based coherency system for maintaining coherency in a dual-ported memory system
US5787478A (en) * 1997-03-05 1998-07-28 International Business Machines Corporation Method and system for implementing a cache coherency mechanism for utilization within a non-inclusive cache memory hierarchy
JPH11102321A (ja) * 1997-09-26 1999-04-13 Nec Corp 分散共有メモリ型並列計算機のキャッシュコヒーレンシ制御方式
EP0908825B1 (en) * 1997-10-10 2002-09-04 Bull S.A. A data-processing system with cc-NUMA (cache coherent, non-uniform memory access) architecture and remote access cache incorporated in local memory
JP4689783B2 (ja) * 1999-09-28 2011-05-25 富士通株式会社 分散共有メモリ型並列計算機
US7096323B1 (en) * 2002-09-27 2006-08-22 Advanced Micro Devices, Inc. Computer system with processor cache that stores remote cache presence information
US20040199727A1 (en) * 2003-04-02 2004-10-07 Narad Charles E. Cache allocation
US7310724B2 (en) * 2003-06-30 2007-12-18 Intel Corporation Parallel execution of enhanced EFI based BIOS drivers on a multi-processor or hyper-threading enabled platform
US7249224B2 (en) * 2003-08-05 2007-07-24 Newisys, Inc. Methods and apparatus for providing early responses from a remote data cache
JP4362454B2 (ja) * 2005-04-07 2009-11-11 富士通株式会社 キャッシュコヒーレンス管理装置およびキャッシュコヒーレンス管理方法
US7404045B2 (en) * 2005-12-30 2008-07-22 International Business Machines Corporation Directory-based data transfer protocol for multiprocessor system

Also Published As

Publication number Publication date
US20070156970A1 (en) 2007-07-05
US7925838B2 (en) 2011-04-12
US20080313427A1 (en) 2008-12-18
CN1991794A (zh) 2007-07-04
US7404045B2 (en) 2008-07-22
JP2007183915A (ja) 2007-07-19
CN100461136C (zh) 2009-02-11
JP4959279B2 (ja) 2012-06-20
TWI386810B (zh) 2013-02-21

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