TW200731511A - An electrically erasable and programmable nonvolatile memory device and array and method for operating thereof - Google Patents

An electrically erasable and programmable nonvolatile memory device and array and method for operating thereof

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Publication number
TW200731511A
TW200731511A TW095104733A TW95104733A TW200731511A TW 200731511 A TW200731511 A TW 200731511A TW 095104733 A TW095104733 A TW 095104733A TW 95104733 A TW95104733 A TW 95104733A TW 200731511 A TW200731511 A TW 200731511A
Authority
TW
Taiwan
Prior art keywords
channel
well
memory cell
charge storage
nonvolatile memory
Prior art date
Application number
TW095104733A
Other languages
Chinese (zh)
Other versions
TWI292218B (en
Inventor
Wang Chih-Hsin
Original Assignee
Wang Chih-Hsin
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wang Chih-Hsin filed Critical Wang Chih-Hsin
Priority to TW95104733A priority Critical patent/TWI292218B/en
Publication of TW200731511A publication Critical patent/TW200731511A/en
Application granted granted Critical
Publication of TWI292218B publication Critical patent/TWI292218B/en

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of a n-type conductivity. The well is formed in a semiconductor substrate of a p-type conductivity. The storage transistor comprises a source, a drain, a channel, and a charge storage region. The source and the drain are formed in the well and having the p-type conductivity with the channel of the well defined therebetween. The charge storage region is disposed over and insulated from the channel region by an insulator. Further provided are methods operating the memory cell, including means for injecting electrons from the channel through the insulator onto the charge storage region and means for injecting holes from the injector through the well through the channel through the insulator onto the charge storage region. The memory cell can be implemented in a conventional logic CMOS process.
TW95104733A 2006-02-13 2006-02-13 An electrically erasable and programmable nonvolatile memory device and array and method for operating thereof TWI292218B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW95104733A TWI292218B (en) 2006-02-13 2006-02-13 An electrically erasable and programmable nonvolatile memory device and array and method for operating thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW95104733A TWI292218B (en) 2006-02-13 2006-02-13 An electrically erasable and programmable nonvolatile memory device and array and method for operating thereof

Publications (2)

Publication Number Publication Date
TW200731511A true TW200731511A (en) 2007-08-16
TWI292218B TWI292218B (en) 2008-01-01

Family

ID=45067457

Family Applications (1)

Application Number Title Priority Date Filing Date
TW95104733A TWI292218B (en) 2006-02-13 2006-02-13 An electrically erasable and programmable nonvolatile memory device and array and method for operating thereof

Country Status (1)

Country Link
TW (1) TWI292218B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11164610B1 (en) 2020-06-05 2021-11-02 Qualcomm Incorporated Memory device with built-in flexible double redundancy
US11177010B1 (en) 2020-07-13 2021-11-16 Qualcomm Incorporated Bitcell for data redundancy

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8324940B2 (en) * 2010-04-13 2012-12-04 International Business Machines Corporation Nanowire circuits in matched devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11164610B1 (en) 2020-06-05 2021-11-02 Qualcomm Incorporated Memory device with built-in flexible double redundancy
US11640835B2 (en) 2020-06-05 2023-05-02 Qualcomm Incorporated Memory device with built-in flexible double redundancy
US11177010B1 (en) 2020-07-13 2021-11-16 Qualcomm Incorporated Bitcell for data redundancy

Also Published As

Publication number Publication date
TWI292218B (en) 2008-01-01

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