TW200727198A - Methods and apparatus for graphics processing - Google Patents

Methods and apparatus for graphics processing

Info

Publication number
TW200727198A
TW200727198A TW096104078A TW96104078A TW200727198A TW 200727198 A TW200727198 A TW 200727198A TW 096104078 A TW096104078 A TW 096104078A TW 96104078 A TW96104078 A TW 96104078A TW 200727198 A TW200727198 A TW 200727198A
Authority
TW
Taiwan
Prior art keywords
alus
data
processing
instructions
processing logic
Prior art date
Application number
TW096104078A
Other languages
Chinese (zh)
Other versions
TWI354241B (en
Inventor
Yang Jeff Jiao
Chien-Te Ho
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Publication of TW200727198A publication Critical patent/TW200727198A/en
Application granted granted Critical
Publication of TWI354241B publication Critical patent/TWI354241B/en

Links

Landscapes

  • Executing Machine-Instructions (AREA)
  • Image Processing (AREA)
  • Image Generation (AREA)

Abstract

The present disclosure describes implementations for processing instructions and data across multiple Arithmetic Logic Units (ALUs). In one implementation, a graphics processing apparatus comprises a plurality of ALUs configured to process independent instructions in parallel. Pre-processing logic is configured to receive instructions and associated data to be directed to one of the plurality of ALUs for processing from a register file, the pre-processing logic being configured to selectively format received instructions for delivery to a plurality of the ALUs. In addition, post-processing logic is configured to receive data output from the plurality of the ALUs and deliver the received data to the register file for write-back, the post-processing logic being configured to selectively format data output from a plurality of the ALUs for delivery to the register file as though the data had been output by a single ALU.
TW96104078A 2006-02-06 2007-02-05 Methods and apparatus for graphics processing TWI354241B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US76565406P 2006-02-06 2006-02-06

Publications (2)

Publication Number Publication Date
TW200727198A true TW200727198A (en) 2007-07-16
TWI354241B TWI354241B (en) 2011-12-11

Family

ID=46727943

Family Applications (1)

Application Number Title Priority Date Filing Date
TW96104078A TWI354241B (en) 2006-02-06 2007-02-05 Methods and apparatus for graphics processing

Country Status (1)

Country Link
TW (1) TWI354241B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI610231B (en) * 2014-12-23 2018-01-01 英特爾股份有限公司 Apparatus and method for vector horizontal logical instruction
TWI689866B (en) * 2011-12-30 2020-04-01 英特爾股份有限公司 Simd variable shift and rotate using control manipulation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI689866B (en) * 2011-12-30 2020-04-01 英特爾股份有限公司 Simd variable shift and rotate using control manipulation
TWI610231B (en) * 2014-12-23 2018-01-01 英特爾股份有限公司 Apparatus and method for vector horizontal logical instruction

Also Published As

Publication number Publication date
TWI354241B (en) 2011-12-11

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