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Application filed by Via Tech IncfiledCriticalVia Tech Inc
Publication of TW200727198ApublicationCriticalpatent/TW200727198A/en
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Publication of TWI354241BpublicationCriticalpatent/TWI354241B/en
The present disclosure describes implementations for processing instructions and data across multiple Arithmetic Logic Units (ALUs). In one implementation, a graphics processing apparatus comprises a plurality of ALUs configured to process independent instructions in parallel. Pre-processing logic is configured to receive instructions and associated data to be directed to one of the plurality of ALUs for processing from a register file, the pre-processing logic being configured to selectively format received instructions for delivery to a plurality of the ALUs. In addition, post-processing logic is configured to receive data output from the plurality of the ALUs and deliver the received data to the register file for write-back, the post-processing logic being configured to selectively format data output from a plurality of the ALUs for delivery to the register file as though the data had been output by a single ALU.
TW96104078A2006-02-062007-02-05Methods and apparatus for graphics processing
TWI354241B
(en)
Programmable digital signal processor having a clustered simd microarchitecture including a complex short multiplier and an independent vector load unit