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Application filed by Powerchip Semiconductor CorpfiledCriticalPowerchip Semiconductor Corp
Priority to TW94146079ApriorityCriticalpatent/TWI285961B/en
Publication of TW200725914ApublicationCriticalpatent/TW200725914A/en
Application grantedgrantedCritical
Publication of TWI285961BpublicationCriticalpatent/TWI285961B/en
A manufacturing method of floating gate layer is described. First, a substrate is provided, and a mask layer is formed on the substrate. Then, some trenches are formed in the mask layer and the substrate. Later on, an insulating layer is formed on the mask layer and fills the trenches, and the top surface of the insulating layer is higher than that of the mask layer. Next, part of the insulating layer is removed to form some first openings which expose the mask layer. After that, the mask layer in the first opening is removed to expose the substrate. Then, a tunneling dielectric layer is formed on the substrate. A floating gate layer is formed on the tunneling dielectric layer to fill these first openings.
TW94146079A2005-12-232005-12-23Method of manufacturing floating gate layer and non-volatile memory
TWI285961B
(en)
Nonvolatile memory fabrication methods in which a dielectric layer underlying a floating gate layer is spaced from an edge of an isolation trench and/or an edge of the floating gate layer