TW200725520A - Analog output buffer circuit for flat panel display - Google Patents

Analog output buffer circuit for flat panel display

Info

Publication number
TW200725520A
TW200725520A TW094144667A TW94144667A TW200725520A TW 200725520 A TW200725520 A TW 200725520A TW 094144667 A TW094144667 A TW 094144667A TW 94144667 A TW94144667 A TW 94144667A TW 200725520 A TW200725520 A TW 200725520A
Authority
TW
Taiwan
Prior art keywords
switch
buffer circuit
period
output buffer
flat panel
Prior art date
Application number
TW094144667A
Other languages
Chinese (zh)
Other versions
TWI299847B (en
Inventor
Huang-Chung Cheng
Ya-Hsiang Tai
Bo-Ting Chen
Chun-Hsiang Fang
Original Assignee
Chunghwa Picture Tubes Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chunghwa Picture Tubes Ltd filed Critical Chunghwa Picture Tubes Ltd
Priority to TW94144667A priority Critical patent/TWI299847B/en
Publication of TW200725520A publication Critical patent/TW200725520A/en
Application granted granted Critical
Publication of TWI299847B publication Critical patent/TWI299847B/en

Links

Landscapes

  • Liquid Crystal Display Device Control (AREA)
  • Electronic Switches (AREA)

Abstract

An analog output buffer circuit for a flat panel display is provided for improving an output signal distortion. The circuit includes a transistor, a current source, an input capacitor, an upper switch, a lower switch, a first switch, a second switch and a third switch. In which, the transistor and the current source are electrically connected in series between a first power supply and a second power supply. The current source provides a compensatory current for the transistor when a leakage current occurs. The upper switch and the first switch are turned on during the first period, and the lower switch and the second switch are turn on during the second period, in which the second period is after the first period. Those switches eliminate the drawback of different voltage levels between the input signal and the output signal obtained from the output buffer circuit inputted by the input signal.
TW94144667A 2005-12-16 2005-12-16 Analog output buffer circuit for flat panel display TWI299847B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94144667A TWI299847B (en) 2005-12-16 2005-12-16 Analog output buffer circuit for flat panel display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94144667A TWI299847B (en) 2005-12-16 2005-12-16 Analog output buffer circuit for flat panel display

Publications (2)

Publication Number Publication Date
TW200725520A true TW200725520A (en) 2007-07-01
TWI299847B TWI299847B (en) 2008-08-11

Family

ID=45069808

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94144667A TWI299847B (en) 2005-12-16 2005-12-16 Analog output buffer circuit for flat panel display

Country Status (1)

Country Link
TW (1) TWI299847B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI678649B (en) * 2018-03-27 2019-12-01 大陸商北京集創北方科技股份有限公司 Common voltage decoupling circuit for touch receiving, and integrated driver and touch display panel using touch display thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI678649B (en) * 2018-03-27 2019-12-01 大陸商北京集創北方科技股份有限公司 Common voltage decoupling circuit for touch receiving, and integrated driver and touch display panel using touch display thereof

Also Published As

Publication number Publication date
TWI299847B (en) 2008-08-11

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees