TW200719460A - Chip package substrate - Google Patents

Chip package substrate

Info

Publication number
TW200719460A
TW200719460A TW094140050A TW94140050A TW200719460A TW 200719460 A TW200719460 A TW 200719460A TW 094140050 A TW094140050 A TW 094140050A TW 94140050 A TW94140050 A TW 94140050A TW 200719460 A TW200719460 A TW 200719460A
Authority
TW
Taiwan
Prior art keywords
conductive
pad
package substrate
chip package
pairs
Prior art date
Application number
TW094140050A
Other languages
Chinese (zh)
Other versions
TWI281244B (en
Inventor
Chi-Chih Lin
Bo Sun
Hung-Jen Wang
Original Assignee
Taiwan Solutions Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Solutions Systems Corp filed Critical Taiwan Solutions Systems Corp
Priority to TW94140050A priority Critical patent/TWI281244B/en
Application granted granted Critical
Publication of TWI281244B publication Critical patent/TWI281244B/en
Publication of TW200719460A publication Critical patent/TW200719460A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Chip package substrate includes multitudes of pairs of conductive connection pad. Two conductive connection pads are positioned oppositely from a distance smaller than a side of a chip. An insulating layer covers the pairs of conductive connect pad to expose a portion of surface of each conductive connect pad. The conductive solder pad covers the exposed surface of each conductive connect pad.
TW94140050A 2005-11-15 2005-11-15 Chip package substrate TWI281244B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94140050A TWI281244B (en) 2005-11-15 2005-11-15 Chip package substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94140050A TWI281244B (en) 2005-11-15 2005-11-15 Chip package substrate

Publications (2)

Publication Number Publication Date
TWI281244B TWI281244B (en) 2007-05-11
TW200719460A true TW200719460A (en) 2007-05-16

Family

ID=38741667

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94140050A TWI281244B (en) 2005-11-15 2005-11-15 Chip package substrate

Country Status (1)

Country Link
TW (1) TWI281244B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI409924B (en) * 2007-09-12 2013-09-21 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof

Also Published As

Publication number Publication date
TWI281244B (en) 2007-05-11

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees