TW200717537A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
TW200717537A
TW200717537A TW095134511A TW95134511A TW200717537A TW 200717537 A TW200717537 A TW 200717537A TW 095134511 A TW095134511 A TW 095134511A TW 95134511 A TW95134511 A TW 95134511A TW 200717537 A TW200717537 A TW 200717537A
Authority
TW
Taiwan
Prior art keywords
pair
memory device
semiconductor memory
lines
local lines
Prior art date
Application number
TW095134511A
Other languages
Chinese (zh)
Other versions
TWI310566B (en
Inventor
Dong-Keun Kim
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200717537A publication Critical patent/TW200717537A/en
Application granted granted Critical
Publication of TWI310566B publication Critical patent/TWI310566B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)

Abstract

A semiconductor memory device can reduce a data writing time. The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines. A pair of first local lines id connected to the pair of bit lines by a first switching unit. A pair of second local lines is connected to the pair of first local lines by a second switching unit. A writing driver drives the second local lines using a normal-driving voltage in response to a data signal through a global line. The writing driver drives the second local lines using an over-driving voltage having a higher level than that of the normal-driving voltage during a predetermined period.
TW095134511A 2005-09-29 2006-09-19 Semiconductor memory device TWI310566B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20050091545 2005-09-29
KR1020060049003A KR100772721B1 (en) 2005-09-29 2006-05-30 Semiconductor memory device

Publications (2)

Publication Number Publication Date
TW200717537A true TW200717537A (en) 2007-05-01
TWI310566B TWI310566B (en) 2009-06-01

Family

ID=37959249

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095134511A TWI310566B (en) 2005-09-29 2006-09-19 Semiconductor memory device

Country Status (3)

Country Link
KR (1) KR100772721B1 (en)
CN (1) CN100580807C (en)
TW (1) TWI310566B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100939118B1 (en) * 2008-06-30 2010-01-28 주식회사 하이닉스반도체 Write driver of phase change memory device
JP5760829B2 (en) * 2011-08-09 2015-08-12 富士通セミコンダクター株式会社 Static RAM
KR101882854B1 (en) * 2011-12-21 2018-07-31 에스케이하이닉스 주식회사 Data delivery circuit and semiconductor memory device including the same
KR102166731B1 (en) * 2013-05-31 2020-10-16 에스케이하이닉스 주식회사 Circuit for transfering data and memory including the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4111371B2 (en) * 2000-10-25 2008-07-02 株式会社ハイニックスセミコンダクター Semiconductor memory device and write driving method thereof
KR20040102238A (en) * 2003-05-27 2004-12-04 삼성전자주식회사 Semiconductor memory device having improved write driver
KR100502667B1 (en) * 2003-10-29 2005-07-21 주식회사 하이닉스반도체 Write driver of a semiconductor memory device

Also Published As

Publication number Publication date
CN100580807C (en) 2010-01-13
KR20070036632A (en) 2007-04-03
CN1941187A (en) 2007-04-04
KR100772721B1 (en) 2007-11-02
TWI310566B (en) 2009-06-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees